CONTEST CHALLENGE TASK ROUND #3

Design a 2-bit up-down counter based on the design in up-counter.sch below. The up-down counter must increment from 0 to 3 and then decrement to 0 again (count sequence: 0,1,2,3,0,3,2,1,0,1,2....) and so on. The counter's mode is controlled by the signal TLINE, shown below. When TLINE is high, the counter is in increment mode, and when TLINE is low, it is in decrement mode.

Copy and paste the new circuitry and the Timing Diagram (obtained via the Analysis/Digital Timing Analysis menu) into a document and email to us. You may want to download and edit the circuit up-counter.sch, which already includes the CLOCK and TLINE waveforms and the two flip-flops needed.

Up-counter

Result of Digital Timing Analysis of Up-counter 

 
Copy and paste the new circuitry and the Timing Diagram (obtained via the Analysis/Digital Timing Analysis menu) into a document and email to us. You may want to download and edit the circuit up-counter.sch, which already includes the CLOCK and TLINE waveforms and the two flip-flops needed.

Round  #1
Round  #2