Creating a Macro from a VHDL code

Using Hardware Description Languages in TINA, Part 1: Creating Macros from a VHDL code

Hardware Description Languages (HDL) are powerful tools to describe and simulate complex electronic devices.

In this tutorial video we will show how you can create a macro from a VHDL (.vhd) code and use     in TINA. You can create macros from Verilog, Verilog-A and Verilog-AMS files in a similar way.

Watch our tutorial video to see how  you can create a macro from a VHDL (.vhd) code and use         in TINA.

 

 UsinghardwaredescriptionlanguagesinTINApart1-blog

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Michael Koltai
www.tina.com