OBSS¸Circuit DescriptionV1.1010/02/94 20:07 CET.Component & analysis parameters of a circuit.TINA 12.0.0.0 SFB(c) Copyright 1993,94,95,96 DesignSoft Inc. All rights reserved.? $Circuit$ÿÿÿÿð?„V§`V§ ÿÿArialo`c #How to program the microcontroller:1. Build project in DAVEX2. Pack together the .hex and .elf files into a .zip (usually found in the Debug folder)&3. Click on the microcontroller symbol"4. Click on the "MCU-code" details5. Select "Upload"'6. Select the .zip file created earlier7. Click "Upload" 8. Click "OK"Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_5DB5820A-BBC6-46F4-93A1-6AF4DC8DCFC5ìaý`aý ÿÿArialo`cMotor:Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_4E5C4F60-25CE-4658-88B1-B60F97378006Las`as ÿÿArialÿ6\a(Other circuits,http://www.infineon.com/ifxdesigner)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_9ABD9F3A-A6FD-425F-8FC4-853D2812F3AEXa3`a3 ÿÿArialÿ<\a(Development platform: DAVE"!,http://www.infineon.com/dave)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_0C041C33-F30B-4C14-A747-82465E7BAF7Caó`aó ÿÿArialÿ’\a(Reference manual: XMC1100 AB-Step,http://www.infineon.com/dgdl/Infineon-xmc1100-AB_rm-UM-v01_02-EN.pdf?fileId=5546d46249cd1014014a0a8438a65e29)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_AFE1A7BF-791F-45A1-A4A9-579A7D4A7514xaÓ`aÓ ÿÿArialÿL\a(Product info: XMC1100-T038F0064 AB,http://www.infineon.com/cms/en/product/microcontroller/32-bit-industrial-microcontroller-based-on-arm-registered-cortex-registered-m/32-bit-xmc1000-industrial-microcontroller-arm-registered-cortex-registered-m0/XMC1100-T038F0064+AB/productType.html?productType=5546d4624cb7f111014d4791f791675e)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_DB2EE3B6-8EC0-4679-9E33-76B55C613AEF,aS`aS ÿÿArialÿ&\a(Buy online,tdl://file.shoppingcart)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_8E8D6933-82D4-4F8F-B622-268D5AD306EAXa+`a+ ÿÿArialo`c TThis circuit is used to drive brushless DC motors in a sensorless configuration via Mback-emf detection and block commutation. The maximum speed is determined by Othe motor parameters and the computation time by the microcontroller used. The *solution has been tested up to 18.000 rpm.LXMC1000 microcontrollers bring together the ARM® Cortex®-M0 core with marketTproven and differentiating peripherals in a leading-edge 65nm manufacturing process.VXMC1000 is the number one choice to bring traditional 8-bit designs to the next level.KThe IR2301 is a high voltage, high speed power MOSFET and IGBT driver with 9independent high and low side referenced output channels.Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_708535BF-A97F-498A-A67A-47A7AFBD9E09Ba`a ÿÿArialo`c1PINUS BOARD V2 with XMC1100, IR2301 and BSC0925NDSymbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_57EBA347-A14F-45C3-8B1B-8DF65DCAA2AFúVR`VR ÿÿArialo`c Need support?Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_0CE178D7-42C1-4D21-B2BA-C1B3B4035E13PVt`Vt ÿÿArialÿ8\a(Technical Assistance,http://www.infineon.com/support)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_0317A7C5-1520-4262-BBBD-9BADB1497FFD0††`†† ÿÿArialÿÿÿ(\a(Simulate Transient,tdl://analysis.tr)Symbol«7zà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_B0E46086-C8A4-468C-837C-42A6FC22EFBFV`V ÿÿArialo`c&1. Wanna try it out? Click on simulate(2. Click on circuit components to change'3. If you like what you see, buy online4. Enjoy other circuitsSymbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_000A19B2-A8AC-4419-8D33-CAA894D7D52Bªa`a ÿÿArialÿe\a(Family: 32-bit XMC1000 Industrial Microcontroller ARM® Cortex®-M0,http://www.infineon.com/xmc1000)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_2849BC92-BD03-4276-844A-B86CBF85DFEAðÕ`Õ ÿÿArialo`c HighsideSymbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_622ED279-0FEE-4602-963D-282A14C93A62îÕŸ`ÕŸ ÿÿArialo`c LowsideSymbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_995EDA95-BDD7-48C4-846E-5F34ECB95555èa“`a“ ÿÿArialÿ\a(Product info: IR2301,http://www.infineon.com/cms/de/product/power/motor-control-and-gate-driver-ics/non-isolated-gate-driver-ics-and-controllers/general-purpose-gate-driver-ics-industrial/IR2301/productType.html?productType=5546d462533600a401533d23ed465b7f)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_5DB88805-1B4A-4172-B924-270BE4175352ša³`a³ ÿÿArialÿÝ\a(Product info: BSC0925ND ,http://www.infineon.com/cms/de/product/power/power-mosfet/20v-300v-n-channel-power-mosfet/20v-30v-n-channel-power-mosfet/BSC0925ND/productType.html?productType=db3a304436c50b180136c61e6033018e)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_897A74C3-3C1E-4F0B-872D-1277267F913A¸at`at ÿÿArialÿl\a(Infineon s solutions for multicopters,http://www.infineon.com/cms/en/applications/consumer/multicopters/)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_FB94E56D-F3FB-4117-AAB2-FF3C20A208FC8aS`aS ÿÿArialÿ¬\a(MOSFET Finder,http://www.infineon.com/cms/en/product/solutionFinder.html?channel=db3a30433cabdd35013ccebb4e4849ae#!showAllParameters=false&sort=group&sortField=SMALLEST)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_BEC0B177-6BD0-4071-A99F-55D4648AFD80Ix p x p ÿÿÿÿ%96F4F578-3B10-43CF-8769-C5D69D91F8C4Ixpxpÿÿÿÿ%37C810B5-F54D-4028-B528-35D2947769D9Ix€p€x€p€ÿÿÿÿ%3DC28245-5610-4293-A1B7-5CF269E9A375Ixpppxpppÿÿÿÿ%6AE3314F-C1C9-4879-A2A0-1E6EB1B71516Ix`p`x`p`ÿÿÿÿ%0C559C83-C1A7-4109-A893-1384D3D6A827IxPpPxPpPÿÿÿÿ%6A535846-53B7-4B44-9955-5ADCDD28EBD7Ix@p@x@p@ÿÿÿÿ%1FAAEF37-EDBD-4167-8C1A-2ED7B3C15135Ix0p0x0p0ÿÿÿÿ%01DAA024-6922-4521-869C-031F6D77977CIx p x p ÿÿÿÿ%9406274F-5375-4F70-BDE5-7690B6662B81Ixpxpÿÿÿÿ%8F7DD2DF-ADF2-4D73-B633-9960FB4DFA99Ih°h¸h°h¸ÿÿÿÿ%F08FA367-3402-4CE3-9B40-6FB472880E97Ihˆh€hˆh€ÿÿÿÿ%E7D9A549-A070-4B52-9E9F-1BDEE1AD5D6CMxhˆxˆhˆÿÿÿÿ%AF6904F7-7F2D-4160-B6E3-1006295E4FE2Ix¸h¸x¸h¸ÿÿÿÿ%55F852A0-473B-4D98-8F13-A8EA95FB7D38Ih(h h(h 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P0.3(P0_3),P0.4(P0_4),P0.5(P0_5),P0.6(P0_6),P0.7(P0_7) -- -- ;:-- P0.8(P0_8),P0.9(P0_9),P0.10(P0_10),P0.11(P0_11),>-- P0.12(P0_12),P0.13(P0_13),P0.14(P0_14),P0.15(P0_15), -- TSE -- ;A-- P1.0(P1_0),P1.1(P1_1),P1.2(P1_2),P1.3(P1_3),P1.4(P1_4),*-- P1.5(P1_5),P2.0(P2_0),P2.1(P2_1) -- ;A-- P2.2(P2_2),P2.3(P2_3),P2.4(P2_4),P2.5(P2_5),P2.6(P2_6),8-- P2.7(P2_7),P2.8(P2_8),P2.9(P2_9),P2.10(P2_10),-- P2.11(P2_11) -- ;-- Description: ARMCORTEX;-- Device: XMC1100_T038;-- !-- TINA HDL Macro Description End%------------------------------------ library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;use mcu.mcu_functions.all;entity XMC1100_T038 is port( clk : in std_logic; vss : in std_logic; vdd : in std_logic; p0_0 : inout std_logic; p0_1 : inout std_logic; p0_2 : inout std_logic; p0_3 : inout std_logic; p0_4 : inout std_logic; p0_5 : inout std_logic; p0_6 : inout std_logic; p0_7 : inout std_logic; p0_8 : inout std_logic; p0_9 : inout std_logic;! p0_10 : inout std_logic;! p0_11 : inout std_logic;! p0_12 : inout std_logic;! p0_13 : inout std_logic;! p0_14 : inout std_logic;! p0_15 : inout std_logic; tse : inout std_logic; p1_0 : inout std_logic; p1_1 : inout std_logic; p1_2 : inout std_logic; p1_3 : inout std_logic; p1_4 : inout std_logic; p1_5 : inout std_logic; p2_0 : inout std_logic; p2_1 : inout std_logic; p2_2 : inout std_logic; p2_3 : inout std_logic; p2_4 : inout std_logic; p2_5 : inout std_logic; p2_6 : inout std_logic; p2_7 : inout std_logic; p2_8 : inout std_logic; p2_9 : inout std_logic;! p2_10 : inout std_logic; p2_11 : inout std_logic );end XMC1100_T038;#architecture RTL of XMC1100_T038 isbegin ARMCORTEX_model: process ( : vss,vdd,p0_0,p0_1,p0_2,p0_3,p0_4,p0_5,p0_6,p0_7,< p0_8,p0_9,p0_10,p0_11,p0_12,p0_13,p0_14,p0_15,tse,2 p1_0,p1_1,p1_2,p1_3,p1_4,p1_5,p2_0,p2_1,= p2_2,p2_3,p2_4,p2_5,p2_6,p2_7,p2_8,p2_9,p2_10,p2_11 )  begin _ARM_class( clk ); end process;end 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:00000001FF noname.lst noname.hex noname.asm€„.AU1"main.cG`#include //Declarations from DAVE Code Generation (includes SFR declaration) int main(void) { DAVE_STATUS_t status; uint32_t delay_count; uint32_t delay=1000;f status = DAVE_Init(); //(DAVE_STATUS_t)DIGITAL_IO_Init(&DIGITAL_IO_0) is called within DAVE_Init() // output init/ DIGITAL_IO_SetOutputHigh(&DIGITAL_IO_H_U);. DIGITAL_IO_SetOutputLow(&DIGITAL_IO_H_V);. DIGITAL_IO_SetOutputLow(&DIGITAL_IO_H_W);/ DIGITAL_IO_SetOutputHigh(&DIGITAL_IO_L_W);. DIGITAL_IO_SetOutputLow(&DIGITAL_IO_L_U);. DIGITAL_IO_SetOutputLow(&DIGITAL_IO_L_V);$ if(status == DAVE_STATUS_SUCCESS) {4 XMC_DEBUG("DAVE Apps initialization success\n"); } else {L XMC_DEBUG(("DAVE Apps initialization failed with status %d\n", status)); while(1U) { } } while(1U) { PWM_CCU4_Stop(&PWM_CCU4_0);D DIGITAL_IO_ToggleOutput(&DIGITAL_IO_H_U); //toggles level at pinD DIGITAL_IO_ToggleOutput(&DIGITAL_IO_H_V); //toggles level at pin9 for(delay_count = 0;delay_count * 2015-08-28:, * - Added CLOCK_XMC1_Init conditionally * * @endcond * */x/*********************************************************************************************************************** * HEADER FILESx **********************************************************************************************************************/#include "DAVE.h"x/*********************************************************************************************************************** * API IMPLEMENTATIONx **********************************************************************************************************************/P/*******************************************************************************< * @brief This function initializes the APPs Init Functions. * * @param[in] None * * @return DAVE_STATUS_t
P ******************************************************************************/DAVE_STATUS_t DAVE_Init(void){ DAVE_STATUS_t init_status; $ init_status = DAVE_STATUS_SUCCESS;2 /** @Initialization of APPs Init Functions */A init_status = (DAVE_STATUS_t)CLOCK_XMC1_Init(&CLOCK_XMC1_0);) if (init_status == DAVE_STATUS_SUCCESS) {B /** Initialization of DIGITAL_IO APP instance DIGITAL_IO_H_U */A init_status = (DAVE_STATUS_t)DIGITAL_IO_Init(&DIGITAL_IO_H_U);  } ) if (init_status == DAVE_STATUS_SUCCESS) {B /** Initialization of DIGITAL_IO APP instance DIGITAL_IO_H_V */A init_status = (DAVE_STATUS_t)DIGITAL_IO_Init(&DIGITAL_IO_H_V);  } ) if (init_status == DAVE_STATUS_SUCCESS) {B /** Initialization of DIGITAL_IO APP instance DIGITAL_IO_H_W */A init_status = (DAVE_STATUS_t)DIGITAL_IO_Init(&DIGITAL_IO_H_W);  } ) if (init_status == DAVE_STATUS_SUCCESS) {B /** Initialization of DIGITAL_IO APP instance DIGITAL_IO_L_U */A init_status = (DAVE_STATUS_t)DIGITAL_IO_Init(&DIGITAL_IO_L_U);  } ) if (init_status == DAVE_STATUS_SUCCESS) {B /** Initialization of DIGITAL_IO APP instance DIGITAL_IO_L_W */A init_status = (DAVE_STATUS_t)DIGITAL_IO_Init(&DIGITAL_IO_L_W);  } ) if (init_status == DAVE_STATUS_SUCCESS) {B /** Initialization of DIGITAL_IO APP instance DIGITAL_IO_L_V */A init_status = (DAVE_STATUS_t)DIGITAL_IO_Init(&DIGITAL_IO_L_V);  } ) if (init_status == DAVE_STATUS_SUCCESS) {< /** Initialization of PWM_CCU4 APP instance PWM_CCU4_0 */; init_status = (DAVE_STATUS_t)PWM_CCU4_Init(&PWM_CCU4_0);  } ) if (init_status == DAVE_STATUS_SUCCESS) {@ /** Initialization of DIGITAL_IO APP instance DIGITAL_IO_0 */? init_status = (DAVE_STATUS_t)DIGITAL_IO_Init(&DIGITAL_IO_0);  }  return init_status;#} /** End of function DAVE_Init */dave.hW/** * @condx *********************************************************************************************************************** */ * Copyright (c) 2015, Infineon Technologies AG * All rights reserved. *r * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: *v * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. *n * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and thee * following disclaimer in the documentation and/or other materials provided with the distribution. *r * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promoteS * products derived from this software without specific prior written permission. *u * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,t * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AREv * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,r * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ORt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,s * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THEK * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *q * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes5 * with Infineon Technologies AG (dave@infineon.com).x *********************************************************************************************************************** * * Change History * -------------- * * 2014-06-16: * - Initial version
* @endcond * */#ifndef _DAVE_H_#define _DAVE_H_x/*********************************************************************************************************************** * HEADER FILESx **********************************************************************************************************************/&/** #include DAVE APP Header files. */#include "xmc_common.h" "#include "DIGITAL_IO/digital_io.h" "#include "CLOCK_XMC1/clock_xmc1.h" $#include "GLOBAL_CCU4/global_ccu4.h" #include "PWM_CCU4/pwm_ccu4.h"  w/********************************************************************************************************************** * ENUMSx **********************************************************************************************************************/typedef enum DAVE_STATUS{ DAVE_STATUS_SUCCESS = 0, DAVE_STATUS_FAILURE,! DAVE_STATUS_ALREADY_INITIALIZED} DAVE_STATUS_t;x/************************************************************************************************************************ API PROTOTYPESx***********************************************************************************************************************/#ifdef __cplusplus extern "C" {#endifDAVE_STATUS_t DAVE_Init(void);#ifdef __cplusplus}#endif#endif /** ifndef _DAVE_H_ */dave_common.h;O/**************************************************************************//** *D * Copyright (C) 2014 Infineon Technologies AG. All rights reserved. *N * Infineon Technologies AG (Infineon) is supplying this software for use with * Infineon's microcontrollers.H * This file can be freely distributed within development tools that are$ * supporting such microcontrollers. *N * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIEDE * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OFO * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.O * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,7 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. *P********************************************************************************P** **P** **P** PLATFORM : Infineon **P** **P** COMPILER : Compiler Independent **P** **P** MODIFICATION DATE : Dec 27, 2014 **P** **P*******************************************************************************//** * @file DAVE_common.h *V * @brief This file contains all app related public data structures,enums and function * prototypes * * Revision History% * 27 Dec 2014 v0.1.0 Initial Version * */#ifndef _DAVE_COMMON_H_#define _DAVE_COMMON_H_P/*******************************************************************************P** @Project Includes **P*******************************************************************************/P/*******************************************************************************P** Global data structures **P*******************************************************************************/typedef struct DAVE_APP_VERSION{ uint8_t major; uint8_t minor; uint8_t patch;} DAVE_APP_VERSION_t;P/*******************************************************************************P** @Prototypes Of Global Functions **P*******************************************************************************/%#endif /** ifndef _DAVE_COMMON_H_ */ clock_xmc1.c¨/** * @file clock_xmc1.c * @date 2015-05-04  * * NOTE:w * This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated. * * @condx ***********************************************************************************************************************F * CLOCK_XMC1 v4.0.14 - APP to configure System and Peripheral Clocks. */ * Copyright (c) 2015, Infineon Technologies AG/ * All rights reserved. / * } * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the # * following conditions are met: P * y * Redistributions of source code must retain the above copyright notice, this list of conditions and the following ( * disclaimer.  * r * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the j * following disclaimer in the documentation and/or other materials provided with the distribution.  * s * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote T * products derived from this software without specific prior written permission. / * w * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, w * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE x * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, z * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR z * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, v * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE O * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. P * x * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes = * with Infineon Technologies AG (dave@infineon.com). x *********************************************************************************************************************** * * Change History * -------------- * 2015-02-16:) * - Initial version for DAVEv4.
 * 2015-05-08:9 * - Typo mistake corrected in _GetAppVersion().
 * 2015-09-22:T * - CLOCK_XMC1_Init API and CLOCK_XMC1_SetMCLKFrequency APIs are provided.
 * 2015-10-19:? * - non-weak OSCHP_GetFrequency function is provided.
K * - CLOCK_XMC1_IsDCO1ExtRefCalibrationReady function is provided.
* @endcond  * */ x/***********************************************************************************************************************u * HEADER FILES x **********************************************************************************************************************/#include "clock_xmc1.h"x/*********************************************************************************************************************** * MACROSx **********************************************************************************************************************/x/*********************************************************************************************************************** * LOCAL DATAx **********************************************************************************************************************/x/*********************************************************************************************************************** * LOCAL ROUTINESx **********************************************************************************************************************/x/************************************************************************************************************************ API IMPLEMENTATIONx***********************************************************************************************************************/)/* API to retrieve version of the APP */1DAVE_APP_VERSION_t CLOCK_XMC1_GetAppVersion(void){ DAVE_APP_VERSION_t version;4 version.major = (uint8_t)CLOCK_XMC1_MAJOR_VERSION;4 version.minor = (uint8_t)CLOCK_XMC1_MINOR_VERSION;4 version.patch = (uint8_t)CLOCK_XMC1_PATCH_VERSION; return (version);}/*2 * API to initialize the CLOCK_XMC1 APP Interrupts */9CLOCK_XMC1_STATUS_t CLOCK_XMC1_Init(CLOCK_XMC1_t *handle){9 CLOCK_XMC1_STATUS_t status = CLOCK_XMC1_STATUS_SUCCESS;D CLOCK_XMC1_STATUS_t loci_event_status = CLOCK_XMC1_STATUS_SUCCESS;F CLOCK_XMC1_STATUS_t stdbyclkfail_status = CLOCK_XMC1_STATUS_SUCCESS;N CLOCK_XMC1_STATUS_t loss_ext_clock_event_status = CLOCK_XMC1_STATUS_SUCCESS;G CLOCK_XMC1_STATUS_t dco1_out_sync_status = CLOCK_XMC1_STATUS_SUCCESS;# if (handle->init_status == false) {##ifdef CLOCK_XMC1_INTERRUPT_ENABLEDU status = (CLOCK_XMC1_STATUS_t)GLOBAL_SCU_XMC1_Init(handle->global_scu_handleptr);, if (CLOCK_XMC1_STATUS_SUCCESS == status) {$#ifdef CLOCK_XMC1_LOCI_EVENT_ENABLED/ /* Initialization of CPU_CTRL_XMC1 APP */P loci_event_status = (CLOCK_XMC1_STATUS_t)GLOBAL_SCU_XMC1_RegisterCallback(W GLOBAL_SCU_XMC1_EVENT_LOCI, handle->callback_function_loci);+ /* Enable Loss of DCO1 Clock Event */@ XMC_SCU_INTERRUPT_EnableEvent(GLOBAL_SCU_XMC1_EVENT_LOCI);#endif,#ifdef CLOCK_XMC1_STDBYCLKFAIL_EVENT_ENABLED/ /* Initialization of CPU_CTRL_XMC1 APP */R stdbyclkfail_status = (CLOCK_XMC1_STATUS_t)GLOBAL_SCU_XMC1_RegisterCallback(i GLOBAL_SCU_XMC1_EVENT_STDBYCLKFAIL, handle->callback_function_stdbyclkfail);. /* Enable Standby Clock Failure Event */H XMC_SCU_INTERRUPT_EnableEvent(GLOBAL_SCU_XMC1_EVENT_STDBYCLKFAIL);#endif#if (UC_SERIES == XMC14).#ifdef CLOCK_XMC1_LOSS_EXT_CLOCK_EVENT_ENABLED/ /* Initialization of CPU_CTRL_XMC1 APP */Z loss_ext_clock_event_status = (CLOCK_XMC1_STATUS_t)GLOBAL_SCU_XMC1_RegisterCallback(u GLOBAL_SCU_XMC1_EVENT_LOSS_EXT_CLOCK, handle->callback_function_loss_ext_clock);6 /* Enable Loss of external OSC_HP clock Event */J XMC_SCU_INTERRUPT_EnableEvent(GLOBAL_SCU_XMC1_EVENT_LOSS_EXT_CLOCK);#endif-#ifdef CLOCK_XMC1_DCO1_OUT_SYNC_EVENT_ENABLED/ /* Initialization of CPU_CTRL_XMC1 APP */S dco1_out_sync_status = (CLOCK_XMC1_STATUS_t)GLOBAL_SCU_XMC1_RegisterCallback(l GLOBAL_SCU_XMC1_EVENT_DCO1_OUT_SYNC, handle->callback_function_dco1_out_sync);* /* Enable DCO1 Out of SYNC Event */I XMC_SCU_INTERRUPT_EnableEvent(GLOBAL_SCU_XMC1_EVENT_DCO1_OUT_SYNC);#endif#endif }#endifd status = (CLOCK_XMC1_STATUS_t)(((uint32_t)loci_event_status) | ((uint32_t)stdbyclkfail_status) |i ((uint32_t)loss_ext_clock_event_status) | ((uint32_t)dco1_out_sync_status));, if (CLOCK_XMC1_STATUS_SUCCESS == status) {! handle->init_status = true; } } return (status);}:/* API for ramping up/down the system clock frequency */3void CLOCK_XMC1_SetMCLKFrequency(uint32_t freq_khz){+ XMC_SCU_CLOCK_SetMCLKFrequency(freq_khz);}#if (CLOCK_XMC1_OSCHP_ENABLED)C/* API to retrieve high precision external oscillator frequency */!uint32_t OSCHP_GetFrequency(void){& return (CLOCK_XMC1_OSCHP_FREQUENCY);}#endif)#if (CLOCK_XMC1_DCO1_CALIBRATION_ENABLED)F/* API to check whether DCO1 is synchronized to the XTAL frequency */2bool CLOCK_XMC1_IsDCO1ExtRefCalibrationReady(void){8 return (XMC_SCU_CLOCK_IsDCO1ExtRefCalibrationReady());}#endif clock_xmc1.h]/** * @file clock_xmc1.h * @date 2015-06-20  * * NOTE:w * This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated. * * @condx ***********************************************************************************************************************F * CLOCK_XMC1 v4.0.14 - APP to configure System and Peripheral Clocks. */ * Copyright (c) 2015, Infineon Technologies AG/ * All rights reserved. / * } * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the # * following conditions are met: P * y * Redistributions of source code must retain the above copyright notice, this list of conditions and the following ( * disclaimer.  * { * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following ` * disclaimer in the documentation and/or other materials provided with the distribution.  * s * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote T * products derived from this software without specific prior written permission. / * w * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, w * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE x * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, z * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR z * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, v * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE O * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. P * x * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes > * with Infineon Technologies AG (dave@infineon.com). x *********************************************************************************************************************** * * Change History * -------------- * * 2015-02-16:( * - Initial version for DAVEv4
 * 2015-05-08:3 * - Version check added for required LLDs
 * 2015-06-20:7 * - Version check added for XMCLib dependency
 * 2015-09-22:P * - CLOCK_XMC1_STATUS enum and CLOCK_XMC1 data structure are provided.
X * - CLOCK_XMC4_Init and CLOCK_XMC4_StepSystemPllFrequency() APIs are provided.
 * 2015-10-19:? * - non-weak OSCHP_GetFrequency function is provided.
K * - CLOCK_XMC1_IsDCO1ExtRefCalibrationReady function is provided.
 * * @endcond  * */#ifndef CLOCK_XMC1_H#define CLOCK_XMC1_Hx/***********************************************************************************************************************u * HEADER FILES x **********************************************************************************************************************/#include #include #include "clock_xmc1_conf.h"##ifdef CLOCK_XMC1_INTERRUPT_ENABLED/#include "../GLOBAL_SCU_XMC1/global_scu_xmc1.h"#endifx /********************************************************************************************************************** * MACROSx **********************************************************************************************************************/)#if (!((XMC_LIB_MAJOR_VERSION == 2U) && \) (XMC_LIB_MINOR_VERSION >= 0U) && \& (XMC_LIB_PATCH_VERSION >= 0U)))D#error "CLOCK_XMC1 requires XMC Peripheral Library v2.0.0 or higher"#endif/**" * @ingroup CLOCK_XMC1_publicparam * @{ *//**; * @brief Initialization data structure for CLOCK_XMC1 APP *//** * @} */x /********************************************************************************************************************** * ENUMSx **********************************************************************************************************************//**# * @ingroup CLOCK_XMC1_enumerations * @{ *//*( * @brief enumeration for CLOCK_XMC1 APP */typedef enum CLOCK_XMC1_STATUS{M CLOCK_XMC1_STATUS_SUCCESS = 0U, /**Description:
N * The function can be used to check application software compatibility with a * specific version of the APP. * * Example Usage: * * @code * #include  * * int main(void) * { * DAVE_STATUS_t init_status; * DAVE_APP_VERSION_t version; *" * // Initialize CLOCK_XMC1 APP:; * // SystemCoreClockSetup() is called from SystemInit(). * init_status = DAVE_Init();* * if(DAVE_STATUS_SUCCESS == init_status) * {+ * version = CLOCK_XMC1_GetAppVersion(); * if (version.major != 4U) {+ * // Probably, not the right version. * } * * // More code here * while(1) { * } * } * return (1); * } * @endcode
 */2DAVE_APP_VERSION_t CLOCK_XMC1_GetAppVersion(void);/**/ * @brief Initializes a CLOCK_XMC1 APP instance2 * @param handle address of CLOCK_XMC1 APP handler * @returnW * CLOCK_XMC1_STATUS_SUCCESS : if initialization is successful\nQ * CLOCK_XMC1_STATUS_FAILURE : if initialization is failed * * \parDescription:
m * CLOCK_XMC1_Init API is called during initialization of DAVE APPS. This API Initializes GLOBAL_SCU_XMC1 APP= * for setting the interrupts and user callback registration. * * \parExample Usage:
 * * @code * #include  * * int main(void) * { * DAVE_STATUS_t status; *` * status = DAVE_Init(); // CLOCK_XMC1_Init API is called during initialization of DAVE APPS& * if(DAVE_STATUS_SUCCESS == status) * { * // user code * * while(1) * { * * } * } * return (1); * } * * @endcode
 */:CLOCK_XMC1_STATUS_t CLOCK_XMC1_Init(CLOCK_XMC1_t *handle);/**< * @brief API for ramping up/down the system clock frequency/ * @param target_freq required frequency in Hz. * @return none * * \parDescription:
K * The function can be used for ramping up/down the system clock frequency. * * Example Usage: * * @code * #include  * * int main(void) * { * DAVE_STATUS_t init_status;@ * uint32_t freq_khz = 1000U; // 1MHz is the target frequency" * // Initialize CLOCK_XMC1 APP:; * // SystemCoreClockSetup() is called from SystemInit(). * init_status = DAVE_Init();* * if(DAVE_STATUS_SUCCESS == init_status) * {` * CLOCK_XMC1_SetMCLKFrequency(freq_khz); // system clock frequency is ramping down to 1 MHz * // More code here * while(1) { * * } * } * return (1); * } * @endcode
 */4void CLOCK_XMC1_SetMCLKFrequency(uint32_t freq_khz);#if (CLOCK_XMC1_OSCHP_ENABLED)/**h * @brief This is a non-weak function, which retrieves high precision external oscillator frequency.
u * Note: This function is used by xmc1_scu LLD for internal operations. Therefore the user do not required to call * this API explicitly. *Y * @return uint32_t Range: 4 to 20 in External Crystal Mode / External Direct Input Mode. * * \parDescription:
s * This function to retrieves the external high precision oscillator frequency value, derived from either "External0 * Crystal Mode" or "External Direct Input Mode" *
 */"uint32_t OSCHP_GetFrequency(void);#endif)#if (CLOCK_XMC1_DCO1_CALIBRATION_ENABLED)/**I * @brief API to check whether DCO1 is synchronized to the XTAL frequency * @param none * @return bool
Q * true : if DCO1 is synchronized to the XTAL frequency\nU * false : if DCO1 is not synchronized to the XTAL frequency\n * * \parDescription:
X * The function can be used to check whether DCO1 is synchronized to the XTAL frequency. * * Example Usage: * * @code * #include  * * int main(void) * { * DAVE_STATUS_t init_status;- * #if(CLOCK_XMC1_DCO1_CALIBRATION_ENABLED)" * bool is_synchronized = false; * #endif" * // Initialize CLOCK_XMC1 APP:; * // SystemCoreClockSetup() is called from SystemInit(). * init_status = DAVE_Init();* * if(DAVE_STATUS_SUCCESS == init_status) * { * // User code here, * #if(CLOCK_XMC1_DCO1_CALIBRATION_ENABLED)i * is_synchronized = CLOCK_XMC1_IsDCO1ExtRefCalibrationReady(); // check whether DCO1 is synchronizedc * // to the XTAL frequency or not! * if(is_synchronized == true) * { * // User code hereF * // Do baud rate configuration related to communication protocol# * // start PWM in compare mode% * // start RTC in the RTC domain * * } * #endif * // More code here * while(1) { * * } * } * return (1); * } * @endcode
 */3bool CLOCK_XMC1_IsDCO1ExtRefCalibrationReady(void);#endif/** * @} */#ifdef __cplusplus} #endif #include"clock_xmc1_extern.h""#endif /* End of _CLOCK_XMC1_H_ */clock_xmc1_conf.cPv/*********************************************************************************************************************6* DAVE APP Name : CLOCK_XMC1 APP Version: 4.0.14** NOTE:v* This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated.v*********************************************************************************************************************//** * @condx *********************************************************************************************************************** */ * Copyright (c) 2015, Infineon Technologies AG * All rights reserved. *r * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: *v * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. *n * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and thee * following disclaimer in the documentation and/or other materials provided with the distribution. *r * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promoteS * products derived from this software without specific prior written permission. *u * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,t * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AREv * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,r * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ORt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,s * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THEK * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *q * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes5 * with Infineon Technologies AG (dave@infineon.com).x *********************************************************************************************************************** * * Change History * -------------- * 2015-02-16:) * - Initial version for DAVEv4.
 * 2015-05-08:9 * - Internal structure object name has changed.
 * 2015-10-15:< * - Updated for changes made in GUI combo options.
* @endcond * */x/*********************************************************************************************************************** * HEADER FILESx **********************************************************************************************************************/#include "clock_xmc1.h"w/*********************************************************************************************************************** DATA STRUCTURESw**********************************************************************************************************************/CLOCK_XMC1_t CLOCK_XMC1_0 ={ .init_status = false};w/*********************************************************************************************************************** API IMPLEMENTATIONw**********************************************************************************************************************/void SystemCoreClockSetup(void){/* LOCAL DATA STRUCTURES */2const XMC_SCU_CLOCK_CONFIG_t CLOCK_XMC1_0_CONFIG ={1 .pclk_src = XMC_SCU_CLOCK_PCLKSRC_DOUBLE_MCLK, . .rtc_src = XMC_SCU_CLOCK_RTCCLKSRC_DCO2, 2 .fdiv = 0U, /**< 8/10 Bit Fractional divider */, .idiv = 1U, /**< 8 Bit integer divider */};- /* Configure FDIV, IDIV, PCLKSEL dividers*/+ XMC_SCU_CLOCK_Init(&CLOCK_XMC1_0_CONFIG);}clock_xmc1_extern.h9v/*********************************************************************************************************************6* DAVE APP Name : CLOCK_XMC1 APP Version: 4.0.14** NOTE:v* This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated.v*********************************************************************************************************************//** * @condx *********************************************************************************************************************** */ * Copyright (c) 2015, Infineon Technologies AG/ * All rights reserved. / * } * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the # * following conditions are met: P * y * Redistributions of source code must retain the above copyright notice, this list of conditions and the following ( * disclaimer.  * { * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following ` * disclaimer in the documentation and/or other materials provided with the distribution.  * s * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote T * products derived from this software without specific prior written permission. / * w * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, w * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE x * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, z * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR z * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, v * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE O * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. P * x * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes > * with Infineon Technologies AG (dave@infineon.com). x *********************************************************************************************************************** * * Change History * -------------- * 2015-02-16:( * - Initial version for DAVEv4
 * 2015-09-22:7 * - CLOCK_XMC1_t extern declaration is added.
 * * @endcond  * */#ifndef CLOCK_XMC1_EXTERN_H#define CLOCK_XMC1_EXTERN_H#include "clock_xmc1.h"!extern CLOCK_XMC1_t CLOCK_XMC1_0;'#endif /* End of CLOCK_XMC1_EXTERN_H */ digital_io.cj/** * @file digital_io.c * @date 2015-08-25 * * NOTE:w * This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated. * * @condx ***********************************************************************************************************************c * DIGITAL_IO v4.0.14 - The DIGITAL_IO APP is used to configure a port pin as digital Input/Output. */ * Copyright (c) 2015, Infineon Technologies AG * All rights reserved. *r * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: *v * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. *n * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and thee * following disclaimer in the documentation and/or other materials provided with the distribution. *r * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promoteS * products derived from this software without specific prior written permission. *u * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,t * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AREv * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,r * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ORt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,s * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THEK * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *q * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes5 * with Infineon Technologies AG (dave@infineon.com).x *********************************************************************************************************************** * * Change History * -------------- * * 2015-02-16 * - Initial version
* 2015-12-22. * - Added hardware controlled IO feature. * * @endcond * */x/*********************************************************************************************************************** * HEADER FILESx **********************************************************************************************************************/#include "digital_io.h"x/*********************************************************************************************************************** * MACROSx **********************************************************************************************************************/x/*********************************************************************************************************************** * LOCAL DATAx **********************************************************************************************************************/x/*********************************************************************************************************************** * LOCAL ROUTINESx **********************************************************************************************************************/x /********************************************************************************************************************** * API IMPLEMENTATIONx **********************************************************************************************************************//**#* @brief Get DIGITAL_IO APP versionT* @return DAVE_APP_VERSION_t APP version information (major, minor and patch number)*/1DAVE_APP_VERSION_t DIGITAL_IO_GetAppVersion(void){ DAVE_APP_VERSION_t version;4 version.major = (uint8_t)DIGITAL_IO_MAJOR_VERSION;4 version.minor = (uint8_t)DIGITAL_IO_MINOR_VERSION;4 version.patch = (uint8_t)DIGITAL_IO_PATCH_VERSION; return (version);}/**@* @brief Function to initialize the port pin as per UI settings.8* @param handler Pointer pointing to APP data structure.4* @return DIGITAL_IO_STATUS_t DIGITAL_IO APP status.*/FDIGITAL_IO_STATUS_t DIGITAL_IO_Init(const DIGITAL_IO_t *const handler){G XMC_ASSERT("DIGITAL_IO_Init: handler null pointer", handler != NULL);2 /* Initializes input / output characteristics */N XMC_GPIO_Init(handler->gpio_port, handler->gpio_pin, &handler->gpio_config);% /*Configure hardware port control*/V XMC_GPIO_SetHardwareControl(handler->gpio_port, handler->gpio_pin, handler->hwctrl); return (DIGITAL_IO_STATUS_OK);} digital_io.hµ/* * * @file digital_io.h * @date 2015-12-22 * * NOTE:w * This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated. * * @condx ***********************************************************************************************************************c * DIGITAL_IO v4.0.14 - The DIGITAL_IO APP is used to configure a port pin as digital Input/Output. */ * Copyright (c) 2015, Infineon Technologies AG * All rights reserved. *r * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: *v * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. *n * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and thee * following disclaimer in the documentation and/or other materials provided with the distribution. *r * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promoteS * products derived from this software without specific prior written permission. *u * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,t * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AREv * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,r * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ORt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,s * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THEK * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *q * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes5 * with Infineon Technologies AG (dave@infineon.com).x *********************************************************************************************************************** * * Change History * -------------- * * 2015-02-16 * - Initial version * * 2015-04-22< * - XMC_ASSERT is added in static inline functions.
 * * 2015-06-207 * - Version check added for XMCLib dependency.
 * * 2015-12-22. * - Added hardware controlled IO feature. * * @endcond * */x/*********************************************************************************************************************** * HEADER FILESx **********************************************************************************************************************/#ifndef DIGITAL_IO_H#define DIGITAL_IO_H#include #include #include "digital_io_conf.h"x/*********************************************************************************************************************** * MACROSx **********************************************************************************************************************/)#if (!((XMC_LIB_MAJOR_VERSION == 2U) && \) (XMC_LIB_MINOR_VERSION >= 0U) && \& (XMC_LIB_PATCH_VERSION >= 0U)))D#error "DIGITAL_IO requires XMC Peripheral Library v2.0.0 or higher"#endifx /********************************************************************************************************************** * ENUMSx **********************************************************************************************************************//**"* @ingroup DIGITAL_IO_enumerations* @{*//**1* @brief Initialization status of DIGITAL_IO APP.*/typedef enum DIGITAL_IO_STATUS{/ DIGITAL_IO_STATUS_OK = 0U,/**< 0=Status OK */7 DIGITAL_IO_STATUS_FAILURE = 1U/**< 1=Status Failed */} DIGITAL_IO_STATUS_t;/*** @}*/w/********************************************************************************************************************** * DATA STRUCTURESx **********************************************************************************************************************//**$* @ingroup DIGITAL_IO_datastructures* @{*//**8* @brief Initialization data structure of DIGITAL_IO APP*/typedef struct DIGITAL_IO{C XMC_GPIO_PORT_t *const gpio_port; /**< port number */w const XMC_GPIO_CONFIG_t gpio_config; /**< mode, initial output level and pad driver strength / hysteresis */B const uint8_t gpio_pin; /**< pin number */M const XMC_GPIO_HWCTRL_t hwctrl; /**< Hardware port control */} DIGITAL_IO_t;/*** @}*/x/*********************************************************************************************************************** * API Prototypesx **********************************************************************************************************************/#ifdef __cplusplus extern "C" {#endif/*** @ingroup DIGITAL_IO_apidoc* @{*//**#* @brief Get DIGITAL_IO APP versionT* @return DAVE_APP_VERSION_t APP version information (major, minor and patch number)** \parDescription:
M* The function can be used to check application software compatibility with a* specific version of the APP.** Example Usage:** @code* #include ** int main(void)* {* DAVE_STATUS_t init_status;* DAVE_APP_VERSION_t version;*!* // Initialize DIGITAL_IO APP:;* // DIGITAL_IO_Init() is called from within DAVE_Init().* init_status = DAVE_Init();** if(init_status == DAVE_STATUS_SUCCESS)* {+* version = DIGITAL_IO_GetAppVersion(); * if (version.major != 4U) {)* // Probably, not the right version.* }* }** // More code here* while(1) {** }* return (1);* }* @endcode
*/2DAVE_APP_VERSION_t DIGITAL_IO_GetAppVersion(void);/***@* @brief Function to initialize the port pin as per UI settings.]* @param handler Pointer pointing to APP data structure. Refer @ref DIGITAL_IO_t for details.j* @return DIGITAL_IO_STATUS_t DIGITAL_IO APP status. Refer @ref DIGITAL_IO_STATUS_t structure for details.** \parDescription:
x* This function initializes GPIO port registers IOCR,PDISC,OMR,PDR/PHCR to configure pin direction,initial output level,%* and pad driver strength/hysteresis.** \parRelated APIs:
* None** Example Usage:* @codeV* #include //Declarations from DAVE Code Generation (includes SFR declaration)* int main(void)* {* DAVE_STATUS_t status;g* status = DAVE_Init(); //(DAVE_STATUS_t)DIGITAL_IO_Init(&DIGITAL_IO_0) is called within DAVE_Init()%* if(status == DAVE_STATUS_SUCCESS)* {6* XMC_DEBUG("DAVE Apps initialization success\n");* }* else* {N* XMC_DEBUG(("DAVE Apps initialization failed with status %d\n", status));* while(1U)* {* }* }m* //Placeholder for user application code. The while loop below can be replaced with user application code. * while(1U)* {* }* return 1U;* } * @endcode*/GDIGITAL_IO_STATUS_t DIGITAL_IO_Init(const DIGITAL_IO_t *const handler);/***'* @brief Function to set port pin high.]* @param handler Pointer pointing to APP data structure. Refer @ref DIGITAL_IO_t for details.* @return None** \parDescription:
d* This function configures port output modification register Pn_OMR, to make port pin to high level.** \parRelated APIs:
* DIGITAL_IO_SetOutputLow()** Example Usage:* @codeV* #include //Declarations from DAVE Code Generation (includes SFR declaration)* int main(void)* {* DAVE_STATUS_t status;g* status = DAVE_Init(); //(DAVE_STATUS_t)DIGITAL_IO_Init(&DIGITAL_IO_0) is called within DAVE_Init()%* if(status == DAVE_STATUS_SUCCESS)* {6* XMC_DEBUG("DAVE Apps initialization success\n");* }* else* {N* XMC_DEBUG(("DAVE Apps initialization failed with status %d\n", status));* while(1U)* {* }* }m* //Placeholder for user application code. The while loop below can be replaced with user application code.,* DIGITAL_IO_SetOutputHigh(&DIGITAL_IO_0); * while(1U)* {"* // Add application code here* }** return (1);* } * @endcode*/P__STATIC_INLINE void DIGITAL_IO_SetOutputHigh(const DIGITAL_IO_t *const handler){P XMC_ASSERT("DIGITAL_IO_SetOutputHigh: handler null pointer", handler != NULL);@ XMC_GPIO_SetOutputHigh(handler->gpio_port, handler->gpio_pin);}/**$* @brief Function to reset port pin.]* @param handler Pointer pointing to APP data structure. Refer @ref DIGITAL_IO_t for details.* @return None** \parDescription:
c* This function configures port output modification register Pn_OMR, to make port pin to low level.** \parRelated APIs:
* DIGITAL_IO_SetOutputHigh()** Example Usage:* @codeW* #include //Declarations from DAVE Code Generation (includes SFR declaration)* int main(void)* {* DAVE_STATUS_t status;h* status = DAVE_Init(); //(DAVE_STATUS_t)DIGITAL_IO_Init(&DIGITAL_IO_0) is called within DAVE_Init()&* if(status == DAVE_STATUS_SUCCESS)* {7* XMC_DEBUG("DAVE Apps initialization success\n");* } * else* {O* XMC_DEBUG(("DAVE Apps initialization failed with status %d\n", status));* while(1U)* {* }* }n* //Placeholder for user application code. The while loop below can be replaced with user application code.,* DIGITAL_IO_SetOutputLow(&DIGITAL_IO_0);* while(1U)* {#* // Add application code here* }** return (1);* } * @endcode*/O__STATIC_INLINE void DIGITAL_IO_SetOutputLow(const DIGITAL_IO_t *const handler){O XMC_ASSERT("DIGITAL_IO_SetOutputLow: handler null pointer", handler != NULL);> XMC_GPIO_SetOutputLow(handler->gpio_port,handler->gpio_pin);}/**%* @brief Function to Toggle port pin.]* @param handler Pointer pointing to APP data structure. Refer @ref DIGITAL_IO_t for details.* @return None** \parDescription:
X* This function configures port output modification register Pn_OMR, to toggle port pin.** \parRelated APIs:
7* DIGITAL_IO_SetOutputLow(), DIGITAL_IO_SetOutputHigh()** Example Usage:** @codeV* #include //Declarations from DAVE Code Generation (includes SFR declaration)* int main(void)* {* DAVE_STATUS_t status;* uint32_t delay_count;;g* status = DAVE_Init(); //(DAVE_STATUS_t)DIGITAL_IO_Init(&DIGITAL_IO_0) is called within DAVE_Init()%* if(status == DAVE_STATUS_SUCCESS)* {6* XMC_DEBUG("DAVE Apps initialization success\n");* }* else* {O* XMC_DEBUG(("DAVE Apps initialization failed with status %d\n", status));* while(1U)* {* }* }m* //Placeholder for user application code. The while loop below can be replaced with user application code. * while(1U)* {f* DIGITAL_IO_ToggleOutput(&DIGITAL_IO_0); //toggles : 1 -> 0 (if initial output level is logic 1)"* //Add application code here>* for(delay_count = 0;delay_count<0xfffff;delay_count++);A* DIGITAL_IO_ToggleOutput(&DIGITAL_IO_0); //toggles : 0 -> 1"* //Add application code here>* for(delay_count = 0;delay_count<0xfffff;delay_count++);* }* return (1);* } * @endcode*/O__STATIC_INLINE void DIGITAL_IO_ToggleOutput(const DIGITAL_IO_t *const handler){O XMC_ASSERT("DIGITAL_IO_ToggleOutput: handler null pointer", handler != NULL);? XMC_GPIO_ToggleOutput(handler->gpio_port, handler->gpio_pin);}/**2* @brief Function to read input level of port pin.]* @param handler Pointer pointing to APP data structure. Refer @ref DIGITAL_IO_t for details./* @return uint32_t input logic level. Range:0-1** \parDescription:
_* This function reads the Pn_IN register and returns the current logical value at the GPIO pin.** \parRelated APIs:
* None** Example Usage:* @codeV* #include //Declarations from DAVE Code Generation (includes SFR declaration)* int main(void)* {* DAVE_STATUS_t status;* uint32_t pin_status;i* status = DAVE_Init(); // (DAVE_STATUS_t)DIGITAL_IO_Init(&DIGITAL_IO_0) is called within DAVE_Init()%* if(status == DAVE_STATUS_SUCCESS)* {6* XMC_DEBUG("DAVE Apps initialization success\n");* }* else* {N* XMC_DEBUG(("DAVE Apps initialization failed with status %d\n", status));* while(1U)* {* }* }m* //Placeholder for user application code. The while loop below can be replaced with user application code. * while(1U)* {6* pin_status = DIGITAL_IO_GetInput(&DIGITAL_IO_0);* if(pin_status == 1)* {$* // Add application code here* } * else* {$* // Add application code here* }* }* return (1);* } * @endcode*/O__STATIC_INLINE uint32_t DIGITAL_IO_GetInput(const DIGITAL_IO_t *const handler){K XMC_ASSERT("DIGITAL_IO_GetInput: handler null pointer", handler != NULL);B return XMC_GPIO_GetInput(handler->gpio_port, handler->gpio_pin);}/***@}*/#ifdef __cplusplus}#endif/* Include APP extern file */#include "digital_io_extern.h"#endif /* DIGITAL_IO_H */digital_io_conf.c‰v/*********************************************************************************************************************6* DAVE APP Name : DIGITAL_IO APP Version: 4.0.14** NOTE:v* This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated.v*********************************************************************************************************************//** * @condx *********************************************************************************************************************** */ * Copyright (c) 2015, Infineon Technologies AG * All rights reserved. *r * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: *v * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. *n * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and thee * following disclaimer in the documentation and/or other materials provided with the distribution. *r * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promoteS * products derived from this software without specific prior written permission. *u * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,t * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AREv * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,r * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ORt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,s * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THEK * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *q * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes5 * with Infineon Technologies AG (dave@infineon.com).x *********************************************************************************************************************** * * Change History * -------------- * * 2015-02-16: * - Initial version
* 2015-12-22. * - Added hardware controlled IO feature. * * @endcond * */x/*********************************************************************************************************************** * HEADER FILESx **********************************************************************************************************************/#include "digital_io.h"#const DIGITAL_IO_t DIGITAL_IO_H_U ={ .gpio_port = XMC_GPIO_PORT0, .gpio_pin = 5U, .gpio_config = {+ .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL,. .output_level = XMC_GPIO_OUTPUT_LEVEL_LOW, },$ .hwctrl = XMC_GPIO_HWCTRL_DISABLED}; #const DIGITAL_IO_t DIGITAL_IO_H_V ={ .gpio_port = XMC_GPIO_PORT0, .gpio_pin = 6U, .gpio_config = {+ .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL,. .output_level = XMC_GPIO_OUTPUT_LEVEL_LOW, },$ .hwctrl = XMC_GPIO_HWCTRL_DISABLED}; #const DIGITAL_IO_t DIGITAL_IO_H_W ={ .gpio_port = XMC_GPIO_PORT0, .gpio_pin = 7U, .gpio_config = {+ .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL,. .output_level = XMC_GPIO_OUTPUT_LEVEL_LOW, },$ .hwctrl = XMC_GPIO_HWCTRL_DISABLED}; #const DIGITAL_IO_t DIGITAL_IO_L_U ={ .gpio_port = XMC_GPIO_PORT0, .gpio_pin = 8U, .gpio_config = {+ .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL,. .output_level = XMC_GPIO_OUTPUT_LEVEL_LOW, },$ .hwctrl = XMC_GPIO_HWCTRL_DISABLED}; #const DIGITAL_IO_t DIGITAL_IO_L_W ={ .gpio_port = XMC_GPIO_PORT0, .gpio_pin = 0U, .gpio_config = {+ .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL,. .output_level = XMC_GPIO_OUTPUT_LEVEL_LOW, },$ .hwctrl = XMC_GPIO_HWCTRL_DISABLED}; #const DIGITAL_IO_t DIGITAL_IO_L_V ={ .gpio_port = XMC_GPIO_PORT0, .gpio_pin = 9U, .gpio_config = {+ .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL,. .output_level = XMC_GPIO_OUTPUT_LEVEL_LOW, },$ .hwctrl = XMC_GPIO_HWCTRL_DISABLED}; !const DIGITAL_IO_t DIGITAL_IO_0 ={ .gpio_port = XMC_GPIO_PORT2, .gpio_pin = 1U, .gpio_config = {+ .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL,. .output_level = XMC_GPIO_OUTPUT_LEVEL_LOW, },$ .hwctrl = XMC_GPIO_HWCTRL_DISABLED};digital_io_extern.hQv/*********************************************************************************************************************6* DAVE APP Name : DIGITAL_IO APP Version: 4.0.14** NOTE:v* This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated.v*********************************************************************************************************************//** * @condx *********************************************************************************************************************** */ * Copyright (c) 2015, Infineon Technologies AG * All rights reserved. *r * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: *v * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. *n * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and thee * following disclaimer in the documentation and/or other materials provided with the distribution. *r * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promoteS * products derived from this software without specific prior written permission. *u * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,t * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AREv * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,r * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ORt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,s * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THEK * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *q * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes5 * with Infineon Technologies AG (dave@infineon.com).x *********************************************************************************************************************** * * Change History * -------------- * * 2015-02-16: * - Initial version
* 2015-12-220 * - APP data structure defined as constant. * * @endcond * */x/*********************************************************************************************************************** * HEADER FILESx **********************************************************************************************************************/ w/********************************************************************************************************************** * MACROSx **********************************************************************************************************************/x/*********************************************************************************************************************** * EXTERN DECLARATIONSx***********************************************************************************************************************/#ifndef DIGITAL_IO_EXTERN_H#define DIGITAL_IO_EXTERN_H*extern const DIGITAL_IO_t DIGITAL_IO_H_U;  *extern const DIGITAL_IO_t DIGITAL_IO_H_V;  *extern const DIGITAL_IO_t DIGITAL_IO_H_W;  *extern const DIGITAL_IO_t DIGITAL_IO_L_U;  *extern const DIGITAL_IO_t DIGITAL_IO_L_W;  *extern const DIGITAL_IO_t DIGITAL_IO_L_V;  (extern const DIGITAL_IO_t DIGITAL_IO_0;   !#endif /* DIGITAL_IO_EXTERN_H */global_ccu4.ca/** * @file global_ccu4.c * @date 2016-02-10 * * NOTE:w * This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated. * * @condx ***********************************************************************************************************************W * GLOBAL_CCU4 v4.1.12 - Configures the global properties of CCU4x peripheral instance. */ * Copyright (c) 2016, Infineon Technologies AG * All rights reserved. *r * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: *v * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. *n * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and thee * following disclaimer in the documentation and/or other materials provided with the distribution. *r * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promoteS * products derived from this software without specific prior written permission. *u * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,t * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AREv * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,r * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ORt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,s * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THEK * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *q * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes5 * with Infineon Technologies AG (dave@infineon.com).x *********************************************************************************************************************** * * Change History * -------------- * * 2015-02-16: * - Initial version
 * * @endcond * */x/*********************************************************************************************************************** * HEADER FILESx **********************************************************************************************************************/#include "global_ccu4.h"x/*********************************************************************************************************************** * MACROSx **********************************************************************************************************************/x/*********************************************************************************************************************** * LOCAL DATAx **********************************************************************************************************************/ x/*********************************************************************************************************************** * LOCAL ROUTINESx **********************************************************************************************************************/w/********************************************************************************************************************** * API IMPLEMENTATIONx **********************************************************************************************************************/1/* Returns the version of the GLOBAL_CCU4 APP. */2DAVE_APP_VERSION_t GLOBAL_CCU4_GetAppVersion(void){ DAVE_APP_VERSION_t version;, version.major = GLOBAL_CCU4_MAJOR_VERSION;, version.minor = GLOBAL_CCU4_MINOR_VERSION;, version.patch = GLOBAL_CCU4_PATCH_VERSION; return version;}</* Initializes the slice with the generated configuration */<GLOBAL_CCU4_STATUS_t GLOBAL_CCU4_Init(GLOBAL_CCU4_t* handle){@ XMC_ASSERT("GLOBAL_CCU4_Init:NULL handler", (NULL != handle));& if (false == handle->is_initialized) { /* Enable CCU4 module */9 XMC_CCU4_Init(handle->module_ptr,handle->mcs_action); /* Start the prescaler */0 XMC_CCU4_StartPrescaler(handle->module_ptr);, /* Restricts multiple initializations */" handle->is_initialized = true; }& return (GLOBAL_CCU4_STATUS_SUCCESS);}global_ccu4.h#/** * @file global_ccu4.h * @date 2016-02-10 * * NOTE:w * This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated. * * @condx ***********************************************************************************************************************W * GLOBAL_CCU4 v4.1.12 - Configures the global properties of CCU4x peripheral instance. */ * Copyright (c) 2016, Infineon Technologies AG * All rights reserved. *r * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: *v * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. *n * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and thee * following disclaimer in the documentation and/or other materials provided with the distribution. *r * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promoteS * products derived from this software without specific prior written permission. *u * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,t * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AREv * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,r * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ORt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,s * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THEK * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *q * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes5 * with Infineon Technologies AG (dave@infineon.com).x *********************************************************************************************************************** * * Change History * -------------- * * 2015-02-16: * - Initial version
 * * 2015-05-08:h * - New parameter "syncstart_trigger_msk" is added in APP handle to start the specific kernel/s
; * - File guard updated according to the guidelines
 * * 2015-05-22: * - API names changedZ * a. GLOBAL_CCU4_SyncStart_TriggerLow() --> GLOBAL_CCU4_SyncStartTriggerLow()
\ * b. GLOBAL_CCU4_SyncStart_TriggerHigh() --> GLOBAL_CCU4_SyncStartTriggerHigh()
 * * 2015-06-20: * - Guidelines update * 2015-07-31:# * - xmc_scu.h file is included * * 2016-01-06:f * - Added a check for XMC4 devices, to verify that CCU clock is enabled or not in CLOCK_XMC4 APP." * - Removed #error statement. * @endcond * */#ifndef GLOBAL_CCU4_H#define GLOBAL_CCU4_Hx/*********************************************************************************************************************** * HEADER FILESx **********************************************************************************************************************/#include #include #include #include "global_ccu4_conf.h"w/********************************************************************************************************************** * MACROSx **********************************************************************************************************************/)#if (!((XMC_LIB_MAJOR_VERSION == 2U) && \) (XMC_LIB_MINOR_VERSION >= 0U) && \& (XMC_LIB_PATCH_VERSION >= 0U)))E#error "GLOBAL_CCU4 requires XMC Peripheral Library v2.0.0 or higher"#endifw/********************************************************************************************************************** * ENUMSx **********************************************************************************************************************//**$ * @ingroup GLOBAL_CCU4_enumerations * @{ *//**. * @brief Return status of the GLOBAL_CCU4 APP */typedef enum GLOBAL_CCU4_STATUS{9 GLOBAL_CCU4_STATUS_SUCCESS = 0U, /**< Status success */3 GLOBAL_CCU4_STATUS_FAILURE /**< Status failure */} GLOBAL_CCU4_STATUS_t;/*** @}*/x/************************************************************************************************************************ DATA STRUCTURESx***********************************************************************************************************************//**& * @ingroup GLOBAL_CCU4_datastructures * @{ *//**1 * This saves the context of the GLOBAL_CCU4 APP. */typedef struct GLOBAL_CCU4{9 const uint32_t module_frequency; /**< fccu frequency */c const XMC_SCU_CCU_TRIGGER_t syncstart_trigger_msk; /**< Mask to start the timers synchronously */K XMC_CCU4_MODULE_t* const module_ptr; /**< reference to module handle */q XMC_CCU4_SLICE_MCMS_ACTION_t const mcs_action; /**< Shadow transfer of selected values in multi-channel mode */] bool is_initialized; /**< Indicates initialized state of particular instance of the APP */} GLOBAL_CCU4_t;/** * @} */x/************************************************************************************************************************ API Prototypesx***********************************************************************************************************************/#ifdef __cplusplus extern "C" {#endif/** * @ingroup GLOBAL_CCU4_apidoc * @{ *//**% * @brief Get GLOBAL_CCU4 APP versionU * @return DAVE_APP_VERSION_t APP version information (major, minor and patch number) *
 * \parDescription:
N * The function can be used to check application software compatibility with a * specific version of the APP. * * Example Usage: * @code * #include  * int main(void) * { * DAVE_STATUS_t status;$ * DAVE_APP_VERSION_t app_version; *K * status = DAVE_Init(); // GLOBAL_CCU4_Init() is called from DAVE_Init() */ * app_version = GLOBAL_CCU4_GetAppVersion(); *! * if (app_version.major != 4U) * {* * // Probably, not the right version. * } * * while(1U) * { * } * return 1; * } * @endcode
 */3DAVE_APP_VERSION_t GLOBAL_CCU4_GetAppVersion(void);/**A * @brief Initializes a GLOBAL_CCU4 with generated configuration. *A * @param handle pointer to the GLOBAL_CCU4 APP handle structure.a * @return GLOBAL_CCU4_STATUS_t\n GLOBAL_CCU4_STATUS_SUCCESS : if initialization is successful\n] * GLOBAL_CCU4_STATUS_FAILURE : if initialization is failed\n *
 * \parDescription:
 *
     *
  • Enable the module.
  • *
  • Start the prescaler.
  •  *
 * * Example Usage: * @code * #include  * int main(void) * { * DAVE_STATUS_t init_status;b * init_status = DAVE_Init(); // GLOBAL_CCU4_Init(&GLOBAL_CCU4_0) will be called from DAVE_Init() * * while(1) * { * } * return 1; * } * @endcode
 */=GLOBAL_CCU4_STATUS_t GLOBAL_CCU4_Init(GLOBAL_CCU4_t* handle);/**] * @brief Start all the timers which are configured to start externally on positive edge.
I * @param ccucon_msk mask for which kernels sync start has to be applied. * \parNote:
\ * This mask has been generated in the APP handle and as a macro in global_ccu4_conf.h file.U * 1. The variable from the APP handle is useful while starting the specific kernel/sx * 2. GLOBAL_CCU4_CCUCON_Msk Macro from global_ccu4_conf.h file can be used to start all the selected kernels at a time. * @retval none * * \parDescription:
c * The top level APPs have to be enabled, to start the timer externally with positive trigger edge. * * Example Usage: * @code * #include  * int main(void) * { * DAVE_STATUS_t status; *K * status = DAVE_Init(); // GLOBAL_CCU4_Init() is called from DAVE_Init() *Y * // Below can be used to start the specific kernels, by generating two instance of APP * // GLOBAL_CCU4_SyncStartTriggerHigh((uint32_t)(GLOBAL_CCU4_0.syncstart_trigger_msk | GLOBAL_CCU4_1.syncstart_trigger_msk));@ * // Below can be used to start all the kernels simultaneously> * GLOBAL_CCU4_SyncStartTriggerHigh(GLOBAL_CCU4_CCUCON_Msk); * * while(1) * { * } * * return 1; * } * @endcode

 */J__STATIC_INLINE void GLOBAL_CCU4_SyncStartTriggerHigh(uint32_t ccucon_msk){( XMC_SCU_SetCcuTriggerHigh(ccucon_msk);}/**] * @brief Start all the timers which are configured to start externally on negative edge.
I * @param ccucon_msk mask for which kernels sync start has to be applied. * \parNote:
Y * This mask has been generated in the APP handle and a macro in global_ccu4_conf.h file.U * 1. The variable from the APP handle is useful while starting the specific kernel/sx * 2. GLOBAL_CCU4_CCUCON_Msk Macro from global_ccu4_conf.h file can be used to start all the selected kernels at a time. * @retval none * * \parDescription:
c * The top level APPs have to be enabled, to start the timer externally with negative trigger edge. * * Example Usage: * @code * #include  * int main(void) * { * DAVE_STATUS_t status; *K * status = DAVE_Init(); // GLOBAL_CCU4_Init() is called from DAVE_Init() *Y * // Below can be used to start the specific kernels, by generating two instance of APP~ * // GLOBAL_CCU4_SyncStartTriggerLow((uint32_t)(GLOBAL_CCU4_0.syncstart_trigger_msk | GLOBAL_CCU4_1.syncstart_trigger_msk));@ * // Below can be used to start all the kernels simultaneously= * GLOBAL_CCU4_SyncStartTriggerLow(GLOBAL_CCU4_CCUCON_Msk); * * while(1) * { * } * * return 1; * } * @endcode

 */I__STATIC_INLINE void GLOBAL_CCU4_SyncStartTriggerLow(uint32_t ccucon_msk){' XMC_SCU_SetCcuTriggerLow(ccucon_msk);}/** * @} */#include "global_ccu4_extern.h"#ifdef __cplusplus}#endif#endif /*CCUGLOBAL_H*/global_ccu4_conf.cEv/*********************************************************************************************************************7* DAVE APP Name : GLOBAL_CCU4 APP Version: 4.1.12** NOTE:v* This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated.v*********************************************************************************************************************//** * @condx *********************************************************************************************************************** */ * Copyright (c) 2016, Infineon Technologies AG * All rights reserved. *r * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: *v * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. *n * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and thee * following disclaimer in the documentation and/or other materials provided with the distribution. *r * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promoteS * products derived from this software without specific prior written permission. *u * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,t * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AREv * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,r * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ORt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,s * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THEK * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *q * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes5 * with Infineon Technologies AG (dave@infineon.com).x *********************************************************************************************************************** * * Change History * -------------- * * 2015-02-16: * - Initial version
 * * 2015-05-08:h * - New parameter "syncstart_trigger_msk" is added in APP handle to start the specific kernel/s
 * * @endcond * */x/*********************************************************************************************************************** * HEADER FILESx **********************************************************************************************************************/#include "global_ccu4.h"x/************************************************************************************************************************ DATA STRUCTURESx***********************************************************************************************************************/ -/**< Configuration for HandleGLOBAL_CCU4_0 */GLOBAL_CCU4_t GLOBAL_CCU4_0 ={D .module_frequency = 64000000U, /**< CCU4 input clock frequency */6 .syncstart_trigger_msk = XMC_SCU_CCU_TRIGGER_CCU40, L .module_ptr = (XMC_CCU4_MODULE_t*) CCU40, /**< CCU4 Module Pointer */X .mcs_action = (XMC_CCU4_SLICE_MCMS_ACTION_t)XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR, .is_initialized = false};global_ccu4_extern.hEv/*********************************************************************************************************************7* DAVE APP Name : GLOBAL_CCU4 APP Version: 4.1.12** NOTE:v* This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated.v*********************************************************************************************************************//** * @condx *********************************************************************************************************************** */ * Copyright (c) 2016, Infineon Technologies AG * All rights reserved. *r * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: *v * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. *n * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and thee * following disclaimer in the documentation and/or other materials provided with the distribution. *r * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promoteS * products derived from this software without specific prior written permission. *u * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,t * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AREv * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,r * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ORt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,s * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THEK * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *q * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes5 * with Infineon Technologies AG (dave@infineon.com).x *********************************************************************************************************************** * * Change History * -------------- * * 2015-02-16: * - Initial version
 * * 2015-05-08:; * - File guard updated according to the guidelines
 * * @endcond * */#ifndef GLOBAL_CCU4_EXTERN_H#define GLOBAL_CCU4_EXTERN_Hx/*********************************************************************************************************************** * HEADER FILESx **********************************************************************************************************************/w/********************************************************************************************************************** * MACROSx **********************************************************************************************************************/x/*********************************************************************************************************************** * EXTERN DECLARATIONSy ***********************************************************************************************************************/Nextern GLOBAL_CCU4_t GLOBAL_CCU4_0; /**< APP handle for handle GLOBAL_CCU4_0*/!#endif /* GLOBAL_CCU4_EXTERN_H */ pwm_ccu4.cN/** * @file pwm_ccu4.c * @date 2016-03-21 * * NOTE:w * This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated. * * @condx ***********************************************************************************************************************t * PWM_CCU4 v4.1.18 - PWM APP using one timer slice of CCU4, with external events support, to generate a PWM output. */ * Copyright (c) 2016, Infineon Technologies AG * All rights reserved. *r * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: *v * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. *x * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following[ * disclaimer in the documentation and/or other materials provided with the distribution. *r * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promoteS * products derived from this software without specific prior written permission. *u * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,t * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AREv * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,r * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ORt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,s * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THEK * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *q * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes5 * with Infineon Technologies AG (dave@infineon.com).x *********************************************************************************************************************** * * Change History * -------------- * * 2015-02-14:# * - Initial version for DAVEv4 * * 2015-05-20:Q * - PWM_CCU4_AcknowledgeInterrupt() api is renamed as PWM_CCU4_ClearEvent(). * * 2015-06-20:' * - Copyright information updated. * * 2015-08-13:m * - Added support for selection of shadow transfer mode using API "XMC_CCU4_SLICE_SetShadowTransferMode"G * - Added support for selection of immediate shadow transfer usingQ * API "XMC_CCU4_SLICE_WriteImmediateAfterShadowTransfer" in XMC14* devices: * - Added support for automatic shadow transfer usingT * API "XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest" in XMC14* devices * @endcond * */x/*********************************************************************************************************************** * HEADER FILESx **********************************************************************************************************************/#include "pwm_ccu4.h"x/*********************************************************************************************************************** * MACROSx **********************************************************************************************************************/x/*********************************************************************************************************************** * LOCAL DATAx **********************************************************************************************************************/x/*********************************************************************************************************************** * LOCAL ROUTINESx **********************************************************************************************************************/#/* Initialize the App Interrupts */=static void PWM_CCU4_lInit_Interrupt(PWM_CCU4_t* handle_ptr);2/* Initialize the App events and configurations */?static void PWM_CCU4_lConfigure_Events(PWM_CCU4_t* handle_ptr);w/********************************************************************************************************************** * API IMPLEMENTATIONx **********************************************************************************************************************/&/* API to retrieve App version info *//DAVE_APP_VERSION_t PWM_CCU4_GetAppVersion(void){ DAVE_APP_VERSION_t version;) version.major = PWM_CCU4_MAJOR_VERSION;) version.minor = PWM_CCU4_MINOR_VERSION;) version.patch = PWM_CCU4_PATCH_VERSION; return version;}'/* This function initializes the app */7PWM_CCU4_STATUS_t PWM_CCU4_Init(PWM_CCU4_t* handle_ptr){ PWM_CCU4_STATUS_t status;* GLOBAL_CCU4_STATUS_t status_ccu4_global; uint32_t frequency_module; uint32_t prescalar;# status = PWM_CCU4_STATUS_FAILURE;2 status_ccu4_global = GLOBAL_CCU4_STATUS_FAILURE;G XMC_ASSERT("PWM_CCU4_Init:handle_ptr is NULL", (handle_ptr != NULL));8 if (PWM_CCU4_STATE_UNINITIALIZED == handle_ptr->state) {" /* Initialize consumed Apps */V status_ccu4_global = GLOBAL_CCU4_Init(handle_ptr->config_ptr->global_ccu4_handle);% /* Initialize CCU4x_CC4y slice */9 if (GLOBAL_CCU4_STATUS_SUCCESS == status_ccu4_global) {3 XMC_DEBUG("PWM_CCU4_Init:Initilizing slice");/ /* Configure CCU4x_CC4y slice as timer */o XMC_CCU4_SLICE_CompareInit(handle_ptr->ccu4_slice_ptr, handle_ptr->config_ptr->ccu4_cc4_slice_timer_ptr);0 /* Set period match value of the timer */k XMC_CCU4_SLICE_SetTimerPeriodMatch(handle_ptr->ccu4_slice_ptr, handle_ptr->config_ptr->period_value);7 /* Set timer compare match value for channel 1 */x XMC_CCU4_SLICE_SetTimerCompareMatch(handle_ptr->ccu4_slice_ptr, (uint16_t) handle_ptr->config_ptr->compare_value);M if (1U == handle_ptr->config_ptr->ccu4_cc4_slice_timer_ptr->mcm_enable) {O XMC_CCU4_SetMultiChannelShadowTransferMode(handle_ptr->ccu4_module_ptr,l (uint32_t) handle_ptr->config_ptr->mcm_shadow_txfr_mode); }H#if (UC_SERIES == XMC14) /*below feature available in XMC14xx devices */u XMC_CCU4_SLICE_SetShadowTransferMode(handle_ptr->ccu4_slice_ptr, handle_ptr->config_ptr->shadow_transfer_mode);R XMC_CCU4_SLICE_WriteImmediateAfterShadowTransfer(handle_ptr->ccu4_slice_ptr,` handle_ptr->config_ptr->immediate_write);U XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest(handle_ptr->ccu4_slice_ptr,m handle_ptr->config_ptr->automatic_shadow_transfer);K if((bool)true == handle_ptr->config_ptr->cascaded_shadow_txfr_enable) {P XMC_CCU4_SLICE_EnableCascadedShadowTransfer(handle_ptr->ccu4_slice_ptr); }#endifP /* Transfer value from shadow timer registers to actual timer registers */^ XMC_CCU4_EnableShadowTransfer(handle_ptr->ccu4_module_ptr, handle_ptr->shadow_txfr_msk);e XMC_CCU4_EnableShadowTransfer(handle_ptr->ccu4_module_ptr, handle_ptr->dither_shadow_txfr_msk); /* Configure events */- PWM_CCU4_lConfigure_Events(handle_ptr);! /* Enable the interrupts */+ PWM_CCU4_lInit_Interrupt(handle_ptr); /*Initializes the GPIO*/D if ((bool) true == handle_ptr->config_ptr->gpio_ch_out_enable) {g XMC_GPIO_Init(handle_ptr->config_ptr->gpio_ch_out_ptr, handle_ptr->config_ptr->gpio_ch_out_pin,F handle_ptr->config_ptr->gpio_ch_out_config_ptr); }V frequency_module = handle_ptr->config_ptr->global_ccu4_handle->module_frequency;a prescalar = (uint32_t) handle_ptr->config_ptr->ccu4_cc4_slice_timer_ptr->prescaler_initval;H frequency_module = frequency_module / ((uint32_t) 1 << prescalar);4 handle_ptr->frequency_tclk = frequency_module;5 handle_ptr->state = PWM_CCU4_STATE_INITIALIZED;' status = PWM_CCU4_STATUS_SUCCESS;J /* Start the PWM generation if start at initialization is enabled */? if ((bool) true == handle_ptr->config_ptr->start_control) {, status = PWM_CCU4_Start(handle_ptr); } } else {7 handle_ptr->state = PWM_CCU4_STATE_UNINITIALIZED; } } else {1 status = PWM_CCU4_STATUS_ALREADY_INITIALIZED;C XMC_DEBUG("PWM_CCU4_Init:PWM_CCU4_STATUS_ALREADY_INITIALIZED"); } return (status);"} /* end of PWM_CCU4_Init() api */<static void PWM_CCU4_lInit_Interrupt(PWM_CCU4_t* handle_ptr){o /* Enable events. Bind event to corresponding service request node.Enable Interrupts. The user may choose to * disable the interrupts by LLD calls. */; if ((bool) true == handle_ptr->config_ptr->int_per_match) {> XMC_DEBUG("PWM_CCU4_Init: Interrupt period match enable");c XMC_CCU4_SLICE_SetInterruptNode(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH,J handle_ptr->config_ptr->sr_per_match);_ XMC_CCU4_SLICE_EnableEvent(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH); }> if ((bool) true == handle_ptr->config_ptr->int_cmp_match_up) {B XMC_DEBUG("PWM_CCU4_Init: Interrupt compare match up enable");g XMC_CCU4_SLICE_SetInterruptNode(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP,M handle_ptr->config_ptr->sr_cmp_match_up);c XMC_CCU4_SLICE_EnableEvent(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP); }@ if ((bool) true == handle_ptr->config_ptr->int_cmp_match_down) {D XMC_DEBUG("PWM_CCU4_Init: Interrupt compare match down enable");i XMC_CCU4_SLICE_SetInterruptNode(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN,O handle_ptr->config_ptr->sr_cmp_match_down);e XMC_CCU4_SLICE_EnableEvent(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN); }@ if ((bool) true == handle_ptr->config_ptr->int_one_match_down) {; XMC_DEBUG("PWM_CCU4_Init: Interrupt one match enable");` XMC_CCU4_SLICE_SetInterruptNode(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH,O handle_ptr->config_ptr->sr_one_match_down);\ XMC_CCU4_SLICE_EnableEvent(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH); }4 if ((bool) true == handle_ptr->config_ptr->int_e0) {9 XMC_DEBUG("PWM_CCU4_Init: Interrupt event 0 enable");] XMC_CCU4_SLICE_SetInterruptNode(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_IRQ_ID_EVENT0,C handle_ptr->config_ptr->sr_e0);Y XMC_CCU4_SLICE_EnableEvent(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_IRQ_ID_EVENT0); }4 if ((bool) true == handle_ptr->config_ptr->int_e1) {9 XMC_DEBUG("PWM_CCU4_Init: Interrupt event 1 enable");] XMC_CCU4_SLICE_SetInterruptNode(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_IRQ_ID_EVENT1,C handle_ptr->config_ptr->sr_e1);Y XMC_CCU4_SLICE_EnableEvent(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_IRQ_ID_EVENT1); }4 if ((bool) true == handle_ptr->config_ptr->int_e2) {9 XMC_DEBUG("PWM_CCU4_Init: Interrupt event 2 enable");] XMC_CCU4_SLICE_SetInterruptNode(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_IRQ_ID_EVENT2,C handle_ptr->config_ptr->sr_e2);Y XMC_CCU4_SLICE_EnableEvent(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_IRQ_ID_EVENT2); }}>static void PWM_CCU4_lConfigure_Events(PWM_CCU4_t* handle_ptr){- /* Configure slice to a external event 0 */S XMC_CCU4_SLICE_ConfigureEvent(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_EVENT_0,K handle_ptr->config_ptr->event0_config_ptr);- /* Configure slice to a external event 1 */S XMC_CCU4_SLICE_ConfigureEvent(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_EVENT_1,K handle_ptr->config_ptr->event1_config_ptr);- /* Configure slice to a external event 2 */S XMC_CCU4_SLICE_ConfigureEvent(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_EVENT_2,K handle_ptr->config_ptr->event2_config_ptr);3 /* External signal controls start of the timer */K if (XMC_CCU4_SLICE_EVENT_NONE != handle_ptr->config_ptr->ext_start_event) {c XMC_CCU4_SLICE_StartConfig(handle_ptr->ccu4_slice_ptr, handle_ptr->config_ptr->ext_start_event,G handle_ptr->config_ptr->ext_start_mode); }* /* External signal can stop the timer */J if (XMC_CCU4_SLICE_EVENT_NONE != handle_ptr->config_ptr->ext_stop_event) {a XMC_CCU4_SLICE_StopConfig(handle_ptr->ccu4_slice_ptr, handle_ptr->config_ptr->ext_stop_event,E handle_ptr->config_ptr->ext_stop_mode); }? /* External signal can change the timer counting direction */O if (XMC_CCU4_SLICE_EVENT_NONE != handle_ptr->config_ptr->ext_count_dir_event) {l XMC_CCU4_SLICE_DirectionConfig(handle_ptr->ccu4_slice_ptr, handle_ptr->config_ptr->ext_count_dir_event); }K /* External signal can stop the timer and the timer value remains same */J if (XMC_CCU4_SLICE_EVENT_NONE != handle_ptr->config_ptr->ext_gate_event) {b XMC_CCU4_SLICE_GateConfig(handle_ptr->ccu4_slice_ptr, handle_ptr->config_ptr->ext_gate_event); }+ /* Timer increments on external signal */K if (XMC_CCU4_SLICE_EVENT_NONE != handle_ptr->config_ptr->ext_count_event) {d XMC_CCU4_SLICE_CountConfig(handle_ptr->ccu4_slice_ptr, handle_ptr->config_ptr->ext_count_event); }a /* Timer gets loaded with compare register value or period register value on external signal */J if (XMC_CCU4_SLICE_EVENT_NONE != handle_ptr->config_ptr->ext_load_event) {b XMC_CCU4_SLICE_LoadConfig(handle_ptr->ccu4_slice_ptr, handle_ptr->config_ptr->ext_load_event); }T /* External signal PWM signal (ST bit) output gets modulated by external signal */I if (XMC_CCU4_SLICE_EVENT_NONE != handle_ptr->config_ptr->ext_mod_event) {f XMC_CCU4_SLICE_ModulationConfig(handle_ptr->ccu4_slice_ptr, handle_ptr->config_ptr->ext_mod_event,p handle_ptr->config_ptr->ext_mod_mode, handle_ptr->config_ptr->ext_mod_sync); }D /* PWM signal (ST bit) output gets modulated by external signal */G if (XMC_CCU4_SLICE_EVENT_2 == handle_ptr->config_ptr->ext_trap_event) {` XMC_CCU4_SLICE_TrapConfig(handle_ptr->ccu4_slice_ptr, handle_ptr->config_ptr->ext_trap_exit,E handle_ptr->config_ptr->ext_trap_sync);? if ((bool) true == handle_ptr->config_ptr->ext_trap_enable) {< XMC_CCU4_SLICE_EnableTrap(handle_ptr->ccu4_slice_ptr); } }l if ((XMC_CCU4_SLICE_EVENT_1 == handle_ptr->config_ptr->ext_override_edge_event) && (XMC_CCU4_SLICE_EVENT_2; == handle_ptr->config_ptr->ext_override_level_event)) {N XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(handle_ptr->ccu4_slice_ptr,] handle_ptr->config_ptr->event1_config_ptr,^ handle_ptr->config_ptr->event2_config_ptr);G XMC_CCU4_SLICE_StatusBitOverrideConfig(handle_ptr->ccu4_slice_ptr); }}l/**********************************************************************************************************/\/*Starts the CCU4_CC4 slice. This needs to be called even if external start is configured.*/8PWM_CCU4_STATUS_t PWM_CCU4_Start(PWM_CCU4_t* handle_ptr){ PWM_CCU4_STATUS_t status;# status = PWM_CCU4_STATUS_FAILURE;E XMC_ASSERT("PWM_CCU4_Start:handle_ptr NULL", (handle_ptr != NULL));i if ((PWM_CCU4_STATE_INITIALIZED == handle_ptr->state) || (PWM_CCU4_STATE_STOPPED == handle_ptr->state)) {4 /* clear IDLE mode for the slice; Start timer */P XMC_CCU4_EnableClock(handle_ptr->ccu4_module_ptr, handle_ptr->slice_number);M if (XMC_CCU4_SLICE_EVENT_NONE == handle_ptr->config_ptr->ext_start_event) {< XMC_CCU4_SLICE_StartTimer(handle_ptr->ccu4_slice_ptr); }/ handle_ptr->state = PWM_CCU4_STATE_RUNNING;% status = PWM_CCU4_STATUS_SUCCESS;* XMC_DEBUG("PWM_CCU4_Start:start PWM"); } return (status);#} /* end of PWM_CCU4_Start() api */l/**********************************************************************************************************//*Stops the CCU4_CC4 slice. */7PWM_CCU4_STATUS_t PWM_CCU4_Stop(PWM_CCU4_t* handle_ptr){ PWM_CCU4_STATUS_t status;# status = PWM_CCU4_STATUS_FAILURE;D XMC_ASSERT("PWM_CCU4_Stop:handle_ptr NULL", (handle_ptr != NULL));8 if (PWM_CCU4_STATE_UNINITIALIZED != handle_ptr->state) {9 XMC_CCU4_SLICE_StopTimer(handle_ptr->ccu4_slice_ptr);: XMC_CCU4_SLICE_ClearTimer(handle_ptr->ccu4_slice_ptr);Q XMC_CCU4_DisableClock(handle_ptr->ccu4_module_ptr, handle_ptr->slice_number);/ handle_ptr->state = PWM_CCU4_STATE_STOPPED;% status = PWM_CCU4_STATUS_SUCCESS;( XMC_DEBUG("PWM_CCU4_Stop:stop PWM"); } return (status);"} /* end of PWM_CCU4_Stop() api */l/**********************************************************************************************************/-/*Gets the timer value of CCU4_CC4 slice. */7uint32_t PWM_CCU4_GetTimerValue(PWM_CCU4_t* handle_ptr){ uint32_t timer_value;M XMC_ASSERT("PWM_CCU4_GetTimerValue:handle_ptr NULL", (handle_ptr != NULL));T timer_value = (uint32_t) XMC_CCU4_SLICE_GetTimerValue(handle_ptr->ccu4_slice_ptr);2 XMC_DEBUG("PWM_CCU4_GetTimerValue:timer value"); return (timer_value);*}/* end of PWM_CCU4_GetTimerValue() api */l/**********************************************************************************************************/(/*Gets the status of CCU4_CC4 slice. */4bool PWM_CCU4_GetTimerStatus(PWM_CCU4_t* handle_ptr){ bool status_timer;N XMC_ASSERT("PWM_CCU4_GetTimerStatus:handle_ptr NULL", (handle_ptr != NULL));K status_timer = XMC_CCU4_SLICE_IsTimerRunning(handle_ptr->ccu4_slice_ptr); return (status_timer);'} /* end of PWM_CCU4_GetStatus() api */l/**********************************************************************************************************/+/*Sets the frequency for CCU4_CC4 slice. */PPWM_CCU4_STATUS_t PWM_CCU4_SetFreq(PWM_CCU4_t* handle_ptr, uint32_t pwm_freq_hz){ PWM_CCU4_STATUS_t status; uint32_t frequency_tclk; uint32_t period; uint32_t duty; uint16_t compare;# status = PWM_CCU4_STATUS_FAILURE; frequency_tclk = 0U;G XMC_ASSERT("PWM_CCU4_SetFreq:handle_ptr NULL", (handle_ptr != NULL));8 if (PWM_CCU4_STATE_UNINITIALIZED != handle_ptr->state) { if (0U == pwm_freq_hz) {= XMC_DEBUG("PWM_CCU4_SetFreq:cannot set frequency 0Hz"); } else {2 frequency_tclk = handle_ptr->frequency_tclk;, period = frequency_tclk / pwm_freq_hz;x if ((uint32_t) XMC_CCU4_SLICE_TIMER_COUNT_MODE_CA == handle_ptr->config_ptr->ccu4_cc4_slice_timer_ptr->timer_mode) {- period = period >> 1U;/*divide by 2*/ }A if ((period != 0U) && (period <= PWM_CCU4_MAX_TIMER_COUNT)) {K /*Calculate the current duty cycle in no-timer concatenation mode*/$ duty = handle_ptr->sym_duty;1 duty = (PWM_CCU4_DUTY_FULL_SCALE - duty); duty = duty * period;/ duty = duty / PWM_CCU4_DUTY_FULL_SCALE;" compare = (uint16_t) duty;` XMC_CCU4_SLICE_SetTimerPeriodMatch(handle_ptr->ccu4_slice_ptr, (uint16_t)(period - 1U));Q XMC_CCU4_SLICE_SetTimerCompareMatch(handle_ptr->ccu4_slice_ptr, compare);` XMC_CCU4_EnableShadowTransfer(handle_ptr->ccu4_module_ptr, handle_ptr->shadow_txfr_msk);4 XMC_DEBUG("PWM_CCU4_SetFreq:frequency set");) status = PWM_CCU4_STATUS_SUCCESS; } } } return (status);.} /* end of PWM_CCU4_SetFreqSymmetric() api */l/**********************************************************************************************************/7/*Sets the duty cycle (uint32_t) for CCU4_CC4 slice. */TPWM_CCU4_STATUS_t PWM_CCU4_SetDutyCycle(PWM_CCU4_t* handle_ptr, uint32_t duty_cycle){ PWM_CCU4_STATUS_t status; uint32_t period; uint32_t compare;# status = PWM_CCU4_STATUS_FAILURE;L XMC_ASSERT("PWM_CCU4_SetDutyCycle:handle_ptr NULL", (handle_ptr != NULL));8 if (PWM_CCU4_STATE_UNINITIALIZED != handle_ptr->state) {3 /* duty cycle has to be in between 0 and 100 */- if ((duty_cycle > PWM_CCU4_SYM_DUTY_MAX)) {F XMC_DEBUG("PWM_CCU4_SetDutyCycle:Cannot set duty cycle > 100%"); } else {^ period = (uint32_t) XMC_CCU4_SLICE_GetTimerPeriodMatch(handle_ptr->ccu4_slice_ptr) + 1U;7 /* Duty Cycle(symmetric) = (PR-CR1)+1 / period */` compare = ((period * (PWM_CCU4_DUTY_FULL_SCALE - duty_cycle)) / PWM_CCU4_DUTY_FULL_SCALE);Z XMC_CCU4_SLICE_SetTimerCompareMatch(handle_ptr->ccu4_slice_ptr, (uint16_t) compare);^ XMC_CCU4_EnableShadowTransfer(handle_ptr->ccu4_module_ptr, handle_ptr->shadow_txfr_msk);( handle_ptr->sym_duty = duty_cycle;7 XMC_DEBUG("PWM_CCU4_SetDutyCycle:dutycycle set");' status = PWM_CCU4_STATUS_SUCCESS; } } return (status);*} /* end of PWM_CCU4_SetDutyCycle() api */l/**********************************************************************************************************/I/*Sets the frequency and duty cycle for CCU4_CC4 slice Symmetric Mode. */kPWM_CCU4_STATUS_t PWM_CCU4_SetFreqAndDutyCycle(PWM_CCU4_t* handle_ptr, uint32_t pwm_freq_hz, uint32_t duty){ PWM_CCU4_STATUS_t status; uint32_t frequency_tclk; uint32_t period; uint32_t compare;# status = PWM_CCU4_STATUS_FAILURE; frequency_tclk = 0U;S XMC_ASSERT("PWM_CCU4_SetFreqAndDutyCycle:handle_ptr NULL", (handle_ptr != NULL));8 if (PWM_CCU4_STATE_UNINITIALIZED != handle_ptr->state) { if (0U == pwm_freq_hz) {R XMC_DEBUG("PWM_CCU4_SetFreqAndDutyCycleSymmetric:cannot set frequency 0Hz"); }* else if (duty > PWM_CCU4_SYM_DUTY_MAX) {< XMC_DEBUG("PWM_CCU4_SetFreqAndDutyCycle:duty > 100%"); } else {2 frequency_tclk = handle_ptr->frequency_tclk;, period = frequency_tclk / pwm_freq_hz;x if ((uint32_t) XMC_CCU4_SLICE_TIMER_COUNT_MODE_CA == handle_ptr->config_ptr->ccu4_cc4_slice_timer_ptr->timer_mode) {- period = period >> 1U;/*divide by 2*/ }A if ((period != 0U) && (period <= PWM_CCU4_MAX_TIMER_COUNT)) {K /*Calculate the current duty cycle in no-timer concatenation mode*/\ compare = ((period * (PWM_CCU4_DUTY_FULL_SCALE - duty)) / PWM_CCU4_DUTY_FULL_SCALE);` XMC_CCU4_SLICE_SetTimerPeriodMatch(handle_ptr->ccu4_slice_ptr, (uint16_t)(period - 1U));\ XMC_CCU4_SLICE_SetTimerCompareMatch(handle_ptr->ccu4_slice_ptr, (uint16_t) compare);` XMC_CCU4_EnableShadowTransfer(handle_ptr->ccu4_module_ptr, handle_ptr->shadow_txfr_msk);$ handle_ptr->sym_duty = duty;@ XMC_DEBUG("PWM_CCU4_SetFreqAndDutyCycle:frequency set");) status = PWM_CCU4_STATUS_SUCCESS; } } } return (status);0}/* end of PWM_CCU4_SetFreqAndDutyCycle() api */l/**********************************************************************************************************///*Sets the dither value, enables the dither. */kvoid PWM_CCU4_SetDither(PWM_CCU4_t* handle_ptr, bool dither_period, bool dither_comp, uint8_t dither_value){I XMC_ASSERT("PWM_CCU4_SetDither:handle_ptr NULL", (handle_ptr != NULL));g XMC_CCU4_SLICE_EnableDithering(handle_ptr->ccu4_slice_ptr, dither_period, dither_comp, dither_value);a XMC_CCU4_EnableShadowTransfer(handle_ptr->ccu4_module_ptr, handle_ptr->dither_shadow_txfr_msk);; XMC_DEBUG("PWM_CCU4_SetDither:dither compare value set");&}/* end of PWM_CCU4_SetDither() api */l/**********************************************************************************************************/4/*exits trap condition if trap signal is inactive *//void PWM_CCU4_ClearTrap(PWM_CCU4_t* handle_ptr){I XMC_ASSERT("PWM_CCU4_ClearTrap:handle_ptr NULL", (handle_ptr != NULL));V XMC_CCU4_SLICE_ClearEvent(handle_ptr->ccu4_slice_ptr, XMC_CCU4_SLICE_IRQ_ID_EVENT2);5 XMC_DEBUG("PWM_CCU4_ClearTrap:trap event cleared");&}/* end of PWM_CCU4_ClearTrap() api */l/**********************************************************************************************************/2/*Gets the interrupt status of CCU4_CC4 slice. */_bool PWM_CCU4_GetInterruptStatus(PWM_CCU4_t* handle_ptr, XMC_CCU4_SLICE_IRQ_ID_t pwm_interrupt){ bool status = (bool) false;R XMC_ASSERT("PWM_CCU4_GetInterruptStatus:handle_ptr NULL", (handle_ptr != NULL));N status = XMC_CCU4_SLICE_GetEvent(handle_ptr->ccu4_slice_ptr, pwm_interrupt); return (status);0} /* end of PWM_CCU4_GetInterruptStatus() api */l/**********************************************************************************************************/3/*Acknowledges the interrupt of CCU4_CC4 slice. */Wvoid PWM_CCU4_ClearEvent(PWM_CCU4_t* handle_ptr, XMC_CCU4_SLICE_IRQ_ID_t pwm_interrupt){J XMC_ASSERT("PWM_CCU4_ClearEvent:handle_ptr NULL", (handle_ptr != NULL));G XMC_CCU4_SLICE_ClearEvent(handle_ptr->ccu4_slice_ptr, pwm_interrupt);9 XMC_DEBUG("PWM_CCU4_ClearEvent:Acknowledge Interrupt");(} /* end of PWM_CCU4_ClearEvent() api */&/* end of CCU4 function definitions */ pwm_ccu4.hg/** * @file pwm_ccu4.h * @date 2016-03-21 * * NOTE:w * This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated. * * @condx ***********************************************************************************************************************t * PWM_CCU4 v4.1.18 - PWM APP using one timer slice of CCU4, with external events support, to generate a PWM output. */ * Copyright (c) 2016, Infineon Technologies AG * All rights reserved. *r * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: *v * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. *x * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following[ * disclaimer in the documentation and/or other materials provided with the distribution. *r * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promoteS * products derived from this software without specific prior written permission. *u * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,t * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AREv * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,r * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ORt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,s * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THEK * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *q * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes5 * with Infineon Technologies AG (dave@infineon.com).x *********************************************************************************************************************** * * Change History * -------------- * * 2015-02-14:# * - Initial version for DAVEv4 * * 2015-05-20:Q * - PWM_CCU4_AcknowledgeInterrupt() api is renamed as PWM_CCU4_ClearEvent().. * - Logic for LLD version check is added. * * 2015-06-19:0 * - Logic for LLD version check is removed., * - LLD package version check is added. * * 2015-06-20:' * - Copyright information updated. * * 2015-06-23B * - In comment section "comapre" correctly spelt as "compare" * * 2015-08-13:? * - Added "immediate_write" member in "PWM_CCU4_CONFIG_t"I * - Added "automatic_shadow_transfer" member in "PWM_CCU4_CONFIG_t"C * - Added "shadow_transfer_mode" member in "PWM_CCU4_CONFIG_t" * @endcond * */#ifndef PWM_CCU4_H_#define PWM_CCU4_H_x/*********************************************************************************************************************** * HEADER FILESx **********************************************************************************************************************/#include #include "pwm_ccu4_conf.h")#if (!((XMC_LIB_MAJOR_VERSION == 2U) && \) (XMC_LIB_MINOR_VERSION >= 0U) && \& (XMC_LIB_PATCH_VERSION >= 0U)))B#error "PWM_CCU4 requires XMC Peripheral Library v2.0.0 or higher"#endifw/*********************************************************************************************************************** MACROSw**********************************************************************************************************************/*#define PWM_CCU4_MAX_TIMER_COUNT (65535U);#define PWM_CCU4_DUTY_FULL_SCALE (10000U) /*100% * 100*/4#define PWM_CCU4_DUTY_SCALE (100U) /*100*/9#define PWM_CCU4_SYM_DUTY_MAX (10000U) /*duty Max*/9#define PWM_CCU4_SYM_DUTY_MIN (0U) /*duty Min*/w/*********************************************************************************************************************** ENUMSw**********************************************************************************************************************/ /**" * @ingroup PWM_CCU4_enumerations * @{ *//**/ * @brief The type identifies the APP status. */typedef enum PWM_CCU4_STATUS{ /** * STATUS SUCCESS */ PWM_CCU4_STATUS_SUCCESS = 0U, /** * STATUS FAILURE */ PWM_CCU4_STATUS_FAILURE = 1U, /** * STATUS ALREADY INITIALIZED */* PWM_CCU4_STATUS_ALREADY_INITIALIZED = 2U} PWM_CCU4_STATUS_t;/**( * @brief The type identifies APP state. */typedef enum PWM_CCU4_STATE{ /**' * default state after power on reset[ * PWM_CCU4 APP is in uninitialized mode. The corresponding CCU4 timer is not configured.! * PWM pulses is not generated. */$ PWM_CCU4_STATE_UNINITIALIZED = 0U, /**U * PWM_CCU4 APP is in initialized mode. The corresponding CCU4 timer is configured.> * The corresponding CCU4 timer is not started(not running). */" PWM_CCU4_STATE_INITIALIZED = 1U, /**N * PWM_CCU4 APP is in running mode. The corresponding CCU4 timer is running.j * Trigger signal for any of the configured Interrupt or service request in the CCU4 timer is triggered. */ PWM_CCU4_STATE_RUNNING = 2U, /**N * PWM_CCU4 APP is in stopped mode. The corresponding CCU4 timer is stopped.n * Trigger signal for any of the configured Interrupt or service request in the CCU4 timer is not triggered. */ PWM_CCU4_STATE_STOPPED = 3U} PWM_CCU4_STATE_t;/** * @} */w/*********************************************************************************************************************** DATA STRUCTURESw**********************************************************************************************************************//**$ * @ingroup PWM_CCU4_datastructures * @{ *//**6 * @brief Configuration parameters of the PWM_CCU4 APP */"typedef struct PWM_CCU4_ConfigType{‚ const bool start_control; /**Description:
k * The function can be used to check application software compatibility with a specific version of the APP. * *Example Usage: * * @code #include  int main(void) { DAVE_APP_VERSION_t version;' version = PWM_CCU4_GetAppVersion(); while(1); return 0; } * @endcode */0DAVE_APP_VERSION_t PWM_CCU4_GetAppVersion(void);/**' * @brief Initializes the PWM_CCU4 APP.P * @param handle_ptr Pointer to PWM_CCU4_t structure containing APP parameters. * @return PWM_CCU4_STATUS_t * * \parDescription:
} * Configures the CCU4 slice registers with the selected PWM_CCU4 parameters. The slice is configured in PWM generation mode. * * Example Usage: * @code #include   int main(void) {; DAVE_Init(); //PWM_CCU4_Init() is called by DAVE_Init(). while(1); return 0; } * @endcode */>PWM_CCU4_STATUS_t PWM_CCU4_Init(PWM_CCU4_t* const handle_ptr);/**( * @brief Start the selected CCU4 slice.P * @param handle_ptr Pointer to PWM_CCU4_t structure containing APP parameters. * @return PWM_CCU4_STATUS_t * * \parDescription:
o * Starts the selected CCU4 slice for PWM generation. Returns PWM_CCU4_STATUS_SUCCESS if the PWM_CCU4 APP statea * is in "PWM_CCU4_STATE_INITIALIZED" or "PWM_CCU4_STOPPED" else returns PWM_CCU4_STATUS_FAILURE.u *
PWM_CCU4_Start() is needed to be called if "Start during initialization" is unchecked to start PWM generation," * else its called by DAVE_Init(); * * Example Usage: * @code #include   int main(void) { DAVE_Init();N //This API needs to be called if "Start during initialization" is unchecked PWM_CCU4_Start(&PWM_CCU4_0); while(1); return 0; } * @endcode*/A PWM_CCU4_STATUS_t PWM_CCU4_Start(PWM_CCU4_t* const handle_ptr); /**) * @brief Stop the selected CCU4 slice.R * @param handle_ptr Pointer to PWM_CCU4_t structure containing APP parameters. * @return PWM_CCU4_STATUS_t *! * \parDescription:
q * Stops the selected CCU4 slice form PWM generation. Returns PWM_CCU4_STATUS_SUCCESS if the PWM_CCU4 APP stateP * is not "PWM_CCU4_STATE_UNINITIALIZED" else returns PWM_CCU4_STATUS_FAILURE. * * Example Usage: * @code #include  int main(void) { DAVE_Init(); PWM_CCU4_Stop(&PWM_CCU4_0); while(1); return 0; } * @endcode */@ PWM_CCU4_STATUS_t PWM_CCU4_Stop(PWM_CCU4_t* const handle_ptr); /**" * @brief Returns the timer value.P * @param handle_ptr Pointer to PWM_CCU4_t structure containing APP parameters. * @return uint32_t * * \parDescription:
5 * Returns the timer value if the APP is initialized. * * Example Usage: * @code #include  int main(void) { uint32_t timer ; DAVE_Init();1 timer = PWM_CCU4_GetTimerValue(&PWM_CCU4_0); while(1); return 0; } * @endcode */@ uint32_t PWM_CCU4_GetTimerValue(PWM_CCU4_t* const handle_ptr); /**% * @brief Returns the timer status.Q * @param handle_ptr Pointer to PWM_CCU4_t structure containing APP parameters. * @return XMC_CCU4_STATUS_t *! * \parDescription:
= * Returns true is the timer is running else returns false. * * Example Usage: * @code #include  int main(void) { bool status; DAVE_Init();3 status = PWM_CCU4_GetTimerStatus(&PWM_CCU4_0); while(1); return 0; } * @endcode */= bool PWM_CCU4_GetTimerStatus(PWM_CCU4_t* const handle_ptr); /**# * @brief Sets the PWM frequency.Q * @param handle_ptr Pointer to PWM_CCU4_t structure containing APP parameters.. * @param pwm_freq_hz value in Hz (uint32_t) * @return PWM_CCU4_STATUS_t *! * \parDescription:
g * Sets the PWM frequency of PWM generation. The APP should not be in "PWM_CCU4_UNINITIALIZED" state.D * Returns PWM_CCU4_STATUS_SUCCESS if frequency update is success. * * Example Usage: * @code #include  int main(void) { PWM_CCU4_STATUS_t status; DAVE_Init();4 status = PWM_CCU4_SetFreq(&PWM_CCU4_0, 100000); while(1); return 0; } * @endcode */Y PWM_CCU4_STATUS_t PWM_CCU4_SetFreq(PWM_CCU4_t* const handle_ptr, uint32_t pwm_freq_hz); /**' * @brief Sets the duty cycle of PWM.Q * @param handle_ptr Pointer to PWM_CCU4_t structure containing APP parameters.3 * @param duty_cycle channel duty cycle uint32_t * @return PWM_CCU4_STATUS_t *! * \parDescription:
P * Sets the PWM duty. The APP should not be in "PWM_CCU4_UNINITIALIZED" state.N * Duty is scaled by 100.
The condition [duty < 100%] should be met.
D * Returns PWM_CCU4_STATUS_SUCCESS if operation update is success. * * Example Usage: * @code #include  int main(void) { PWM_CCU4_STATUS_t status; DAVE_Init();2 // sets the channel duty to 40%.7 status = PWM_CCU4_SetDutyCycle(&PWM_CCU4_0, 4000); while(1); return 0; } * @endcode */] PWM_CCU4_STATUS_t PWM_CCU4_SetDutyCycle(PWM_CCU4_t* const handle_ptr, uint32_t duty_cycle); /**1 * @brief Sets the frequency duty cycle of PWM.Q * @param handle_ptr Pointer to PWM_CCU4_t structure containing APP parameters.. * @param pwm_freq_hz value in Hz (uint32_t) * @param duty channel duty * @return PWM_CCU4_STATUS_t *! * \parDescription:
a * Sets the frequency and duty of PWM. The APP should not be in "PWM_CCU4_UNINITIALIZED" state.N * Duty is scaled by 100.
The condition [duty < 100%] should be met.
D * Returns PWM_CCU4_STATUS_SUCCESS if operation update is success. * * Example Usage: * @code #include  int main(void) { PWM_CCU4_STATUS_t status; DAVE_Init();; // Sets freq = 100000, channel duty = 40%F status = PWM_CCU4_SetFreqAndDutyCycle(&PWM_CCU4_0, 100000, 4000); while(1); return 0; } * @endcode */t PWM_CCU4_STATUS_t PWM_CCU4_SetFreqAndDutyCycle(PWM_CCU4_t* const handle_ptr, uint32_t pwm_freq_hz, uint32_t duty); /**< * @brief Sets the dither value for period , duty or both.Q * @param handle_ptr Pointer to PWM_CCU4_t structure containing APP parameters.0 * @param dither_period apply dither to period/ * @param dither_comp apply dither to compare% * @param dither_value dither value * @return void *! * \parDescription:
9 * Sets the dither value for period , duty or both.
+ * dither_value: is the dither value.
? * dither_period: when true, dither is applied to period.
> * dither_comp: when true, dither is applied to compare.
 * * Example Usage: * @code #include  int main(void) { DAVE_Init();A PWM_CCU4_SetDither(&PWM_CCU4_0,(bool) true, (bool)true, 10); while(1); return 0; } * @endcode */t void PWM_CCU4_SetDither(PWM_CCU4_t* const handle_ptr, bool dither_period, bool dither_comp, uint8_t dither_value); /**" * @brief Clears the trap event.Q * @param handle_ptr Pointer to PWM_CCU4_t structure containing APP parameters. * @return void *! * \parDescription:
H * Clears the trap event provided the trap condition no longer exists. * * Example Usage: * @code #include  int main(void) { DAVE_Init();% PWM_CCU4_ClearTrap(&PWM_CCU4_0); while(1); return 0; } * @endcode */8 void PWM_CCU4_ClearTrap(PWM_CCU4_t* const handle_ptr); /**) * @brief Returns the interrupt status.Q * @param handle_ptr Pointer to PWM_CCU4_t structure containing APP parameters.& * @param pwm_interrupt interrupt ID * @return bool *! * \parDescription:
C * Returns true if the interrupt flag is set, else returns false. * * Example Usage: * @code #include  int main(void) { bool status; DAVE_Init();= // Returns period match interrupt status.Z status = PWM_CCU4_GetInterruptStatus(&PWM_CCU4_0,XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH);F // Returns channel compare match interrupt status.^ status = PWM_CCU4_GetInterruptStatus(&PWM_CCU4_0,XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP); while(1); return 0; } * @endcode */h bool PWM_CCU4_GetInterruptStatus(PWM_CCU4_t* const handle_ptr, XMC_CCU4_SLICE_IRQ_ID_t pwm_interrupt); /**' * @brief Acknowledges the interrupt.Q * @param handle_ptr Pointer to PWM_CCU4_t structure containing APP parameters.& * @param pwm_interrupt interrupt ID * @return *! * \parDescription:
Y * Clears the interrupt status flag, provided the interrupt condition no longer exists. * * Example Usage: * @code #include  int main(void) { DAVE_Init();I PWM_CCU4_ClearEvent(&PWM_CCU4_0,XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH);M PWM_CCU4_ClearEvent(&PWM_CCU4_0,XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP); while(1); return 0; } * @endcode */` void PWM_CCU4_ClearEvent(PWM_CCU4_t* const handle_ptr, XMC_CCU4_SLICE_IRQ_ID_t pwm_interrupt);#include "pwm_ccu4_extern.h"/** * @} */#ifdef __cplusplus}#endif#endif /* PWM_CCU4_H_ */pwm_ccu4_conf.cÉv/*********************************************************************************************************************4* DAVE APP Name : PWM_CCU4 APP Version: 4.1.18** NOTE:v* This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated.v*********************************************************************************************************************//** * @condx *********************************************************************************************************************** */ * Copyright (c) 2016, Infineon Technologies AG * All rights reserved. *r * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: *v * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. *x * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following[ * disclaimer in the documentation and/or other materials provided with the distribution. *r * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promoteS * products derived from this software without specific prior written permission. *u * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,t * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AREv * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,r * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ORt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,s * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THEK * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *q * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes5 * with Infineon Technologies AG (dave@infineon.com).x *********************************************************************************************************************** * * Change History * -------------- * * 2015-02-14:# * - Initial version for DAVEv4 * * 2015-08-13:Y * - Added support for initializing "immediate_write" member in "PWM_CCU4_CONFIG_t"c * - Added support for initializing "automatic_shadow_transfer" member in "PWM_CCU4_CONFIG_t"] * - Added support for initializing "shadow_transfer_mode" member in "PWM_CCU4_CONFIG_t" * @endcond * */x/*********************************************************************************************************************** * HEADER FILESx **********************************************************************************************************************/#include "pwm_ccu4.h"w/********************************************************************************************************************** * DATA STRUCTURESx **********************************************************************************************************************/v/********************************************************************************************************************/D const XMC_CCU4_SLICE_COMPARE_CONFIG_t PWM_CCU4_0_timer_handle = {L .timer_mode = (uint32_t)XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA,Q .monoshot = (uint32_t)XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT," .shadow_xfer_clear = 0U," .dither_timer_period = 0U," .dither_duty_cycle = 0U,N .prescaler_mode = (uint32_t)XMC_CCU4_SLICE_PRESCALER_MODE_NORMAL," .mcm_enable = 0U," .prescaler_initval = 0U," .dither_limit = 0U," .timer_concatenation = 0U,R .passive_level = (uint32_t)XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW,  };C const XMC_CCU4_SLICE_EVENT_CONFIG_t PWM_CCU4_0_event0_config =  {4 .mapped_input = XMC_CCU4_SLICE_INPUT_A,H .edge = XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE,O .level = XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW,B .duration = XMC_CCU4_SLICE_EVENT_FILTER_DISABLED, };C const XMC_CCU4_SLICE_EVENT_CONFIG_t PWM_CCU4_0_event1_config =  {4 .mapped_input = XMC_CCU4_SLICE_INPUT_A,H .edge = XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE,O .level = XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW,B .duration = XMC_CCU4_SLICE_EVENT_FILTER_DISABLED, };C const XMC_CCU4_SLICE_EVENT_CONFIG_t PWM_CCU4_0_event2_config =  {4 .mapped_input = XMC_CCU4_SLICE_INPUT_A,H .edge = XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE,O .level = XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW,B .duration = XMC_CCU4_SLICE_EVENT_FILTER_DISABLED, };7 const PWM_CCU4_CONFIG_t PWM_CCU4_0_config_handle = {8 .start_control = true, 3 .period_value = 6399U,3 .compare_value = 3200U,2 .int_per_match = true,3 .int_cmp_match_up = false,3 .int_cmp_match_down = false,3 .int_one_match_down = false,3 .int_e0 = false,3 .int_e1 = false,3 .int_e2 = false,D .sr_per_match = XMC_CCU4_SLICE_SR_ID_0,D .sr_cmp_match_up = XMC_CCU4_SLICE_SR_ID_0,D .sr_cmp_match_down = XMC_CCU4_SLICE_SR_ID_0,D .sr_one_match_down = XMC_CCU4_SLICE_SR_ID_0,D .sr_e0 = XMC_CCU4_SLICE_SR_ID_0,D .sr_e1 = XMC_CCU4_SLICE_SR_ID_0,D .sr_e2 = XMC_CCU4_SLICE_SR_ID_0,G .event0_config_ptr = &PWM_CCU4_0_event0_config,G .event1_config_ptr = &PWM_CCU4_0_event1_config,G .event2_config_ptr = &PWM_CCU4_0_event2_config,G .ext_start_event = XMC_CCU4_SLICE_EVENT_NONE,S .ext_start_mode = XMC_CCU4_SLICE_START_MODE_TIMER_START,G .ext_stop_event = XMC_CCU4_SLICE_EVENT_NONE,P .ext_stop_mode = XMC_CCU4_SLICE_END_MODE_TIMER_STOP,G .ext_count_dir_event = XMC_CCU4_SLICE_EVENT_NONE,G .ext_gate_event = XMC_CCU4_SLICE_EVENT_NONE,G .ext_count_event = XMC_CCU4_SLICE_EVENT_NONE,G .ext_load_event = XMC_CCU4_SLICE_EVENT_NONE,G .ext_mod_event = XMC_CCU4_SLICE_EVENT_NONE,Y .ext_mod_mode = XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_ST_OUT,3 .ext_mod_sync = false,G .ext_override_edge_event = XMC_CCU4_SLICE_EVENT_NONE,G .ext_override_level_event = XMC_CCU4_SLICE_EVENT_NONE,3 .ext_trap_enable = false,G .ext_trap_event = XMC_CCU4_SLICE_EVENT_NONE,2 .ext_trap_sync = true,U .ext_trap_exit = XMC_CCU4_SLICE_TRAP_EXIT_MODE_AUTOMATIC,^ .mcm_shadow_txfr_mode = XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE0, #if (UC_SERIES == XMC14)f .shadow_transfer_mode = XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_PERIOD_MATCH,0 .immediate_write = 0U,0 .automatic_shadow_transfer = 0U,3 .cascaded_shadow_txfr_enable = false,#endifF .ccu4_cc4_slice_timer_ptr = &PWM_CCU4_0_timer_handle,3 .gpio_ch_out_enable = false,F .gpio_ch_out_ptr = (XMC_GPIO_PORT_t *) NULL,0 .gpio_ch_out_pin = 0U,6 .gpio_ch_out_config_ptr = NULL, N .global_ccu4_handle = (GLOBAL_CCU4_t*) &GLOBAL_CCU4_0, }; PWM_CCU4_t PWM_CCU4_0 = {G .config_ptr = &PWM_CCU4_0_config_handle,M .ccu4_module_ptr = (XMC_CCU4_MODULE_t*) CCU40_BASE,L .ccu4_slice_ptr = (XMC_CCU4_SLICE_t*) CCU40_CC40,0 .slice_number = 0U,0 .kernel_number = 0U,X .shadow_txfr_msk = (uint32_t)XMC_CCU4_SHADOW_TRANSFER_SLICE_0,_ .dither_shadow_txfr_msk = (uint32_t)XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_0,b .prescaler_shadow_txfr_msk = (uint32_t)XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_0,J .state = PWM_CCU4_STATE_UNINITIALIZED,3 .sym_duty = 5000U, };j/********************************************************************************************************/pwm_ccu4_extern.hEv/*********************************************************************************************************************4* DAVE APP Name : PWM_CCU4 APP Version: 4.1.18** NOTE:v* This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated.v*********************************************************************************************************************//** * @condx *********************************************************************************************************************** */ * Copyright (c) 2016, Infineon Technologies AG * All rights reserved. *r * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: *v * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. *x * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following[ * disclaimer in the documentation and/or other materials provided with the distribution. *r * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promoteS * products derived from this software without specific prior written permission. *u * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,t * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AREv * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,r * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ORt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,s * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THEK * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *q * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes5 * with Infineon Technologies AG (dave@infineon.com).x *********************************************************************************************************************** * * Change History * -------------- * * 2015-02-14:# * - Initial version for DAVEv4 * * 2015-06-20:' * - Copyright information updated. * @endcond * */#ifndef PWM_CCU4EXTERN_H_#define PWM_CCU4EXTERN_H_x/*********************************************************************************************************************** * HEADER FILESx **********************************************************************************************************************/ w/********************************************************************************************************************** * MACROSx **********************************************************************************************************************/x/*********************************************************************************************************************** * EXTERN DECLARATIONSx***********************************************************************************************************************/! extern PWM_CCU4_t PWM_CCU4_0;#endifsystem_xmc1100.hTO/****************************************************************************** * @file system_XMC1100.hM * @brief Device specific initialization for the XMC1300-Series according * to CMSIS * @version V1.2 * @date 19 Jul 2013 * * @noteI * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved. * * @parO * Infineon Technologies AG (Infineon) is supplying this software for use with  * Infineon’s microcontrollers. * I * This file can be freely distributed within development tools that are $ * supporting such microcontrollers. *  * * @parN * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIEDE * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OFO * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.O * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,7 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. *P ******************************************************************************//*O * *************************** Change history *********************************F * V1.1, 13 Dec 2012, PKB, Created this table, added extern and stdintJ * V1.2, 19 Jul 2013, PKB, Added header guard, BootROM header, C++ support */#ifndef SYSTEM_XMC1100_H#define SYSTEM_XMC1100_HP/******************************************************************************* * HEADER FILESQ *******************************************************************************/#include P/******************************************************************************* * GLOBAL VARIABLESQ *******************************************************************************/ extern uint32_t SystemCoreClock;P/******************************************************************************* * API PROTOTYPESQ *******************************************************************************/#ifdef __cplusplus extern "C" {#endif/** * @brief Initialize the system * */void SystemInit(void);/**! * @brief Initialize CPU settings * */void SystemCoreSetup(void);/** * @brief Initialize clock * */ void SystemCoreClockSetup(void);/**) * @brief Update SystemCoreClock variable * */!void SystemCoreClockUpdate(void);#ifdef __cplusplus}#endif#endif xmc1100.h…N/****************************************************************************//**FCopyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.* ** @parN* Infineon Technologies AG (Infineon) is supplying this software for use with J* Infineon's microcontrollers. This file can be freely distributed within>* development tools that are supporting such microcontrollers.** @parJ* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIEDD* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OFN* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.N* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,6* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.*O******************************************************************************/i/****************************************************************************************************//** * @file XMC1100.h *D * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for# * XMC1100 from Infineon. *+ * @version V1.2.2 (Reference Manual v1.2) * @date 23. January 2015 *+ * @note Generated with SVDConv V2.86c c * from CMSIS SVD File 'XMC1100_Processed_SVD.xml' Version 1.2.2 (Reference Manual v1.2),i *******************************************************************************************************//** @addtogroup Infineon * @{ *//** @addtogroup XMC1100 * @{ */#ifndef XMC1100_H#define XMC1100_H#ifdef __cplusplus extern "C" {#endifV/* ------------------------- Interrupt Number Definition ------------------------ */typedef enum {V/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ SysTick_IRQn = -1, /*!< 15 System Tick Timer */V/* --------------------- XMC1100 Specific Interrupt Numbers --------------------- */O SCU_0_IRQn = 0, /*!< SCU SR0 Interrupt */O SCU_1_IRQn = 1, /*!< SCU SR1 Interrupt */O SCU_2_IRQn = 2, /*!< SCU SR2 Interrupt */O ERU0_0_IRQn = 3, /*!< ERU0 SR0 Interrupt */O ERU0_1_IRQn = 4, /*!< ERU0 SR1 Interrupt */O ERU0_2_IRQn = 5, /*!< ERU0 SR2 Interrupt */O ERU0_3_IRQn = 6, /*!< ERU0 SR3 Interrupt */ O USIC0_0_IRQn = 9, /*!< USIC SR0 Interrupt */O USIC0_1_IRQn = 10, /*!< USIC SR1 Interrupt */O USIC0_2_IRQn = 11, /*!< USIC SR2 Interrupt */O USIC0_3_IRQn = 12, /*!< USIC SR3 Interrupt */O USIC0_4_IRQn = 13, /*!< USIC SR4 Interrupt */O USIC0_5_IRQn = 14, /*!< USIC SR5 Interrupt */ O VADC0_C0_0_IRQn = 15, /*!< VADC SR0 Interrupt */O VADC0_C0_1_IRQn = 16, /*!< VADC SR1 Interrupt */ O CCU40_0_IRQn = 21, /*!< CCU40 SR0 Interrupt */O CCU40_1_IRQn = 22, /*!< CCU40 SR1 Interrupt */O CCU40_2_IRQn = 23, /*!< CCU40 SR2 Interrupt */O CCU40_3_IRQn = 24, /*!< CCU40 SR3 Interrupt */ } IRQn_Type;&/** @addtogroup Configuration_of_CMSIS * @{ */V/* ================================================================================ */V/* ================ Processor and Core Peripheral Section ================ */V/* ================================================================================ */c/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */#define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */#define __MPU_PRESENT 0 /*!< MPU present or not */#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */3/** @} */ /* End of group Configuration_of_CMSIS */#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */#include "system_XMC1100.h" /*!< XMC1100 System */V/* ================================================================================ */V/* ================ Device Specific Peripheral Section ================ */V/* ================================================================================ */5/* Macro to modify desired bitfields of a register */E#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \@ ((uint32_t)mask)) | \O (reg & ((uint32_t)~((uint32_t)mask)))5/* Macro to modify desired bitfields of a register */3#define WR_REG_SIZE(reg, mask, pos, val, size) { \Euint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \Guint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \@uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \Fuint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \&reg = (uint##size##_t) (VAL2 | VAL4);\}./** Macro to read bitfields from a register */H#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos)./** Macro to read bitfields from a register */M#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \O (uint32_t)mask) >> pos) )%/** Macro to set a bit in register */9#define SET_BIT(reg, pos) (reg |= ((uint32_t)1<#include #include L/* c++ destructor dynamic shared object needed if -fuse-cxa-atexit is used*/*void *__dso_handle __attribute__ ((weak));// defined in linker script extern caddr_t Heap_Bank1_Start;extern caddr_t Heap_Bank1_End;caddr_t _sbrk(int nbytes){! static caddr_t heap_ptr = NULL; caddr_t base; if (heap_ptr == NULL) {* heap_ptr = (caddr_t)&Heap_Bank1_Start; } base = heap_ptr; /* heap word alignment */ nbytes = (nbytes + 3) & ~0x3U;5 if ((caddr_t)&Heap_Bank1_End > (heap_ptr + nbytes)) { heap_ptr += nbytes; return (base); } else { /* Heap overflow */ errno = ENOMEM; return ((caddr_t)-1); }} /* Init */void _init(void){}#endif /* __GNUC__ */ xmc1_gpio.h0/** * @file xmc1_gpio.h * @date 2015-06-20 * * @condw *********************************************************************************************************************1 * XMClib v2.1.6 - XMC Peripheral Driver Library  *4 * Copyright (c) 2015-2016, Infineon Technologies AG/ * All rights reserved. / * s * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the # * following conditions are met: P * t * Redistributions of source code must retain the above copyright notice, this list of conditions and the following & * disclaimer.  * w * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following p * disclaimer in the documentation and/or other materials provided with the distribution.  * q * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote | * products derived from this software without specific prior written permission. P * v * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, v * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE w * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, t * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR u * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, w * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE y * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. P * w * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with i * Infineon Technologies AG dave@infineon.com). v ********************************************************************************************************************* * * Change History * -------------- * * 2015-02-20: * - Initial draft
 *  * 2015-06-20:G * - Removed version macros and declaration of GetDriverVersion API * * @endcond * */#ifndef XMC1_GPIO_H#define XMC1_GPIO_Hw/********************************************************************************************************************** * HEADER FILESw *********************************************************************************************************************/#include "xmc_common.h"#if UC_FAMILY == XMC1#include "xmc1_gpio_map.h"/**, * @addtogroup XMClib XMC Peripheral Library * @{ *//** * @addtogroup GPIO * @{ */w/********************************************************************************************************************** * MACROSw *********************************************************************************************************************/#if defined(PORT0)7#define XMC_GPIO_PORT0 ((XMC_GPIO_PORT_t *) PORT0_BASE);#define XMC_GPIO_CHECK_PORT0(port) (port == XMC_GPIO_PORT0)#else$#define XMC_GPIO_CHECK_PORT0(port) 0#endif#if defined(PORT1)7#define XMC_GPIO_PORT1 ((XMC_GPIO_PORT_t *) PORT1_BASE);#define XMC_GPIO_CHECK_PORT1(port) (port == XMC_GPIO_PORT1)#else$#define XMC_GPIO_CHECK_PORT1(port) 0#endif#if defined(PORT2)7#define XMC_GPIO_PORT2 ((XMC_GPIO_PORT_t *) PORT2_BASE);#define XMC_GPIO_CHECK_PORT2(port) (port == XMC_GPIO_PORT2)#else$#define XMC_GPIO_CHECK_PORT2(port) 0#endif#if defined(PORT3)7#define XMC_GPIO_PORT3 ((XMC_GPIO_PORT_t *) PORT3_BASE);#define XMC_GPIO_CHECK_PORT3(port) (port == XMC_GPIO_PORT3)#else$#define XMC_GPIO_CHECK_PORT3(port) 0#endif#if defined(PORT4)7#define XMC_GPIO_PORT4 ((XMC_GPIO_PORT_t *) PORT4_BASE);#define XMC_GPIO_CHECK_PORT4(port) (port == XMC_GPIO_PORT4)#else$#define XMC_GPIO_CHECK_PORT4(port) 0#endifB#define XMC_GPIO_CHECK_PORT(port) (XMC_GPIO_CHECK_PORT0(port) || \B XMC_GPIO_CHECK_PORT1(port) || \B XMC_GPIO_CHECK_PORT2(port) || \* XMC_GPIO_CHECK_PORT3(port) || \& XMC_GPIO_CHECK_PORT4(port))B#define XMC_GPIO_CHECK_OUTPUT_PORT(port) XMC_GPIO_CHECK_PORT(port)# A#define XMC_GPIO_CHECK_ANALOG_PORT(port) (port == XMC_GPIO_PORT2)# l#define XMC_GPIO_CHECK_INPUT_HYSTERESIS(hysteresis) ((hysteresis == XMC_GPIO_INPUT_HYSTERESIS_STANDARD) || \e (hysteresis == XMC_GPIO_INPUT_HYSTERESIS_LARGE))w/********************************************************************************************************************** * ENUMSw *********************************************************************************************************************//**s * Defines the direction and characteristics of a pin. Use type \a XMC_GPIO_MODE_t for this enum. For the operationx * with alternate functions, the port pins are directly connected to input or output functions of the on-chip periphery. */typedef enum XMC_GPIO_MODE{l XMC_GPIO_MODE_INPUT_TRISTATE = 0x0UL << PORT_IOCR_PC_Pos, /**< No internal pull device active */n XMC_GPIO_MODE_INPUT_PULL_DOWN = 0x1UL << PORT_IOCR_PC_Pos, /**< Internal pull-down device active */l XMC_GPIO_MODE_INPUT_PULL_UP = 0x2UL << PORT_IOCR_PC_Pos, /**< Internal pull-up device active */š XMC_GPIO_MODE_INPUT_SAMPLING = 0x3UL << PORT_IOCR_PC_Pos, /**< No internal pull device active; Pn_OUTx continuously samples the input value */u XMC_GPIO_MODE_INPUT_INVERTED_TRISTATE = 0x4UL << PORT_IOCR_PC_Pos, /**< Inverted no internal pull device active */w XMC_GPIO_MODE_INPUT_INVERTED_PULL_DOWN = 0x5UL << PORT_IOCR_PC_Pos, /**< Inverted internal pull-down device active */u XMC_GPIO_MODE_INPUT_INVERTED_PULL_UP = 0x6UL << PORT_IOCR_PC_Pos, /**< Inverted internal pull-up device active */¢ XMC_GPIO_MODE_INPUT_INVERTED_SAMPLING = 0x7UL << PORT_IOCR_PC_Pos, /**< Inverted no internal pull device active;Pn_OUTx continuously samples the input value */j XMC_GPIO_MODE_OUTPUT_PUSH_PULL = 0x80UL, /**< Push-pull general-purpose output */l XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN = 0xc0UL, /**< Open-drain general-purpose output */8 XMC_GPIO_MODE_OUTPUT_ALT1 = 0x1UL << PORT_IOCR_PC_Pos,8 XMC_GPIO_MODE_OUTPUT_ALT2 = 0x2UL << PORT_IOCR_PC_Pos,8 XMC_GPIO_MODE_OUTPUT_ALT3 = 0x3UL << PORT_IOCR_PC_Pos,8 XMC_GPIO_MODE_OUTPUT_ALT4 = 0x4UL << PORT_IOCR_PC_Pos,8 XMC_GPIO_MODE_OUTPUT_ALT5 = 0x5UL << PORT_IOCR_PC_Pos,8 XMC_GPIO_MODE_OUTPUT_ALT6 = 0x6UL << PORT_IOCR_PC_Pos,8 XMC_GPIO_MODE_OUTPUT_ALT7 = 0x7UL << PORT_IOCR_PC_Pos,#if (UC_SERIES == XMC14) 8 XMC_GPIO_MODE_OUTPUT_ALT8 = 0x8UL << PORT_IOCR_PC_Pos,8 XMC_GPIO_MODE_OUTPUT_ALT9 = 0x9UL << PORT_IOCR_PC_Pos,#endif “ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT1, /**< Push-pull alternate output function 1 */“ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT2, /**< Push-pull alternate output function 2 */“ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT3 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT3, /**< Push-pull alternate output function 3 */“ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT4, /**< Push-pull alternate output function 4 */“ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT5 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT5, /**< Push-pull alternate output function 5 */“ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT6 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT6, /**< Push-pull alternate output function 6 */“ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT7, /**< Push-pull alternate output function 7 */#if (UC_SERIES == XMC14) “ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT8 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT8, /**< Push-pull alternate output function 8 */“ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT9 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT9, /**< Push-pull alternate output function 9 */#endif– XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT1 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT1, /**< Open drain alternate output function 1 */– XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT2, /**< Open drain alternate output function 2 */– XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT3 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT3, /**< Open drain alternate output function 3 */– XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT4 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT4, /**< Open drain alternate output function 4 */– XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT5 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT5, /**< Open drain alternate output function 5 */– XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT6, /**< Open drain alternate output function 6 */– XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT7, /**< Open drain alternate output function 7 */#if (UC_SERIES == XMC14) – XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT8 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT8, /**< Open drain alternate output function 8 */• XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT9 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT9 /**< Open drain alternate output function 9 */#endif} XMC_GPIO_MODE_t;/**b * Configures input hysteresis mode of pin. Use type \a XMC_GPIO_INPUT_HYSTERESIS_t for this enum.U * Selecting the appropriate pad hysteresis allows optimized pad oscillation behavior" * for touch-sensing applications. */&typedef enum XMC_GPIO_INPUT_HYSTERESIS{H XMC_GPIO_INPUT_HYSTERESIS_STANDARD = 0x0U, /**< Standard hysteresis */E XMC_GPIO_INPUT_HYSTERESIS_LARGE = 0x4U /**< Large hysteresis */} XMC_GPIO_INPUT_HYSTERESIS_t;w/********************************************************************************************************************** * DATA STRUCTURESw *********************************************************************************************************************//**[ * Structure points port hardware registers. Use type XMC_GPIO_PORT_t for this structure. */typedef struct XMC_GPIO_PORT {d __IO uint32_t OUT; /**< The port output register determines the value of a GPIO pin when it is@ selected by Pn_IOCRx as output */f __O uint32_t OMR; /**< The port output modification register contains control bits that make itn possible to individually set, reset, or toggle the logic state of a single port& line*/ __I uint32_t RESERVED0[2];l __IO uint32_t IOCR[4]; /**< The port input/output control registers select the digital output and input] driver functionality and characteristics of a GPIO port pin */ __I uint32_t RESERVED1;l __I uint32_t IN; /**< The logic level of a GPIO pin can be read via the read-only port input register1 Pn_IN */ __I uint32_t RESERVED2[6];C __IO uint32_t PHCR[2]; /**< Pad hysteresis control register */ __I uint32_t RESERVED3[6];k __IO uint32_t PDISC; /**< Pin Function Decision Control Register is to disable/enable the digital padM structure in shared analog and digital ports*/ __I uint32_t RESERVED4[3];8 __IO uint32_t PPS; /**< Pin Power Save Register */? __IO uint32_t HWSEL; /**< Pin Hardware Select Register */} XMC_GPIO_PORT_t;/**R * Structure initializes port pin. Use type XMC_GPIO_CONFIG_t for this structure. */typedef struct XMC_GPIO_CONFIG{Y XMC_GPIO_MODE_t mode; /**< Defines the direction and characteristics of a pin */^ XMC_GPIO_INPUT_HYSTERESIS_t input_hysteresis; /**< Defines input pad hysteresis of a pin */P XMC_GPIO_OUTPUT_LEVEL_t output_level; /**< Defines output level of a pin */} XMC_GPIO_CONFIG_t;w/********************************************************************************************************************** * API PROTOTYPESw *********************************************************************************************************************/?__STATIC_INLINE bool XMC_GPIO_IsModeValid(XMC_GPIO_MODE_t mode){3 return ((mode == XMC_GPIO_MODE_INPUT_TRISTATE) ||4 (mode == XMC_GPIO_MODE_INPUT_PULL_DOWN) ||2 (mode == XMC_GPIO_MODE_INPUT_PULL_UP) ||3 (mode == XMC_GPIO_MODE_INPUT_SAMPLING) ||< (mode == XMC_GPIO_MODE_INPUT_INVERTED_TRISTATE) ||= (mode == XMC_GPIO_MODE_INPUT_INVERTED_PULL_DOWN) ||; (mode == XMC_GPIO_MODE_INPUT_INVERTED_PULL_UP) ||< (mode == XMC_GPIO_MODE_INPUT_INVERTED_SAMPLING) ||5 (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL) ||: (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1) ||: (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2) ||: (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT3) ||: (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4) ||: (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT5) ||: (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT6) ||: (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7) ||#if (UC_SERIES == XMC14): (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT8) ||: (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT9) ||#endif 6 (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN) ||; (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT1) ||; (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2) ||; (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT3) ||; (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT4) ||; (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT5) ||; (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6) ||9 (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7) #if (UC_SERIES == XMC14)> || (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT8) ||; (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT9)#endif  );}/** * @brief Sets pad hysteresis._ * @param port Constant pointer pointing to GPIO port, to access hardware register Pn_PHCR." * @param pin Port pin number.g * @param hysteresis input hysteresis selection. Refer data structure @ref XMC_GPIO_INPUT_HYSTERESIS_t * for details. * * @return None * * \parDescription:
x * Sets port pin input hysteresis. It configures hardware registers Pn_PHCR.\a hysteresis is initially configured duringk * initialization in XMC_GPIO_Init(). Call this API to alter pad hysteresis as needed later in the program. * * \parRelated APIs:
 * None * * \parNote:
\ * Prior to this api, user has to configure port pin to input mode using XMC_GPIO_SetMode(). * */>void XMC_GPIO_SetInputHysteresis(XMC_GPIO_PORT_t *const port, 4 const uint8_t pin, O const XMC_GPIO_INPUT_HYSTERESIS_t hysteresis);/** * @} (end addtogroup GPIO) *//** * @} (end addtogroup XMClib) */#endif /* UC_FAMILY == XMC1 */#endif /* XMC1_GPIO_H */ xmc1_scu.hõ/** * @file xmc1_scu.h * @date 2016-03-09 * * @condu*********************************************************************************************************************1 * XMClib v2.1.6 - XMC Peripheral Driver Library  *4 * Copyright (c) 2015-2016, Infineon Technologies AG * All rights reserved. *r * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: *s * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. *v * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the followingY * disclaimer in the documentation and/or other materials provided with the distribution. *p * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promoteQ * products derived from this software without specific prior written permission. *u * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,t * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AREv * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,r * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ORt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,v * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USEG * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *v * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with/ * Infineon Technologies AG dave@infineon.com).v ********************************************************************************************************************* * * Change History * -------------- * * 2015-02-20: * - Initial * * 2015-05-20:! * - Description updated
 * * 2015-06-20:H * - XMC_SCU_INTERRUPT_EVENT enum elements are typecasted to int64_t * * 2015-06-20:" * - Added support for XMC1400 * * 2015-11-30: * - Documentation improved * * 2015-12-09:I * - Added XMC_SCU_EnablePrefetchUnit and XMC_SCU_DisablePrefetchUnit *  * 2016-03-09:G * - Added XMC_SCU_POWER_EnableMonitor/XMC_SCU_POWER_DisableMonitor * * @endcond * */#ifndef XMC1_SCU_H#define XMC1_SCU_Hv/********************************************************************************************************************* * HEADER FILESv ********************************************************************************************************************/#include "xmc_common.h"#if UC_FAMILY == XMC1/**, * @addtogroup XMClib XMC Peripheral Library * @{ *//** * @addtogroup SCU * @{ */v/********************************************************************************************************************* * MACROSv ********************************************************************************************************************//** * List of events */n#define XMC_SCU_INTERRUPT_EVENT_WDT_WARN SCU_INTERRUPT_SRMSK_PRWARN_Msk /**< WDT pre-warning event. */k#define XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC SCU_INTERRUPT_SRCLR_PI_Msk /**< RTC periodic event. */h#define XMC_SCU_INTERRUPT_EVENT_RTC_ALARM SCU_INTERRUPT_SRCLR_AI_Msk /**< RTC alarm event. */o#define XMC_SCU_INTERRUPT_EVENT_VDDPI SCU_INTERRUPT_SRMSK_VDDPI_Msk /**< VDDP pre-warning event. */#if defined(COMPARATOR)y#define XMC_SCU_INTERRUPT_EVENT_ACMP0 SCU_INTERRUPT_SRMSK_ACMP0I_Msk /**< Analog comparator-0 output event. */y#define XMC_SCU_INTERRUPT_EVENT_ACMP1 SCU_INTERRUPT_SRMSK_ACMP1I_Msk /**< Analog comparator-1 output event. */y#define XMC_SCU_INTERRUPT_EVENT_ACMP2 SCU_INTERRUPT_SRMSK_ACMP2I_Msk /**< Analog comparator-2 output event. */,#if (UC_SERIES == XMC14) || defined(DOXYGEN)¶#define XMC_SCU_INTERRUPT_EVENT_ACMP3 (((int64_t)SCU_INTERRUPT_SRMSK1_ACMP3I_Msk) << 32U) /**< Analog comparator-3 output event. @note Only available for XMC1400 series */#endif#endife#define XMC_SCU_INTERRUPT_EVENT_VDROP SCU_INTERRUPT_SRMSK_VDROPI_Msk /**< VDROP event. */#if UC_SERIES != XMC11y#define XMC_SCU_INTERRUPT_EVENT_ORC0 SCU_INTERRUPT_SRMSK_ORC0I_Msk /**< Out of range comparator-0 event. */y#define XMC_SCU_INTERRUPT_EVENT_ORC1 SCU_INTERRUPT_SRMSK_ORC1I_Msk /**< Out of range comparator-1 event. */y#define XMC_SCU_INTERRUPT_EVENT_ORC2 SCU_INTERRUPT_SRMSK_ORC2I_Msk /**< Out of range comparator-2 event. */y#define XMC_SCU_INTERRUPT_EVENT_ORC3 SCU_INTERRUPT_SRMSK_ORC3I_Msk /**< Out of range comparator-3 event. */y#define XMC_SCU_INTERRUPT_EVENT_ORC4 SCU_INTERRUPT_SRMSK_ORC4I_Msk /**< Out of range comparator-4 event. */y#define XMC_SCU_INTERRUPT_EVENT_ORC5 SCU_INTERRUPT_SRMSK_ORC5I_Msk /**< Out of range comparator-5 event. */y#define XMC_SCU_INTERRUPT_EVENT_ORC6 SCU_INTERRUPT_SRMSK_ORC6I_Msk /**< Out of range comparator-6 event. */y#define XMC_SCU_INTERRUPT_EVENT_ORC7 SCU_INTERRUPT_SRMSK_ORC7I_Msk /**< Out of range comparator-7 event. */#endifm#define XMC_SCU_INTERRUPT_EVENT_LOCI SCU_INTERRUPT_SRMSK_LOCI_Msk /**< Loss of clock event. */r#define XMC_SCU_INTERRUPT_EVENT_PESRAM SCU_INTERRUPT_SRMSK_PESRAMI_Msk /**< PSRAM Parity error event. */r#define XMC_SCU_INTERRUPT_EVENT_PEUSIC0 SCU_INTERRUPT_SRMSK_PEU0I_Msk /**< USIC0 Parity error event. */#if defined(USIC1)‡#define XMC_SCU_INTERRUPT_EVENT_PEUSIC1 (((int64_t)SCU_INTERRUPT_SRMSK1_PEU1I_Msk) << 32U) /**< USIC1 Parity error event. */#endifz#define XMC_SCU_INTERRUPT_EVENT_FLASH_ERROR SCU_INTERRUPT_SRMSK_FLECC2I_Msk /**< Flash ECC double bit error event. */{#define XMC_SCU_INTERRUPT_EVENT_FLASH_COMPLETED SCU_INTERRUPT_SRCLR_FLCMPLTI_Msk /**< Flash operation completion event. */e#define XMC_SCU_INTERRUPT_EVENT_VCLIP SCU_INTERRUPT_SRMSK_VCLIPI_Msk /**< VCLIP event. */w#define XMC_SCU_INTERRUPT_EVENT_STDBYCLKFAIL SCU_INTERRUPT_SRMSK_SBYCLKFI_Msk /**< Standby clock failure event. */w#define XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED SCU_INTERRUPT_SRMSK_RTC_CTR_Msk /**< RTCCTR register update event. */{#define XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk /**< RTCATIM0 register update event. */{#define XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk /**< RTCATIM1 register update event. */y#define XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk /**< RTCTIM0 register update event. */y#define XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk /**< RTCTIM1 register update event. */„#define XMC_SCU_INTERRUPT_EVENT_TSE_DONE SCU_INTERRUPT_SRMSK_TSE_DONE_Msk /**< Temperature measurement Completion event. */v#define XMC_SCU_INTERRUPT_EVENT_TSE_HIGH SCU_INTERRUPT_SRMSK_TSE_HIGH_Msk /**< Temperature too high event. */s#define XMC_SCU_INTERRUPT_EVENT_TSE_LOW SCU_INTERRUPT_SRMSK_TSE_LOW_Msk /**< Temperature too low event. */#if defined(CAN)#define XMC_SCU_INTERRUPT_EVENT_PEMCAN (((int64_t)SCU_INTERRUPT_SRMSK1_PEMCI_Msk) << 32U) /**< MultiCAN SRAM Parity Error Event. */#endif,#if (UC_SERIES == XMC14) || defined(DOXYGEN)¹#define XMC_SCU_INTERRUPT_EVENT_LOSS_EXT_CLOCK (((int64_t)SCU_INTERRUPT_SRMSK1_LOECI_Msk) << 32U) /**< Loss of external OSC_HP clock event. @note Only available for XMC1400 series */±#define XMC_SCU_INTERRUPT_EVENT_DCO1_OUT_SYNC (((int64_t)SCU_INTERRUPT_SRMSK1_DCO1OFSI_Msk) << 32U) /**< DCO1 Out of SYNC Event. @note Only available for XMC1400 series */#endifv/********************************************************************************************************************* * ENUMSv ********************************************************************************************************************//**Y * Defines the cause of last reset. The cause of last reset gets automatically stored inv * the \a SCU_RSTSTAT register and can be checked by user software to determine the state of the system and for debug] * purpose. All the enum items are tabulated as per bits present in \a SCU_RSTSTAT register.K * Use type \a XMC_SCU_RESET_REASON_t for accessing these enum parameters. */!typedef enum XMC_SCU_RESET_REASON{s XMC_SCU_RESET_REASON_PORST = (1UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Power On reset. */q XMC_SCU_RESET_REASON_MASTER = (2UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Master reset. */} XMC_SCU_RESET_REASON_SW = (4UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Software initiated reset. */o XMC_SCU_RESET_REASON_LOCKUP = (8UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to CPU lockup. */p XMC_SCU_RESET_REASON_FLASH = (16UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to flash error. */m XMC_SCU_RESET_REASON_WATCHDOG = (32UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to watchdog. */o XMC_SCU_RESET_REASON_CLOCK_LOSS = (64UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to clock loss. */u XMC_SCU_RESET_REASON_PARITY_ERROR = (128UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos) /**< Reset due to RAM parity error. */} XMC_SCU_RESET_REASON_t;/**u * Defines the reset sources that can cause device reset. These enums can be used to configure reset source in resett * control \a RSTCON register which enables different reset sources to identify the reset cause. The \a SCU_RSTSTAT_ * register can be checked by user software to determine the state of the system and for debug\ * purpose. Use type \a XMC_SCU_SYSTEM_RESET_REQUEST_t for accessing these enum parameters. */)typedef enum XMC_SCU_SYSTEM_RESET_REQUEST{~ XMC_SCU_RESET_REQUEST_FLASH_ECC_ERROR = SCU_RESET_RSTCON_ECCRSTEN_Msk, /**< Reset when ECC double bit error occurs.*/w XMC_SCU_RESET_REQUEST_CLOCK_LOSS = SCU_RESET_RSTCON_LOCRSTEN_Msk, /**< Reset when loss of clock occurs.*/{ XMC_SCU_RESET_REQUEST_SRAM_PARITY_ERROR = SCU_RESET_RSTCON_SPERSTEN_Msk, /**< Reset when SRAM parity error occurs.*/ƒ XMC_SCU_RESET_REQUEST_USIC_SRAM_PARITY_ERROR = SCU_RESET_RSTCON_U0PERSTEN_Msk /**< Reset when USIC0 memory parity error occurs.*/!} XMC_SCU_SYSTEM_RESET_REQUEST_t;/**g * Defines list of events that can generate SCU interrupt. These enums can be used to configure eventsi * in \a SRMSK register for assertion of interrupt. All the enum items are tabulated as per bits presentj * in \a SRMSK register. Use type \a XMC_SCU_INTERRUPT_EVENT_t for accessing these enum parameters. TheseY * enums can also be used for checking the status of events from the \a SRSTAT register. */#if (UC_SERIES == XMC14)+typedef uint64_t XMC_SCU_INTERRUPT_EVENT_t;#else+typedef uint32_t XMC_SCU_INTERRUPT_EVENT_t;#endif/**{ * Defines possible sources of RTC clock. These enums can be used to configure \a RTCCLKSEL bits of \a CLKCR Clock ControlX * Register. Use type \a XMC_SCU_CLOCK_RTCCLKSRC_t for accessing these enum parameters. */$typedef enum XMC_SCU_CLOCK_RTCCLKSRC{s XMC_SCU_CLOCK_RTCCLKSRC_DCO2 = (0x0UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos), /**< RTC clock source is standby clock. */z XMC_SCU_CLOCK_RTCCLKSRC_ERU_IOUT0 = (0x1UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos), /**< RTC clock source is external clock froma ERU0.IOUT0. */z XMC_SCU_CLOCK_RTCCLKSRC_ACMP0_OUT = (0x2UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos), /**< RTC clock source is external clock from` ACMP0.OUT. */z XMC_SCU_CLOCK_RTCCLKSRC_ACMP1_OUT = (0x3UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos), /**< RTC clock source is external clock from_ ACMP1.OUT. */z XMC_SCU_CLOCK_RTCCLKSRC_ACMP2_OUT = (0x4UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos), /**< RTC clock source is external clock from_ ACMP2.OUT. */,#if (UC_SERIES == XMC14) || defined(DOXYGEN)™ XMC_SCU_CLOCK_RTCCLKSRC_OSCLP = (0x5UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos) /**< 32.768kHz XTAL clock via OSC_LP. @note Only available for XMC1400 series */#endif} XMC_SCU_CLOCK_RTCCLKSRC_t;/**y * Defines possible sources of peripheral clock (PCLK). These enums can be used to configure \a PCLKSEL bits of \a CLKCRd * Clock Control Register. Use type \a XMC_SCU_CLOCK_PCLKSRC_t for accessing these enum parameters. */"typedef enum XMC_SCU_CLOCK_PCLKSRC{g XMC_SCU_CLOCK_PCLKSRC_MCLK = (0UL << SCU_CLK_CLKCR_PCLKSEL_Pos), /**< MCLK as the source for PCLK. */r XMC_SCU_CLOCK_PCLKSRC_DOUBLE_MCLK = (1UL << SCU_CLK_CLKCR_PCLKSEL_Pos) /**< Source of PCLK is twice the MCLK. */} XMC_SCU_CLOCK_PCLKSRC_t;,#if (UC_SERIES == XMC14) || defined(DOXYGEN)/** * DCLK clock source selection) * @note Only available in XMC1400 series */"typedef enum XMC_SCU_CLOCK_DCLKSRC{j XMC_SCU_CLOCK_DCLKSRC_DCO1 = 0UL << SCU_CLK_CLKCR1_DCLKSEL_Pos, /**< Internal oscillator DCO1 (48MHz) */i XMC_SCU_CLOCK_DCLKSRC_EXT_XTAL = 1UL << SCU_CLK_CLKCR1_DCLKSEL_Pos, /**< External crystal oscillator */} XMC_SCU_CLOCK_DCLKSRC_t;/** * OSCHP mode) * @note Only available in XMC1400 series */%typedef enum XMC_SCU_CLOCK_OSCHP_MODE{” XMC_SCU_CLOCK_OSCHP_MODE_OSC = 0UL << SCU_ANALOG_ANAOSCHPCTRL_MODE_Pos, /**< Oscillator is enabled and in active power mode with shaper enabled */† XMC_SCU_CLOCK_OSCHP_MODE_DIRECT = 1UL << SCU_ANALOG_ANAOSCHPCTRL_MODE_Pos, /**< Oscillator in power down mode with shaper enabled */ˆ XMC_SCU_CLOCK_OSCHP_MODE_DISABLED = 3UL << SCU_ANALOG_ANAOSCHPCTRL_MODE_Pos, /**< Oscillator in power down mode with shaper enabled */} XMC_SCU_CLOCK_OSCHP_MODE_t;/** * OSCLP mode) * @note Only available in XMC1400 series */%typedef enum XMC_SCU_CLOCK_OSCLP_MODE{” XMC_SCU_CLOCK_OSCLP_MODE_OSC = 0UL << SCU_ANALOG_ANAOSCLPCTRL_MODE_Pos, /**< Oscillator is enabled and in active power mode with shaper enabled */ˆ XMC_SCU_CLOCK_OSCLP_MODE_DISABLED = 3UL << SCU_ANALOG_ANAOSCLPCTRL_MODE_Pos, /**< Oscillator in power down mode with shaper enabled */} XMC_SCU_CLOCK_OSCLP_MODE_t;/**# * Clock source for synchronization) * @note Only available in XMC1400 series */&typedef enum XMC_SCU_CLOCK_SYNC_CLKSRC{K XMC_SCU_CLOCK_SYNC_CLKSRC_OSCLP = 0U << SCU_ANALOG_ANASYNC1_XTAL_SEL_Pos,K XMC_SCU_CLOCK_SYNC_CLKSRC_OSCHP = 1U << SCU_ANALOG_ANASYNC1_XTAL_SEL_Pos,} XMC_SCU_CLOCK_SYNC_CLKSRC_t;!#endif /* (UC_SERIES == XMC14) *//**m * Defines the list of peripherals that support clock gating. After a master reset, only core, memories, SCUd * and PORT peripheral are not clock gated. The rest of the peripherals are by default clock gated.R * All the enum items are tabulated as per bits present in \a CGATSTAT0 register.O * Use type \a XMC_SCU_PERIPHERAL_CLOCK_t for accessing these enum parameters.4 * @note Peripherals availability depends on device */%typedef enum XMC_SCU_PERIPHERAL_CLOCK{#if defined(VADC)c XMC_SCU_PERIPHERAL_CLOCK_VADC = SCU_CLK_CGATSTAT0_VADC_Msk, /**< VADC peripheral clock gate. */#endif#if defined(CCU80)e XMC_SCU_PERIPHERAL_CLOCK_CCU80 = SCU_CLK_CGATSTAT0_CCU80_Msk, /**< CCU80 peripheral clock gate. */#endif#if defined(CCU40)e XMC_SCU_PERIPHERAL_CLOCK_CCU40 = SCU_CLK_CGATSTAT0_CCU40_Msk, /**< CCU40 peripheral clock gate. */#endif#if defined(USIC0)e XMC_SCU_PERIPHERAL_CLOCK_USIC0 = SCU_CLK_CGATSTAT0_USIC0_Msk, /**< USIC0 peripheral clock gate. */#endif#if defined(BCCU0)e XMC_SCU_PERIPHERAL_CLOCK_BCCU0 = SCU_CLK_CGATSTAT0_BCCU0_Msk, /**< BCCU0 peripheral clock gate. */#endif#if defined(LEDTS0)g XMC_SCU_PERIPHERAL_CLOCK_LEDTS0 = SCU_CLK_CGATSTAT0_LEDTS0_Msk, /**< LEDTS0 peripheral clock gate. */#endif#if defined(LEDTS1)g XMC_SCU_PERIPHERAL_CLOCK_LEDTS1 = SCU_CLK_CGATSTAT0_LEDTS1_Msk, /**< LEDTS1 peripheral clock gate. */#endif#if defined(POSIF0)g XMC_SCU_PERIPHERAL_CLOCK_POSIF0 = SCU_CLK_CGATSTAT0_POSIF0_Msk, /**< POSIF0 peripheral clock gate. */#endif#if defined(MATH)c XMC_SCU_PERIPHERAL_CLOCK_MATH = SCU_CLK_CGATSTAT0_MATH_Msk, /**< MATH peripheral clock gate. */#endifa XMC_SCU_PERIPHERAL_CLOCK_WDT = SCU_CLK_CGATSTAT0_WDT_Msk, /**< WDT peripheral clock gate. */a XMC_SCU_PERIPHERAL_CLOCK_RTC = SCU_CLK_CGATSTAT0_RTC_Msk, /**< RTC peripheral clock gate. */#if defined(CCU81)e XMC_SCU_PERIPHERAL_CLOCK_CCU81 = SCU_CLK_CGATSTAT0_CCU81_Msk, /**< CCU80 peripheral clock gate. */#endif#if defined(CCU41)e XMC_SCU_PERIPHERAL_CLOCK_CCU41 = SCU_CLK_CGATSTAT0_CCU41_Msk, /**< CCU80 peripheral clock gate. */#endif#if defined(USIC1)e XMC_SCU_PERIPHERAL_CLOCK_USIC1 = SCU_CLK_CGATSTAT0_USIC1_Msk, /**< USIC0 peripheral clock gate. */#endif#if defined(LEDTS2)g XMC_SCU_PERIPHERAL_CLOCK_LEDTS2 = SCU_CLK_CGATSTAT0_LEDTS2_Msk, /**< LEDTS1 peripheral clock gate. */#endif#if defined(POSIF1)g XMC_SCU_PERIPHERAL_CLOCK_POSIF1 = SCU_CLK_CGATSTAT0_POSIF1_Msk, /**< POSIF0 peripheral clock gate. */#endif#if defined(CAN)d XMC_SCU_PERIPHERAL_CLOCK_MCAN = SCU_CLK_CGATSTAT0_MCAN0_Msk, /**< POSIF0 peripheral clock gate. */#endif} XMC_SCU_PERIPHERAL_CLOCK_t;/** * Defines options for Capture/Compare unit timer slice trigger that enables synchronous start function available on the \a SCU,^ * \a CCUCON register. Use type \a XMC_SCU_CCU_TRIGGER_t for accessing these enum parameters. */ typedef enum XMC_SCU_CCU_TRIGGER{] XMC_SCU_CCU_TRIGGER_CCU40 = SCU_GENERAL_CCUCON_GSC40_Msk, /**< Trigger CCU40 peripheral. */#if defined(CCU80)] XMC_SCU_CCU_TRIGGER_CCU80 = SCU_GENERAL_CCUCON_GSC80_Msk, /**< Trigger CCU80 peripheral. */#endif#if defined(CCU41)] XMC_SCU_CCU_TRIGGER_CCU41 = SCU_GENERAL_CCUCON_GSC41_Msk, /**< Trigger CCU40 peripheral. */#endif#if defined(CCU81)] XMC_SCU_CCU_TRIGGER_CCU81 = SCU_GENERAL_CCUCON_GSC81_Msk, /**< Trigger CCU80 peripheral. */#endif} XMC_SCU_CCU_TRIGGER_t;,#if (UC_SERIES == XMC14) || defined(DOXYGEN)/**? * Selects the service request connected to the interrupt node.# * @image html "xmc1400_irqmux.png"* * @note Only available for XMC1400 series */typedef enum XMC_SCU_IRQCTRL{` XMC_SCU_IRQCTRL_SCU_SR0_IRQ0 = (0U << 8U) | 0U, /**< SCU_SR0 connected to IRQ0 */#if defined(CAN)a XMC_SCU_IRQCTRL_CAN0_SR0_IRQ0 = (0U << 8U) | 1U, /**< CAN0_SR0 connected to IRQ0 */#endifb XMC_SCU_IRQCTRL_CCU40_SR0_IRQ0 = (0U << 8U) | 2U, /**< CCU40_SR0 connected to IRQ0 */#if defined(CAN)t XMC_SCU_IRQCTRL_SCU_SR0_OR_CAN0_SR0_IRQ0 = (0U << 8U) | 3U, /**< SCU_SR0 and CAN_SR0 are both connected to IRQ0*/#endif` XMC_SCU_IRQCTRL_SCU_SR1_IRQ1 = (1U << 8U) | 0U, /**< SCU_SR1 connected to IRQ1 */#if defined(CAN)a XMC_SCU_IRQCTRL_CAN0_SR1_IRQ1 = (1U << 8U) | 1U, /**< CAN0_SR1 connected to IRQ1 */#endif#if defined(CCU80)b XMC_SCU_IRQCTRL_CCU80_SR0_IRQ1 = (1U << 8U) | 2U, /**< CCU80_SR0 connected to IRQ1 */#endif#if defined(CAN)m XMC_SCU_IRQCTRL_SCU_SR1_OR_CAN0_SR1_IRQ1 = (1U << 8U) | 3U, /**< SCU_SR1 and CAN0_SR1 connected to IRQ1 */#endif` XMC_SCU_IRQCTRL_SCU_SR2_IRQ2 = (2U << 8U) | 0U, /**< SCU_SR2 connected to IRQ2 */#if defined(CAN)a XMC_SCU_IRQCTRL_CAN0_SR2_IRQ2 = (2U << 8U) | 1U, /**< CAN0_SR2 connected to IRQ2 */#endif#if defined(CCU80)b XMC_SCU_IRQCTRL_CCU80_SR1_IRQ2 = (2U << 8U) | 2U, /**< CCU80_SR1 connected to IRQ2 */#endif#if defined(CAN)m XMC_SCU_IRQCTRL_SCU_SR2_OR_CAN0_SR2_IRQ2 = (2U << 8U) | 3U, /**< SCU_SR2 and CAN0_SR2 connected to IRQ2 */#endifa XMC_SCU_IRQCTRL_ERU0_SR0_IRQ3 = (3U << 8U) | 0U, /**< ERU0_SR0 connected to IRQ3 */a XMC_SCU_IRQCTRL_ERU1_SR0_IRQ3 = (3U << 8U) | 1U, /**< ERU1_SR0 connected to IRQ3 */#if defined(CAN)a XMC_SCU_IRQCTRL_CAN0_SR0_IRQ3 = (3U << 8U) | 2U, /**< CAN0_SR0 connected to IRQ3 */#endifn XMC_SCU_IRQCTRL_ERU0_SR0_OR_ERU1_SR0_IRQ3 = (3U << 8U) | 3U, /**< ERU0_SR0 and ERU1_SR0 connected to IRQ3 */a XMC_SCU_IRQCTRL_ERU0_SR1_IRQ4 = (4U << 8U) | 0U, /**< ERU0_SR1 connected to IRQ4 */a XMC_SCU_IRQCTRL_ERU1_SR1_IRQ4 = (4U << 8U) | 1U, /**< ERU1_SR1 connected to IRQ4 */#if defined(CAN)a XMC_SCU_IRQCTRL_CAN0_SR1_IRQ4 = (4U << 8U) | 2U, /**< CAN0_SR1 connected to IRQ4 */#endifn XMC_SCU_IRQCTRL_ERU0_SR1_OR_ERU1_SR1_IRQ4 = (4U << 8U) | 3U, /**< ERU0_SR1 and ERU1_SR1 connected to IRQ4 */a XMC_SCU_IRQCTRL_ERU0_SR2_IRQ5 = (5U << 8U) | 0U, /**< ERU0_SR2 connected to IRQ5 */a XMC_SCU_IRQCTRL_ERU1_SR2_IRQ5 = (5U << 8U) | 1U, /**< ERU1_SR2 connected to IRQ5 */#if defined(CAN)a XMC_SCU_IRQCTRL_CAN0_SR2_IRQ5 = (5U << 8U) | 2U, /**< CAN0_SR2 connected to IRQ5 */#endifn XMC_SCU_IRQCTRL_ERU0_SR2_OR_ERU1_SR2_IRQ5 = (5U << 8U) | 3U, /**< ERU0_SR2 and ERU1_SR2 connected to IRQ5 */a XMC_SCU_IRQCTRL_ERU0_SR3_IRQ6 = (6U << 8U) | 0U, /**< ERU0_SR3 connected to IRQ6 */a XMC_SCU_IRQCTRL_ERU1_SR3_IRQ6 = (6U << 8U) | 1U, /**< ERU1_SR3 connected to IRQ6 */#if defined(CAN)a XMC_SCU_IRQCTRL_CAN0_SR3_IRQ6 = (6U << 8U) | 2U, /**< CAN0_SR3 connected to IRQ6 */#endifn XMC_SCU_IRQCTRL_ERU0_SR3_OR_ERU1_SR3_IRQ6 = (6U << 8U) | 3U, /**< ERU0_SR3 and ERU1_SR3 connected to IRQ6 */#if defined(MATH)d XMC_SCU_IRQCTRL_MATH_SR0_IRQ7 = (7U << 8U) | 0U, /**< MATH_SR0 connected to IRQ7 */#endif#if defined(CAN)d XMC_SCU_IRQCTRL_CAN0_SR3_IRQ7 = (7U << 8U) | 1U, /**< CAN0_SR3 connected to IRQ7 */#endife XMC_SCU_IRQCTRL_CCU40_SR1_IRQ7 = (7U << 8U) | 2U, /**< CCU40_SR1 connected to IRQ7 */!#if defined(MATH) && defined(CAN)q XMC_SCU_IRQCTRL_MATH_SR0_OR_CAN0_SR3_IRQ7 = (7U << 8U) | 3U, /**< MATH_SR0 and CAN0_SR3 connected to IRQ7 */#endif#if defined(LEDTS2)f XMC_SCU_IRQCTRL_LEDTS2_SR0_IRQ8 = (8U << 8U) | 0U, /**< LEDTS2_SR0 connected to IRQ8 */#endife XMC_SCU_IRQCTRL_CCU40_SR0_IRQ8 = (8U << 8U) | 1U, /**< CCU40_SR0 connected to IRQ8 */#if defined(CCU80)e XMC_SCU_IRQCTRL_CCU80_SR0_IRQ8 = (8U << 8U) | 2U, /**< CCU80_SR0 connected to IRQ8 */#endif#if defined(LEDTS2)t XMC_SCU_IRQCTRL_LEDTS2_SR0_OR_CCU40_SR0_IRQ8 = (8U << 8U) | 3U, /**< LEDTS2_SR0 and CCU40_SR0 connected to IRQ8 */#endife XMC_SCU_IRQCTRL_USIC0_SR0_IRQ9 = (9U << 8U) | 0U, /**< USIC0_SR0 connected to IRQ9 */#if defined(USIC1)e XMC_SCU_IRQCTRL_USIC1_SR0_IRQ9 = (9U << 8U) | 1U, /**< USIC1_SR0 connected to IRQ9 */#endifd XMC_SCU_IRQCTRL_ERU0_SR0_IRQ9 = (9U << 8U) | 2U, /**< ERU0_SR0 connected to IRQ9 */#if defined(USIC1)s XMC_SCU_IRQCTRL_USIC0_SR0_OR_USIC1_SR0_IRQ9 = (9U << 8U) | 3U, /**< USIC0_SR0 and USIC1_SR0 connected to IRQ9 */#endifg XMC_SCU_IRQCTRL_USIC0_SR1_IRQ10 = (10U << 8U) | 0U, /**< USIC0_SR1 connected to IRQ10 */#if defined(USIC1)g XMC_SCU_IRQCTRL_USIC1_SR1_IRQ10 = (10U << 8U) | 1U, /**< USIC1_SR1 connected to IRQ10 */#endiff XMC_SCU_IRQCTRL_ERU0_SR1_IRQ10 = (10U << 8U) | 2U, /**< ERU0_SR1 connected to IRQ10 */#if defined(USIC1)u XMC_SCU_IRQCTRL_USIC0_SR1_OR_USIC1_SR1_IRQ10 = (10U << 8U) | 3U, /**< USIC0_SR1 and USIC1_SR1 connected to IRQ10 */#endifg XMC_SCU_IRQCTRL_USIC0_SR2_IRQ11 = (11U << 8U) | 0U, /**< USIC0_SR2 connected to IRQ11 */#if defined(USIC1)g XMC_SCU_IRQCTRL_USIC1_SR2_IRQ11 = (11U << 8U) | 1U, /**< USIC1_SR2 connected to IRQ11 */#endiff XMC_SCU_IRQCTRL_ERU0_SR2_IRQ11 = (11U << 8U) | 2U, /**< ERU0_SR2 connected to IRQ11 */#if defined(USIC1)u XMC_SCU_IRQCTRL_USIC0_SR2_OR_USIC1_SR2_IRQ11 = (11U << 8U) | 3U, /**< USIC0_SR2 and USIC1_SR2 connected to IRQ11 */#endifg XMC_SCU_IRQCTRL_USIC0_SR3_IRQ12 = (12U << 8U) | 0U, /**< USIC0_SR3 connected to IRQ12 */#if defined(USIC1)g XMC_SCU_IRQCTRL_USIC1_SR3_IRQ12 = (12U << 8U) | 1U, /**< USIC1_SR3 connected to IRQ12 */#endiff XMC_SCU_IRQCTRL_ERU0_SR3_IRQ12 = (12U << 8U) | 2U, /**< ERU0_SR3 connected to IRQ12 */#if defined(USIC1)u XMC_SCU_IRQCTRL_USIC0_SR3_OR_USIC1_SR3_IRQ12 = (12U << 8U) | 3U, /**< USIC0_SR3 and USIC1_SR3 connected to IRQ12 */#endifg XMC_SCU_IRQCTRL_USIC0_SR4_IRQ13 = (13U << 8U) | 0U, /**< USIC0_SR4 connected to IRQ13 */#if defined(USIC1)g XMC_SCU_IRQCTRL_USIC1_SR4_IRQ13 = (13U << 8U) | 1U, /**< USIC1_SR4 connected to IRQ13 */#endif#if defined(CCU80)g XMC_SCU_IRQCTRL_CCU80_SR1_IRQ13 = (13U << 8U) | 2U, /**< CCU80_SR1 connected to IRQ13 */#endif#if defined(USIC1)u XMC_SCU_IRQCTRL_USIC0_SR4_OR_USIC1_SR4_IRQ13 = (13U << 8U) | 3U, /**< USIC0_SR4 and USIC1_SR4 connected to IRQ13 */#endifg XMC_SCU_IRQCTRL_USIC0_SR5_IRQ14 = (14U << 8U) | 0U, /**< USIC0_SR5 connected to IRQ14 */#if defined(USIC1)g XMC_SCU_IRQCTRL_USIC1_SR5_IRQ14 = (14U << 8U) | 1U, /**< USIC1_SR5 connected to IRQ14 */#endif#if defined(POSIF0)h XMC_SCU_IRQCTRL_POSIF0_SR0_IRQ14 = (14U << 8U) | 2U, /**< POSIF0_SR0 connected to IRQ14 */#endif#if defined(USIC1)u XMC_SCU_IRQCTRL_USIC0_SR5_OR_USIC1_SR5_IRQ14 = (14U << 8U) | 3U, /**< USIC0_SR5 and USIC1_SR5 connected to IRQ14 */#endifk XMC_SCU_IRQCTRL_VADC0_C0SR0_IRQ15 = (15U << 8U) | 0U, /**< VADC0_C0SR0 connected to IRQ15 */i XMC_SCU_IRQCTRL_USIC0_SR0_IRQ15 = (15U << 8U) | 1U, /**< USIC0_SR0 connected to IRQ15 */#if defined(POSIF0)j XMC_SCU_IRQCTRL_POSIF0_SR1_IRQ15 = (15U << 8U) | 2U, /**< POSIF0_SR1 connected to IRQ15 */#endify XMC_SCU_IRQCTRL_VADC0_C0SR0_OR_USIC0_SR0_IRQ15 = (15U << 8U) | 3U, /**< VADC0_C0SR0 and USIC0_SR0 connected to IRQ15 */k XMC_SCU_IRQCTRL_VADC0_C0SR1_IRQ16 = (16U << 8U) | 0U, /**< VADC0_C0SR1 connected to IRQ16 */i XMC_SCU_IRQCTRL_USIC0_SR1_IRQ16 = (16U << 8U) | 1U, /**< USIC0_SR1 connected to IRQ16 */i XMC_SCU_IRQCTRL_CCU40_SR2_IRQ16 = (16U << 8U) | 2U, /**< CCU40_SR2 connected to IRQ16 */y XMC_SCU_IRQCTRL_VADC0_C0SR1_OR_USIC0_SR1_IRQ16 = (16U << 8U) | 3U, /**< VADC0_C0SR1 and USIC0_SR1 connected to IRQ16 */k XMC_SCU_IRQCTRL_VADC0_G0SR0_IRQ17 = (17U << 8U) | 0U, /**< VADC0_G0SR0 connected to IRQ17 */i XMC_SCU_IRQCTRL_USIC0_SR2_IRQ17 = (17U << 8U) | 1U, /**< USIC0_SR2 connected to IRQ17 */#if defined(CAN)h XMC_SCU_IRQCTRL_CAN0_SR0_IRQ17 = (17U << 8U) | 2U, /**< CAN0_SR0 connected to IRQ17 */#endify XMC_SCU_IRQCTRL_VADC0_G0SR0_OR_USIC0_SR2_IRQ17 = (17U << 8U) | 3U, /**< VADC0_G0SR0 and USIC0_SR2 connected to IRQ17 */k XMC_SCU_IRQCTRL_VADC0_G0SR1_IRQ18 = (18U << 8U) | 0U, /**< VADC0_G0SR1 connected to IRQ18 */i XMC_SCU_IRQCTRL_USIC0_SR3_IRQ18 = (18U << 8U) | 1U, /**< USIC0_SR3 connected to IRQ18 */#if defined(CAN)h XMC_SCU_IRQCTRL_CAN0_SR1_IRQ18 = (18U << 8U) | 2U, /**< CAN0_SR1 connected to IRQ18 */#endify XMC_SCU_IRQCTRL_VADC0_G0SR1_OR_USIC0_SR3_IRQ18 = (18U << 8U) | 3U, /**< VADC0_G0SR1 and USIC0_SR3 connected to IRQ18 */k XMC_SCU_IRQCTRL_VADC0_G1SR0_IRQ19 = (19U << 8U) | 0U, /**< VADC0_G1SR0 connected to IRQ19 */i XMC_SCU_IRQCTRL_USIC0_SR4_IRQ19 = (19U << 8U) | 1U, /**< USIC0_SR4 connected to IRQ19 */#if defined(CAN)h XMC_SCU_IRQCTRL_CAN0_SR2_IRQ19 = (19U << 8U) | 2U, /**< CAN0_SR2 connected to IRQ19 */#endify XMC_SCU_IRQCTRL_VADC0_G1SR0_OR_USIC0_SR4_IRQ19 = (19U << 8U) | 3U, /**< VADC0_G1SR0 and USIC0_SR4 connected to IRQ19 */k XMC_SCU_IRQCTRL_VADC0_G1SR1_IRQ20 = (20U << 8U) | 0U, /**< VADC0_G1SR1 connected to IRQ20 */i XMC_SCU_IRQCTRL_USIC0_SR5_IRQ20 = (20U << 8U) | 1U, /**< USIC0_SR5 connected to IRQ20 */#if defined(CAN)h XMC_SCU_IRQCTRL_CAN0_SR4_IRQ20 = (20U << 8U) | 2U, /**< CAN0_SR4 connected to IRQ20 */#endify XMC_SCU_IRQCTRL_VADC0_G1SR1_OR_USIC0_SR5_IRQ20 = (20U << 8U) | 3U, /**< VADC0_G1SR1 and USIC0_SR5 connected to IRQ20 */i XMC_SCU_IRQCTRL_CCU40_SR0_IRQ21 = (21U << 8U) | 0U, /**< CCU40_SR0 connected to IRQ21 */#if defined(CCU41)i XMC_SCU_IRQCTRL_CCU41_SR0_IRQ21 = (21U << 8U) | 1U, /**< CCU41_SR0 connected to IRQ21 */#endifi XMC_SCU_IRQCTRL_USIC0_SR0_IRQ21 = (21U << 8U) | 2U, /**< USIC0_SR0 connected to IRQ21 */#if defined(CCU41)w XMC_SCU_IRQCTRL_CCU40_SR0_OR_CCU41_SR0_IRQ21 = (21U << 8U) | 3U, /**< CCU40_SR0 and CCU41_SR0 connected to IRQ21 */#endifi XMC_SCU_IRQCTRL_CCU40_SR1_IRQ22 = (22U << 8U) | 0U, /**< CCU40_SR1 connected to IRQ22 */#if defined(CCU41)i XMC_SCU_IRQCTRL_CCU41_SR1_IRQ22 = (22U << 8U) | 1U, /**< CCU41_SR1 connected to IRQ22 */#endifi XMC_SCU_IRQCTRL_USIC0_SR1_IRQ22 = (22U << 8U) | 2U, /**< USIC0_SR1 connected to IRQ22 */#if defined(CCU41)w XMC_SCU_IRQCTRL_CCU40_SR0_OR_CCU41_SR0_IRQ22 = (22U << 8U) | 3U, /**< CCU40_SR0 and CCU41_SR0 connected to IRQ22 */#endifi XMC_SCU_IRQCTRL_CCU40_SR2_IRQ23 = (23U << 8U) | 0U, /**< CCU40_SR2 connected to IRQ23 */#if defined(CCU41)i XMC_SCU_IRQCTRL_CCU41_SR2_IRQ23 = (23U << 8U) | 1U, /**< CCU41_SR2 connected to IRQ23 */#endifi XMC_SCU_IRQCTRL_USIC0_SR2_IRQ23 = (23U << 8U) | 2U, /**< USIC0_SR2 connected to IRQ23 */#if defined(CCU41)w XMC_SCU_IRQCTRL_CCU40_SR2_OR_CCU41_SR2_IRQ23 = (23U << 8U) | 3U, /**< CCU40_SR2 and CCU41_SR2 connected to IRQ23 */#endifi XMC_SCU_IRQCTRL_CCU40_SR3_IRQ24 = (24U << 8U) | 0U, /**< CCU40_SR3 connected to IRQ24 */#if defined(CCU41)i XMC_SCU_IRQCTRL_CCU41_SR3_IRQ24 = (24U << 8U) | 1U, /**< CCU41_SR3 connected to IRQ24 */#endifi XMC_SCU_IRQCTRL_USIC0_SR3_IRQ24 = (24U << 8U) | 2U, /**< USIC0_SR3 connected to IRQ24 */#if defined(CCU41)w XMC_SCU_IRQCTRL_CCU40_SR3_OR_CCU41_SR3_IRQ24 = (24U << 8U) | 3U, /**< CCU40_SR3 and CCU41_SR3 connected to IRQ24 */#endif#if defined(CCU80)i XMC_SCU_IRQCTRL_CCU80_SR0_IRQ25 = (25U << 8U) | 0U, /**< CCU80_SR0 connected to IRQ25 */#endif#if defined(CCU81)i XMC_SCU_IRQCTRL_CCU81_SR0_IRQ25 = (25U << 8U) | 1U, /**< CCU81_SR0 connected to IRQ25 */#endifi XMC_SCU_IRQCTRL_USIC0_SR4_IRQ25 = (25U << 8U) | 2U, /**< USIC0_SR4 connected to IRQ25 */$#if defined(CCU80) && defined(CCU81)w XMC_SCU_IRQCTRL_CCU80_SR0_OR_CCU81_SR0_IRQ25 = (25U << 8U) | 3U, /**< CCU80_SR0 and CCU81_SR0 connected to IRQ25 */#endif#if defined(CCU80)i XMC_SCU_IRQCTRL_CCU80_SR1_IRQ26 = (26U << 8U) | 0U, /**< CCU80_SR1 connected to IRQ26 */#endif#if defined(CCU81)i XMC_SCU_IRQCTRL_CCU81_SR1_IRQ26 = (26U << 8U) | 1U, /**< CCU81_SR1 connected to IRQ26 */#endifi XMC_SCU_IRQCTRL_USIC0_SR5_IRQ26 = (26U << 8U) | 2U, /**< USIC0_SR5 connected to IRQ26 */$#if defined(CCU80) && defined(CCU81)w XMC_SCU_IRQCTRL_CCU80_SR1_OR_CCU81_SR1_IRQ26 = (26U << 8U) | 3U, /**< CCU80_SR1 and CCU81_SR1 connected to IRQ26 */#endif#if defined(POSIF0)j XMC_SCU_IRQCTRL_POSIF0_SR0_IRQ27 = (27U << 8U) | 0U, /**< POSIF0_SR0 connected to IRQ27 */#endif#if defined(POSIF1)j XMC_SCU_IRQCTRL_POSIF1_SR0_IRQ27 = (27U << 8U) | 1U, /**< POSIF1_SR0 connected to IRQ27 */#endifi XMC_SCU_IRQCTRL_CCU40_SR3_IRQ27 = (27U << 8U) | 2U, /**< CCU40_SR3 connected to IRQ27 */&#if defined(POSIF0) && defined(POSIF1)y XMC_SCU_IRQCTRL_POSIF0_SR0_OR_POSIF1_SR0_IRQ27 = (27U << 8U) | 3U, /**< POSIF0_SR0 and POSIF1_SR0 connected to IRQ27 */#endif#if defined(POSIF0)j XMC_SCU_IRQCTRL_POSIF0_SR1_IRQ28 = (28U << 8U) | 0U, /**< POSIF0_SR1 connected to IRQ28 */#endif#if defined(POSIF1)j XMC_SCU_IRQCTRL_POSIF1_SR1_IRQ28 = (28U << 8U) | 1U, /**< POSIF1_SR1 connected to IRQ28 */#endifh XMC_SCU_IRQCTRL_ERU0_SR0_IRQ28 = (28U << 8U) | 2U, /**< ERU0_SR0 connected to IRQ28 */&#if defined(POSIF0) && defined(POSIF1)y XMC_SCU_IRQCTRL_POSIF0_SR1_OR_POSIF1_SR1_IRQ28 = (28U << 8U) | 3U, /**< POSIF0_SR1 and POSIF1_SR1 connected to IRQ28 */#endif#if defined(LEDTS0)j XMC_SCU_IRQCTRL_LEDTS0_SR0_IRQ29 = (29U << 8U) | 0U, /**< LEDTS0_SR0 connected to IRQ29 */#endifi XMC_SCU_IRQCTRL_CCU40_SR1_IRQ29 = (29U << 8U) | 1U, /**< CCU40_SR1 connected to IRQ29 */h XMC_SCU_IRQCTRL_ERU0_SR1_IRQ29 = (29U << 8U) | 2U, /**< ERU0_SR1 connected to IRQ29 */#if defined(LEDTS0)x XMC_SCU_IRQCTRL_LEDTS0_SR0_OR_CCU40_SR1_IRQ29 = (29U << 8U) | 3U, /**< LEDTS0_SR0 and CCU40_SR1 connected to IRQ29 */#endif#if defined(LEDTS1)j XMC_SCU_IRQCTRL_LEDTS1_SR0_IRQ30 = (30U << 8U) | 0U, /**< LEDTS1_SR0 connected to IRQ30 */#endifi XMC_SCU_IRQCTRL_CCU40_SR2_IRQ30 = (30U << 8U) | 1U, /**< CCU40_SR2 connected to IRQ30 */h XMC_SCU_IRQCTRL_ERU0_SR2_IRQ30 = (30U << 8U) | 2U, /**< ERU0_SR2 connected to IRQ30 */#if defined(LEDTS1)x XMC_SCU_IRQCTRL_LEDTS0_SR0_OR_CCU40_SR1_IRQ30 = (30U << 8U) | 3U, /**< LEDTS0_SR0 and CCU40_SR1 connected to IRQ30 */#endif#if defined(BCCU0)i XMC_SCU_IRQCTRL_BCCU0_SR0_IRQ31 = (31U << 8U) | 0U, /**< BCCU0_SR0 connected to IRQ31 */#endifi XMC_SCU_IRQCTRL_CCU40_SR3_IRQ31 = (31U << 8U) | 1U, /**< CCU40_SR3 connected to IRQ31 */h XMC_SCU_IRQCTRL_ERU0_SR3_IRQ31 = (31U << 8U) | 2U, /**< ERU0_SR3 connected to IRQ31 */#if defined(BCCU0)w XMC_SCU_IRQCTRL_BCCU0_SR0_OR_CCU40_SR3_IRQ31 = (31U << 8U) | 3U, /**< BCCU0_SR0 and CCU40_SR3 connected to IRQ31 */#endif} XMC_SCU_IRQCTRL_t;#endif /* XMC_SERIES = XMC14 *//** TODO * */(typedef enum XMC_SCU_POWER_MONITOR_RANGE{W XMC_SCU_POWER_MONITOR_RANGE_2_25V = 0U << SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos, /**< */W XMC_SCU_POWER_MONITOR_RANGE_3_00V = 1U << SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos, /**< */W XMC_SCU_POWER_MONITOR_RANGE_4_40V = 2U << SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos /**< */ } XMC_SCU_POWER_MONITOR_RANGE_t;/** TODO * */(typedef enum XMC_SCU_POWER_MONITOR_DELAY{X XMC_SCU_POWER_MONITOR_DELAY_1US = 0U << SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos, /**< */X XMC_SCU_POWER_MONITOR_DELAY_500NS = 1U << SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos, /**< */X XMC_SCU_POWER_MONITOR_DELAY_250NS = 2U << SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos, /**< */X XMC_SCU_POWER_MONITOR_DELAY_NONE = 3U << SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos /**< */ } XMC_SCU_POWER_MONITOR_DELAY_t;v/********************************************************************************************************************* * DATA STRUCTURESv ********************************************************************************************************************//**^ * Defines a data structure for initializing the data of the supply voltage monitoring block.y * Supply voltage monitoring block consists of 2 detectors namely External voltage detector (VDEL) and External brownoutw * detector (BDE) in the EVR that are used to monitor the VDDP. \a VDEL detector compares the supply voltage against a" * pre-warning threshold voltage.Q * Use type \a XMC_SCU_SUPPLYMONITOR_t for accessing these structure parameters. */$typedef struct XMC_SCU_SUPPLYMONITOR{U uint32_t ext_supply_threshold; /**< External supply range (VDEL Range Select).\n2 \b Range:-
    N
  • 00B sets threshold value to 2.25VM
  • 01B sets threshold value to 3.0VN
  • 10B sets threshold value to 4.4V 0
*/_ uint32_t ext_supply_monitor_speed; /**< Speed of the voltage monitor(VDEL Timing Setting).\n4 \b Range:/
    e
  • 00B sets monitor speed typ 1us - slowest response timeN
  • 01B sets monitor speed typ 500nN
  • 10B sets monitor speed typ 250nl
  • 11B sets monitor speed with no delay - fastest response time.2
*/W bool enable_prewarning_int; /**< Configure pre-warning interrupt generation.\n4 \b Range: .
    N
  • \a true to enable the interrupt.P
  • \a false to disable the interrupt.1
*/Q bool enable_vdrop_int; /**< Configure VDROP interrupt generation.\n4 \b Range: .
    N
  • \a true to enable the interrupt.z
  • \a false to disable the interrupt. 1
*/F bool enable_vclip_int; /**< Configure VCLIP interrupt.\n4 \b Range: .
    N
  • \a true to enable the interrupt.z
  • \a false to disable the interrupt. 1
*/z bool enable_at_init; /**< Whether the monitor has to be enabled (VDEL unit Enable) after initialization.\n4 \b Range: .
    U
  • \a true to enable after initialization.V
  • \a false to enable after initialization.1
*/} XMC_SCU_SUPPLYMONITOR_t;/**U * Defines a data structure for initializing the data of the clock functional block.r * Clock functional block configures clock dividers, peripheral and RTC clock source by configuring corresponding, * bits in \a CLKCR clock control register.P * Use type \a XMC_SCU_CLOCK_CONFIG_t for accessing these structure parameters. */#typedef struct XMC_SCU_CLOCK_CONFIG{#if (UC_SERIES == XMC14)O uint16_t fdiv; /**< Fractional clock divider (FDIV). \b Range: 0 to 1023. */#else| uint8_t fdiv; /**< Fractional clock divider (FDIV). \b Range: 0 to 255. @note XMC1400 series extends the range to 1023 */#endifJ uint8_t idiv; /**< Integer clock divider (IDIV). \b Range: 0 to 255. */,#if (UC_SERIES == XMC14) || defined(DOXYGEN)o XMC_SCU_CLOCK_DCLKSRC_t dclk_src; /**< DCLK clock source selection. @note Only available in XMC1400 series */c XMC_SCU_CLOCK_OSCHP_MODE_t oschp_mode; /**< OSCHP mode. @note Only available in XMC1400 series */c XMC_SCU_CLOCK_OSCLP_MODE_t osclp_mode; /**< OSCLP mode. @note Only available in XMC1400 series */#endifA XMC_SCU_CLOCK_PCLKSRC_t pclk_src; /**< Source of PCLK Clock */A XMC_SCU_CLOCK_RTCCLKSRC_t rtc_src; /**< Source of RTC Clock */} XMC_SCU_CLOCK_CONFIG_t;/**D * Defines the data structure for initializing the deep sleep mode.R * During deep sleep mode peripheral clock is disabled and flash is powered down.T * Use type \a XMC_SCU_CLOCK_DEEP_SLEEP_t for accessing these structure parameters. */'typedef struct XMC_SCU_CLOCK_DEEP_SLEEP{Z bool flash_power_down; /**< Whether the device flash memory has to be powered down= during deep sleep mode.\n] \b Range: Set true to disable flash in deep sleep mode.*/c uint32_t clock_gating_mask; /**< Configures mask value of clocks to be gated during deep sleep.\ni \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t to get the bitmaske of the peripheral clocks. Multiple peripherals can be combined by@ using the \a OR operation.*/} XMC_SCU_CLOCK_DEEP_SLEEP_t;v/********************************************************************************************************************* * API PROTOTYPESv ********************************************************************************************************************/#ifdef __cplusplus extern "C" {#endif/** *< * @param freq_khz Required MCLK frequency value in kHz.\nF * \b Range: XMC11/XMC12/XMC13 Device: 125 to 32000.k * XMC14 Device: 188 to 48000 when DCO1 is clock source for clock control unit.o * 79 to 48000 when OSC_HP is clock source for clock control unit.\n * * @return None * * \parDescription
T * This API configures main clock (MCLK) frequency to requested frequency value.\n\nb * The API configures main clock by setting \a IDIV and \a FDIV bit's of the \a CLKCR register forp * XMC11/XMC12/XMC13/XMC14 Device and with additional \a FDIV bit (FDIV[9:8]) of the \a CLKCR1 register settings * for XMC14 device. * \parRelated APIs:
+ * XMC_SCU_CLOCK_ScaleMCLKFrequency()\n\n\n */7void XMC_SCU_CLOCK_SetMCLKFrequency(uint32_t freq_khz);/** * * @param idiv Divider value.\n% * \b Range: 0 to 255.\n+ * @param fdiv Fractional Divider value.\n= * \b Range: XMC11/XMC12/XMC13 Device: 0 to 255.4 * XMC14 Device: 0 to 1023.\n * * @return None * * \parDescription
` * This API configures main clock (MCLK) frequency by updating user provided divider values.\n\nb * The API configures main clock by setting \a IDIV and \a FDIV bit's of the \a CLKCR register forp * XMC11/XMC12/XMC13/XMC14 Device and with additional \a FDIV bit (FDIV[9:8]) of the \a CLKCR1 register settings * for XMC14 device. * \parRelated APIs:
) * XMC_SCU_CLOCK_SetMCLKFrequency()\n\n\n */Dvoid XMC_SCU_CLOCK_ScaleMCLKFrequency(uint32_t idiv, uint32_t fdiv);/** * * @return None * * \parDescription
7 * Locks access to protected bit fields of the SCU.\n\n[ * The bit protection scheme prevents changing selected register bits by unauthorized code.Z * Bit protection scheme is enabled by writing 000000C3H to \a PASSWD register. By writingZ * this value, the API is setting the \a MODE bit field to bit protection enabled state.\n@ * List of Protected Register Bit Fields are mentioned below. \n * P * P * P * P * P * P * P * *
\a Register \a Bit fields
SCU_CLKCR FDIV, IDIV, PCLKSEL, RTCLKSEL
SCU_CGATSET0 All bits
SCU_CGATCLR0 All bits
SCU_ANAOFFSET ADJL_OFFSET
VADC0_ACCPROT0 All bits
VADC0_ACCPROT1 All bits
 * * \parRelated APIs:
' * XMC_SCU_UnlockProtectedBits() \n\n\n */%void XMC_SCU_LockProtectedBits(void);/** * * @return None * * \parDescription
9 * Unlocks access to protected bit fields of the SCU.\n\n[ * The bit protection scheme prevents changing selected register bits by unauthorized code.t * Bit protection scheme can be temporarily(for 32 MCLK cycles) disabled by writing 000000C0H to \a PASSWD register.l * By writing this value, the API is setting the \a MODE bit field to bit protection disabled state. The APIH * waits for the protection to be disabled after changing the \a MODE.\ns * User can change the values of the protected bit fields within 32 MCLK cycles. After 32 MCLK cycles the lock will * be enabled automatically.@ * List of Protected Register Bit Fields are mentioned below. \n * P * P * P * P * P * P * P * *
\a Register \a Bit fields
SCU_CLKCR FDIV, IDIV, PCLKSEL, RTCLKSEL
SCU_CGATSET0 All bits
SCU_CGATCLR0 All bits
SCU_ANAOFFSET ADJL_OFFSET
VADC0_ACCPROT0 All bits
VADC0_ACCPROT1 All bits
 * * \parRelated APIs:
% * XMC_SCU_LockProtectedBits() \n\n\n */'void XMC_SCU_UnlockProtectedBits(void);/** *^ * @param obj Pointer to data structure consisting voltage monitoring block configuration.\no * \b Range: Use type @ref XMC_SCU_SUPPLYMONITOR_t for detailed description of structure members. * * @return None * * \parDescription
0 * Initializes power supply monitoring unit.\n\nw * Supply voltage monitoring block consist of 2 detectors namely External voltage detector (VDEL) and External brownoutv * detector (BDE) in the EVR that are used to monitor the VDDP. \a VDEL detector compares the supply voltage against a * pre-warning threshold voltage \a ext_supply_threshold. The threshold level is programmable via register \a ANAVDEL.VDEL_SELECT. An interrupt~ * if enabled via \a enable_prewarning_int, will be triggered if a level below this threshold is detected and the flag, VDDPI,‰ * in SRRAW register bit is set. Similarly interrupts can be enabled for the events of VCLIP and prewarning, using the structure members,{ * \a enable_vclip_int and \a enable_prewarning_int. The handlers for these interrupts have to be explicitly defined using/ * the API XMC_SCU_INTERRUPT_SetEventHandler(). * \parRelated APIs:
, * XMC_SCU_INTERRUPT_SetEventHandler()\n\n\n */Cvoid XMC_SCU_SupplyMonitorInit(const XMC_SCU_SUPPLYMONITOR_t *obj);/**P * @param limit Kelvin degree temperature lower compare limit in range [233,388]8 * @return XMC_SCU_STATUS_t status of limit installation * * \parDescription
( * Set lower temperature compare limit. q * A low temperature interrupt (SCU_IRQ1) is triggered if Tchip < limit and the event and interrupt are enabled. J * Alternatively XMC_SCU_LowTemperature() can be used to check the status. * \parRelated APIs:
! * XMC_SCU_LowTemperature()\n\n\n * **/9XMC_SCU_STATUS_t XMC_SCU_SetTempLowLimit(uint32_t limit);/**Q * @param limit Kelvin degree temperature higher compare limit in range [233,388]8 * @return XMC_SCU_STATUS_t status of limit installation * * \parDescription
) * Set higher temperature compare limit. r * A high temperature interrupt (SCU_IRQ1) is triggered if Tchip > limit and the event and interrupt are enabled. K * Alternatively XMC_SCU_HighTemperature() can be used to check the status. * \parRelated APIs:
" * XMC_SCU_HighTemperature()\n\n\n * **/:XMC_SCU_STATUS_t XMC_SCU_SetTempHighLimit(uint32_t limit);/** *F * @param lower_temp Lower threshold value for the die temperature.\n8 * \b Range: 0 to 65535(16 bit unsigned value).F * @param upper_temp Upper threshold value for the die temperature.\n8 * \b Range: 0 to 65535(16 bit unsigned value). * * @return None * * \parDescription
n * Configures upper and lower thresholds of die temperature as raw digital values into temperature sensor.\n\np * The API configures \a ANATSEIH and \a ANATSEIL registers for upper and lower die temperature threshold limits * respectively.\n. * It is recommended to use following steps:\nh * - Call \a XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.\nh * - Call \a XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values.\nU * - Finally call \a XMC_SCU_StartTempMeasurement to start temperature measurement.\n * * \parRelated APIs:
G * XMC_SCU_StopTempMeasurement(), XMC_SCU_StartTempMeasurement() \n\n\n */Tvoid XMC_SCU_SetRawTempLimits(const uint32_t lower_temp, const uint32_t upper_temp);t// /* API to program temperature limits in centigrade into temperature sensor unit */ // need to implement in futureT// void XMC_SCU_SetTempLimits(const uint32_t lower_temp, const uint32_t upper_temp);/** *O * @return XMC_SCU_STATUS_t Status of starting the temperature measurement.\nV * \b Range: Use type @ref XMC_SCU_STATUS_t to identify the result.\nV * XMC_SCU_STATUS_OK- Temperature measurement started successfully.\n4 * Always returns the above status. * * \parDescription
L * Starts die temperature measurement using internal temperature sensor.\n\nV * The API, enables die temperature measurement and waits for about 10000 cycles untilX * temperature measurement result is available on \a SCU_ANALOG->ANATSEMON bit fields.\n. * It is recommended to use following steps:\nh * - Call \a XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.\nx * - Call \a XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values if it is needed.\nM * - Call \a XMC_SCU_StartTempMeasurement to start temperature measurement.\nF * - Read die temperature value using \a XMC_SCU_GetTemperature API.\n * \parRelated APIs:
] * XMC_SCU_StopTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_GetTemperature() \n\n\n */(void XMC_SCU_StartTempMeasurement(void);/** * @return None * * \parDescription
- * Stops the die temperature measurement.\n\nX * Die temperature measurement is stopped by disabling the sensor using \a TSE_EN bit of * \a ANATSECTRL register. * \parRelated APIs:
^ * XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_GetTemperature() \n\n\n */'void XMC_SCU_StopTempMeasurement(void);/** *c * @return bool Result of checking whether the die temperature is more than the upper threshold.\nd * \b Range: \a false if temperature is below the upper threshold. \a true if temperatureR * has exceeded the upper threshold configured in \a ANATSEIH register. * * \parDescription
G * Check if the temperature has exceeded the upper threshold value.\n\nk * The API checks for \a TSE_HIGH bit (TSE Compare High Temperature Event Status bit) of \a SRRAW register.^ * The bit will be set when the \a TSE_MON value in \a ANATSEMON register exceeds the value of+ * \a TSE_IH value in \a ANATSEIH register. * \parRelated APIs:
x * XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_GetTemperature(), XMC_SCU_LowTemperature() \n\n\n */#bool XMC_SCU_HighTemperature(void);/** *c * @return bool Result of checking whether the die temperature is less than the lower threshold.\nj * \b Range: \a false if temperature is higher than the lower threshold. \a true if temperatureW * has dropped below the lower threshold configured in \a ANATSEIL register. * * \parDescription
L * Check if the temperature has dropped below the lower threshold value.\n\ni * The API checks for \a TSE_LOW bit (TSE Compare Low Temperature Event Status bit) of \a SRRAW register.b * The bit will be set when the \a TSE_MON value in \a ANATSEMON register drops below the value of+ * \a TSE_IL value in \a ANATSEIL register. * \parRelated APIs:
y * XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_GetTemperature(), XMC_SCU_HighTemperature() \n\n\n */"bool XMC_SCU_LowTemperature(void);/**G * @return uint32_t Raw die temperature value. \b Range: 16 bit value. * * \parDescription
. * Provides the raw die temperature value.\n\nY * The API reads temperature measurement result from \a SCU_ANALOG->ANATSEMON bit fields. * \parRelated APIs:
( * XMC_SCU_StartTempMeasurement() \n\n\n */&uint32_t XMC_SCU_GetTemperature(void);/**M * @return uint32_t Calculate die temperature value. \b Range: 16 bit value. * * \parDescription
? * Calculates the die temperature value using ROM function.\n\n * \parRelated APIs:
( * XMC_SCU_StartTempMeasurement() \n\n\n */'uint32_t XMC_SCU_CalcTemperature(void);/** * * @param None *$ * @return true DTS Measurement Done) * @return false DTS Measurement not Done * * \parDescription
J * This functions checks the status of the DTS Measurement completion.\n\n * \parRelated APIs:
( * XMC_SCU_StartTempMeasurement() \n\n\n */8__STATIC_INLINE bool XMC_SCU_IsTempMeasurementDone(void){K return ((SCU_INTERRUPT->SRRAW & SCU_INTERRUPT_SRRAW_TSE_DONE_Msk) != 0U);}/** * @return None * * \parDescription
# * Trigger device master reset.\n\nT * The API triggers master reset by setting the \a MRSTEN bit of \a RSTCON register.l * It also internally triggers system reset. Almost all the logics of the device are affected by this reset. * \parRelated APIs:
, * XMC_SCU_RESET_EnableResetRequest() \n\n\n */:__STATIC_INLINE void XMC_SCU_RESET_AssertMasterReset(void){3 SCU_RESET->RSTCON |= SCU_RESET_RSTCON_MRSTEN_Msk;}/** *> * @param request Reset source to trigger the device reset.\nb * \b Range: Use type @ref XMC_SCU_SYSTEM_RESET_REQUEST_t to identify the reset source.\nj * XMC_SCU_RESET_REQUEST_FLASH_ECC_ERROR- Reset when flash memory double bit error is detected.\nU * XMC_SCU_RESET_REQUEST_CLOCK_LOSS- Reset when loss of clock is detected.\n` * XMC_SCU_RESET_REQUEST_SRAM_PARITY_ERROR- Reset when SRAM parity error is detected.\nk * XMC_SCU_RESET_REQUEST_USIC_SRAM_PARITY_ERROR- Reset when USIC0 SRAM parity error is detected.\n * * @return None * * \parDescription
D * Configures trigger for system reset from the selected source.\n\nN * The API configures the reset source specific bit in the \a RSTCON register.L * Multiple reset sources can be combined using \a OR operation. By enablingR * the reset using this API will not trigger the reset. The reset will happen when+ * the configured source event is detected. * \parRelated APIs:
+ * XMC_SCU_RESET_AssertMasterReset() \n\n\n */G__STATIC_INLINE void XMC_SCU_RESET_EnableResetRequest(uint32_t request){ SCU_RESET->RSTCON |= request;}/** *> * @return uint32_t Fast peripheral clock frequency in Hertz. * * \parDescription
r * Provides the clock frequency of peripherals on the peripheral bus that are using a shared functional clock.\n\n^ * The value is derived using the bitfield \a PCLKSEL from \a CLKCR register. Peripheral clockK * can have 2 times the frequency of system clock if the \a PCLKSEL is set. * \parRelated APIs:
6 * XMC_SCU_CLOCK_SetFastPeripheralClockSource() \n\n\n */=uint32_t XMC_SCU_CLOCK_GetFastPeripheralClockFrequency(void);/** *1 * @param source Fast peripheral clock source.\n[ * \b Range: Use type @ref XMC_SCU_CLOCK_PCLKSRC_t to identify the clock source.\nK * XMC_SCU_CLOCK_PCLKSRC_MCLK- Use MCLK as the peripheral clock.\nc * XMC_SCU_CLOCK_PCLKSRC_DOUBLE_MCLK- peripheral clock will be 2 times the MCLK frequency. * * @return None * * \parDescription
2 * Configures the source of peripheral clock. \n\nR * The peripheral clock can be either same as MCLK or twice the frequency of MCLK. * \parRelated APIs:
9 * XMC_SCU_CLOCK_GetFastPeripheralClockFrequency() \n\n\n */Vvoid XMC_SCU_CLOCK_SetFastPeripheralClockSource(const XMC_SCU_CLOCK_PCLKSRC_t source);/** *P * @param temperature measured temperature using the on-chip temperature sensor * * @return None * * \parDescription
V * DCO1 clock frequency can be calibrated during runtime to achieve a better accuracy.A * This function start the DCO1 calibration based on temperature. *  */Ivoid XMC_SCU_CLOCK_CalibrateOscillatorOnTemperature(int32_t temperature);,#if (UC_SERIES == XMC14) || defined(DOXYGEN)/** *` * @param sync_clk Clock source selected as external reference. @ref XMC_SCU_CLOCK_SYNC_CLKSRC_tE * @param prescaler integer(\f$\frac{300 \times f_{OSC}[MHz]}{48}\f$)M * @param syn_preload integer(\f$\frac{48 \times prescaler}{f_{OSC}[MHz]}\f$) * * @return None *  * \parDescription
V * DCO1 clock frequency can be calibrated during runtime to achieve a better accuracy.Z * This function starts the automatic DCO1 calibration based on the selected clock source.* * @note Only available for XMC1400 series */void XMC_SCU_CLOCK_EnableDCO1ExtRefCalibration(XMC_SCU_CLOCK_SYNC_CLKSRC_t sync_clk, uint32_t prescaler, uint32_t syn_preload);/** * * @param None * * @return None *  * \parDescription
Y * This function stops the automatic DCO1 calibration based on the selected clock source.* * @note Only available for XMC1400 series */6void XMC_SCU_CLOCK_DisableDCO1ExtRefCalibration(void);/** * * @param None *C * @return true DCO1 is synchronized to the selected XTAL frequency7 * @return false Actual DCO1 frequency is out of target *  * \parDescription
: * This functions checks the status of the synchronisation* * @note Only available for XMC1400 series */6bool XMC_SCU_CLOCK_IsDCO1ExtRefCalibrationReady(void);/** * * @param None * * @return None *  * \parDescription
; * This function enables the watchdog on the DCO1 frequency* * @note Only available for XMC1400 series */6void XMC_SCU_CLOCK_EnableDCO1OscillatorWatchdog(void);/** * * @param None * * @return None *  * \parDescription
< * This function disables the watchdog on the DCO1 frequency* * @note Only available for XMC1400 series */7void XMC_SCU_CLOCK_DisableDCO1OscillatorWatchdog(void);/** * * @param None * * @return None *  * \parDescription
H * This function clears the status of the watchdog on the DCO1 frequency* * @note Only available for XMC1400 series */;void XMC_SCU_CLOCK_ClearDCO1OscillatorWatchdogStatus(void);/* * * @param None *+ * @return true The OSC frequency is usableR * @return false The OSC frequency is not usable. Frequency is too high or too low *  * \parDescription
N * This function checks if the DCO1 frequency is in the limits of the watchdog* * @note Only available for XMC1400 series */4bool XMC_SCU_CLOCK_IsDCO1ClockFrequencyUsable(void);/**J * This function selects service request source for a NVIC interrupt node.? * The XMC1400 series has up to 54 peripheral service requests.E * The Cortex M0 however has 32 interrupts available for peripherals.e * This function allows you to select which 32 peripheral requests of the 54 the CPU should react on. *. * @param irq_number Interrupt number, 0 to 31G * @param source Peripheral service request. See @ref XMC_SCU_IRQCTRL_t ** * @note Only available for XMC1400 series */Ovoid XMC_SCU_SetInterruptControl(uint8_t irq_number, XMC_SCU_IRQCTRL_t source);/**1 * This function enables the Prefetch Unit (PFU).W * The purpose of the Prefetch unit is to reduce the Flash latency gap at higher systemA * frequencies to increase the instruction per cycle performance. ** * @note Only available for XMC1400 series */5__STATIC_INLINE void XMC_SCU_EnablePrefetchUnit(void){6 SCU_GENERAL->PFUCR &= ~SCU_GENERAL_PFUCR_PFUBYP_Msk;}/**2 * This function disables the Prefetch Unit (PFU).W * The purpose of the Prefetch unit is to reduce the Flash latency gap at higher systemA * frequencies to increase the instruction per cycle performance. ** * @note Only available for XMC1400 series */6__STATIC_INLINE void XMC_SCU_DisablePrefetchUnit(void){5 SCU_GENERAL->PFUCR |= SCU_GENERAL_PFUCR_PFUBYP_Msk;}#endif/** TODO* * Note: Brown Out Trap need to be enabled */z__STATIC_INLINE void XMC_SCU_POWER_EnableMonitor(XMC_SCU_POWER_MONITOR_RANGE_t range, XMC_SCU_POWER_MONITOR_DELAY_t delay){9 SCU_ANALOG->ANAVDEL = SCU_ANALOG_ANAVDEL_VDEL_EN_Msk | * (uint32_t)range | ( (uint32_t)delay;}/** TODO * */7__STATIC_INLINE void XMC_SCU_POWER_DisableMonitor(void){: SCU_ANALOG->ANAVDEL &= ~SCU_ANALOG_ANAVDEL_VDEL_EN_Msk; }#ifdef __cplusplus}#endif/** * @} *//** * @} */#endif /* UC_FAMILY == XMC1 */#endif /* XMC1_SCU_H */ xmc_ccu4.h< /** * @file xmc_ccu4.h * @date 2016-03-09 * * @condv *********************************************************************************************************************1 * XMClib v2.1.6 - XMC Peripheral Driver Library  *4 * Copyright (c) 2015-2016, Infineon Technologies AG/ * All rights reserved. / * s * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the # * following conditions are met: P * t * Redistributions of source code must retain the above copyright notice, this list of conditions and the following & * disclaimer.  * w * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following p * disclaimer in the documentation and/or other materials provided with the distribution.  * q * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote | * products derived from this software without specific prior written permission. P * v * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, v * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE w * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, t * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR u * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, w * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE y * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. P * w * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with i * Infineon Technologies AG dave@infineon.com). v ********************************************************************************************************************* * * Change History * -------------- * * 2015-02-20: * - Initial
# * - Documentation updates
 * * 2015-06-20:L * - Removed version macros and declaration of GetDriverVersion API
 * * 2015-07-22:b * - XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent() is updated to support XMC14 device.
 * * 2015-08-17:T * - XMC_CCU4_SLICE_PRESCALER_t enum is added to set the prescaler divider.
l * - XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t enum item names are updated according to the guidelines.
Z * - XMC_CCU4_EnableShadowTransfer() API is made as inline, to improve the speed.
 * * 2015-09-29:w * - In XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_t, two more enum items are added to support external count direction * settings. * * 2015-10-07:5 * - XMC_CCU4_SLICE_GetEvent() is made as inline.i * - XMC_CCU4_SLICE_MULTI_IRQ_ID_t is added to support the XMC_CCU4_SLICE_EnableMultipleEvents() and 5 * XMC_CCU4_SLICE_DisableMultipleEvents() APIs.. * - DOC updates for the newly added APIs. * * 2016-03-09:. * - Optimization of write only registers * @endcond */#ifndef XMC_CCU4_H#define XMC_CCU4_H v/********************************************************************************************************************* * HEADER FILESv ********************************************************************************************************************/#include "xmc_common.h"#if defined(CCU40)#if UC_FAMILY == XMC1 #include "xmc1_ccu4_map.h"#endif#if UC_FAMILY == XMC4 #include "xmc4_ccu4_map.h"#endif/**, * @addtogroup XMClib XMC Peripheral Library * @{ */ /** * @addtogroup CCU4_ * @brief Capture Compare Unit 4 (CCU4) low level driver for XMC family of microcontrollers
 *d * The CCU4 peripheral is a major component for systems that need general purpose timers for signal u * monitoring/conditioning and Pulse Width Modulation (PWM) signal generation. Power electronic control systems like x * switched mode power supplies or interruptible power supplies, can easily be implemented with the functions inside the * CCU4 peripheral.\nv * Each CCU4 module is comprised of four identical 16 bit Capture/Compare Timer slices, CC4y (where y = [0..4]). Each ; * timer slice can work in compare mode or in capture mode. *N * APIs provided in this file cover the following functional blocks of CCU4:\ni * -- Timer configuration, Capture configuration, Function/Event configuration, Interrupt configuration\n * \par Note:5 * 1. SLICE (APIs prefixed with e.g. XMC_CCU4_SLICE_)< * 2. Module (APIs are not having any prefix e.g. XMC_CCU4_) ** * \par Timer(Compare mode) configuration:w * This section of the LLD provides the configuration structure XMC_CCU4_SLICE_COMPARE_CONFIG_t and the initialization ) * function XMC_CCU4_SLICE_CompareInit(). * * It can be used to:Y * -# Start and Stop the timer. (XMC_CCU4_SLICE_StartTimer(), XMC_CCU4_SLICE_StopTimer())p * -# Update the period, compare, Dither, Prescaler and Passive values. (XMC_CCU4_SLICE_SetTimerPeriodMatch(), t * XMC_CCU4_SLICE_SetTimerCompareMatch(), XMC_CCU4_SLICE_SetPrescaler(), XMC_CCU4_SLICE_SetDitherCompareValue(), ' * XMC_CCU4_SLICE_SetPassiveLevel())_ * -# Enable the slices to support multichannel mode. (XMC_CCU4_SLICE_EnableMultiChannelMode()) *  * \par Capture configuration:v * This section of the LLD provides the configuration structure XMC_CCU4_SLICE_CAPTURE_CONFIG_t and the initialization) * function XMC_CCU4_SLICE_CaptureInit(). * * It can be used to:m * -# Configure the capture functionality. (XMC_CCU4_SLICE_Capture0Config(), XMC_CCU4_SLICE_Capture1Config())` * -# Read the captured values along with the status, which indicate the value is latest or not.0 * (XMC_CCU4_SLICE_GetCaptureRegisterValue()) * % * \par Function/Event configuration:` * This section of the LLD provides the configuration structure XMC_CCU4_SLICE_EVENT_CONFIG_t.\n *  * It can be used to:b * -# Enable and Disable the events. (XMC_CCU4_SLICE_EnableEvent(), XMC_CCU4_SLICE_DisableEvent())z * -# Configure to start and stop the timer on external events.(XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_StopConfig())c * -# Modulation, external load and Gating of the timer output.(XMC_CCU4_SLICE_ModulationConfig(), ? * XMC_CCU4_SLICE_LoadConfig(), XMC_CCU4_SLICE_GateConfig())n * -# Control the count direction of the timer based on the external event. (XMC_CCU4_SLICE_DirectionConfig())> * -# Count the external events.(XMC_CCU4_SLICE_CountConfig())x * -# External Trap. Which can be used as protective feature.(XMC_CCU4_SLICE_EnableTrap(), XMC_CCU4_SLICE_DisableTrap()," * XMC_CCU4_SLICE_TrapConfig()) * * \par Interrupt configuration:‚ * This section of the LLD provides the function to configure the interrupt node to each event (XMC_CCU4_SLICE_SetInterruptNode()) * @{ */ v/********************************************************************************************************************* * MACROSv ********************************************************************************************************************/:/* Macro to check if the interrupt enum passed is valid */3#define XMC_CCU4_SLICE_CHECK_INTERRUPT(interrupt) \E ((interrupt == XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH) || \E (interrupt == XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH) || \@ (interrupt == XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP) || \@ (interrupt == XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN)|| \E (interrupt == XMC_CCU4_SLICE_IRQ_ID_EVENT0) || \E (interrupt == XMC_CCU4_SLICE_IRQ_ID_EVENT1) || \E (interrupt == XMC_CCU4_SLICE_IRQ_ID_EVENT2) || \/ (interrupt == XMC_CCU4_SLICE_IRQ_ID_TRAP))v/********************************************************************************************************************* * ENUMSv ********************************************************************************************************************//**) * Typedef for CCU4 Global data structure */.typedef CCU4_GLOBAL_TypeDef XMC_CCU4_MODULE_t;/**( * Typedef for CCU4 Slice data structure */*typedef CCU4_CC4_TypeDef XMC_CCU4_SLICE_t;/** * Return Value of an API */ typedef enum XMC_CCU4_STATUS{; XMC_CCU4_STATUS_OK = 0U, /**< API fulfils request */E XMC_CCU4_STATUS_ERROR , /**< API cannot fulfil the request */L XMC_CCU4_STATUS_RUNNING , /**< The timer slice is currently running */I XMC_CCU4_STATUS_IDLE /**< The timer slice is currently idle */} XMC_CCU4_STATUS_t;/** * CCU4 module clock */ typedef enum XMC_CCU4_CLOCK{F XMC_CCU4_CLOCK_SCU = 0U, /**< Select the fCCU as the clock */: XMC_CCU4_CLOCK_EXTERNAL_A , /**< External clock-A */: XMC_CCU4_CLOCK_EXTERNAL_B , /**< External clock-B */: XMC_CCU4_CLOCK_EXTERNAL_C /**< External clock-C */} XMC_CCU4_CLOCK_t;/**: * CCU4 set the shadow transfer type for multichannel mode */3typedef enum XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER{v XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE0 = (uint32_t)0x4000000, /**< Shadow transfer through software g only for slice 0*/v XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE0 = (uint32_t)0x4000400, /**< Shadow transfer through software p and hardware for slice 0 */v XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE1 = (uint32_t)0x8000000, /**< Shadow transfer through software g only for slice 1*/v XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE1 = (uint32_t)0x8000800, /**< Shadow transfer through software p and hardware for slice 1 */v XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE2 = (uint32_t)0x10000000, /**< Shadow transfer through softwarei only for slice 2 */v XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE2 = (uint32_t)0x10001000, /**< Shadow transfer through softwareq and hardware for slice 2 */v XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE3 = (uint32_t)0x20000000, /**< Shadow transfer through softwareh only for slice 3*/v XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE3 = (uint32_t)0x20002000 /**< Shadow transfer through softwareq and hardware for slice 3 */+} XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_t;/**# * Operational modes of CCU4 slice */ typedef enum XMC_CCU4_SLICE_MODE{Q XMC_CCU4_SLICE_MODE_COMPARE = 0U, /**< slice(CC4y) operates in Compare Mode */Q XMC_CCU4_SLICE_MODE_CAPTURE /**< slice(CC4y) operates in Capture Mode */} XMC_CCU4_SLICE_MODE_t;/**& * Timer counting modes for the slice */ ,typedef enum XMC_CCU4_SLICE_TIMER_COUNT_MODE{E XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA = 0U, /**< Edge Aligned Mode */G XMC_CCU4_SLICE_TIMER_COUNT_MODE_CA /**< Center Aligned Mode */$} XMC_CCU4_SLICE_TIMER_COUNT_MODE_t;/**' * Timer repetition mode for the slice */ -typedef enum XMC_CCU4_SLICE_TIMER_REPEAT_MODE{f XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT = 0U, /**< Repetitive mode: continuous mode of operation */e XMC_CCU4_SLICE_TIMER_REPEAT_MODE_SINGLE /**< Single shot mode: Once a Period match/One matchX occurs timer goes to idle state */%} XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t;/**. * Timer counting direction for the CCU4 slice */ +typedef enum XMC_CCU4_SLICE_TIMER_COUNT_DIR{? XMC_CCU4_SLICE_TIMER_COUNT_DIR_UP = 0U, /**< Counting up */A XMC_CCU4_SLICE_TIMER_COUNT_DIR_DOWN /**< Counting down */#} XMC_CCU4_SLICE_TIMER_COUNT_DIR_t;/** * Capture mode register sets */ 'typedef enum XMC_CCU4_SLICE_CAP_REG_SET{[ XMC_CCU4_SLICE_CAP_REG_SET_LOW = 0U, /**< Capture register-0, Capture register-1 used */[ XMC_CCU4_SLICE_CAP_REG_SET_HIGH /**< Capture register-2, Capture register-3 used */} XMC_CCU4_SLICE_CAP_REG_SET_t;/** * Prescaler mode */ *typedef enum XMC_CCU4_SLICE_PRESCALER_MODE{S XMC_CCU4_SLICE_PRESCALER_MODE_NORMAL = 0U, /**< Fixed division of module clock */F XMC_CCU4_SLICE_PRESCALER_MODE_FLOAT /**< Floating divider. */"} XMC_CCU4_SLICE_PRESCALER_MODE_t;/** * Timer output passive level */ 0typedef enum XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL{L XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW = 0U, /**< Passive level = Low */M XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH /**< Passive level = High */(} XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t;/** * Timer clock Divider */%typedef enum XMC_CCU4_SLICE_PRESCALER{? XMC_CCU4_SLICE_PRESCALER_1 = 0U, /**< Slice Clock = fccu4 */A XMC_CCU4_SLICE_PRESCALER_2 , /**< Slice Clock = fccu4/2 */A XMC_CCU4_SLICE_PRESCALER_4 , /**< Slice Clock = fccu4/4 */A XMC_CCU4_SLICE_PRESCALER_8 , /**< Slice Clock = fccu4/8 */B XMC_CCU4_SLICE_PRESCALER_16 , /**< Slice Clock = fccu4/16 */B XMC_CCU4_SLICE_PRESCALER_32 , /**< Slice Clock = fccu4/32 */B XMC_CCU4_SLICE_PRESCALER_64 , /**< Slice Clock = fccu4/64 */C XMC_CCU4_SLICE_PRESCALER_128 , /**< Slice Clock = fccu4/128 */C XMC_CCU4_SLICE_PRESCALER_256 , /**< Slice Clock = fccu4/256 */C XMC_CCU4_SLICE_PRESCALER_512 , /**< Slice Clock = fccu4/512 */D XMC_CCU4_SLICE_PRESCALER_1024 , /**< Slice Clock = fccu4/1024 */D XMC_CCU4_SLICE_PRESCALER_2048 , /**< Slice Clock = fccu4/2048 */D XMC_CCU4_SLICE_PRESCALER_4096 , /**< Slice Clock = fccu4/4096 */D XMC_CCU4_SLICE_PRESCALER_8192 , /**< Slice Clock = fccu4/8192 */E XMC_CCU4_SLICE_PRESCALER_16384 , /**< Slice Clock = fccu4/16384 */E XMC_CCU4_SLICE_PRESCALER_32768 /**< Slice Clock = fccu4/32768 */} XMC_CCU4_SLICE_PRESCALER_t;/** * External Function list */ $typedef enum XMC_CCU4_SLICE_FUNCTION{F XMC_CCU4_SLICE_FUNCTION_START = 0U, /**< Start function */E XMC_CCU4_SLICE_FUNCTION_STOP , /**< Stop function */p XMC_CCU4_SLICE_FUNCTION_CAPTURE_EVENT0 , /**< Capture Event-0 function, CCycapt0 signal is used for eventB generation */p XMC_CCU4_SLICE_FUNCTION_CAPTURE_EVENT1 , /**< Capture Event-1 function, CCycapt1 signal is used for eventB generation */G XMC_CCU4_SLICE_FUNCTION_GATING , /**< Gating function */J XMC_CCU4_SLICE_FUNCTION_DIRECTION , /**< Direction function */E XMC_CCU4_SLICE_FUNCTION_LOAD , /**< Load function */I XMC_CCU4_SLICE_FUNCTION_COUNT , /**< Counting function */I XMC_CCU4_SLICE_FUNCTION_OVERRIDE , /**< Override function */K XMC_CCU4_SLICE_FUNCTION_MODULATION , /**< Modulation function */E XMC_CCU4_SLICE_FUNCTION_TRAP /**< Trap function */} XMC_CCU4_SLICE_FUNCTION_t;/** * External Event list */ !typedef enum XMC_CCU4_SLICE_EVENT{/ XMC_CCU4_SLICE_EVENT_NONE = 0U, /**< None */2 XMC_CCU4_SLICE_EVENT_0 , /**< Event-0 */2 XMC_CCU4_SLICE_EVENT_1 , /**< Event-1 */2 XMC_CCU4_SLICE_EVENT_2 /**< Event-2 */} XMC_CCU4_SLICE_EVENT_t;/**7 * External Event trigger criteria - Edge sensitivity */ 2typedef enum XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY{G XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE = 0U, /**< None */y XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE , /**< Rising Edge of the input signal generates event trigger*/p XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE , /**< Falling Edge of the input signal generates eventJ trigger */v XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE /**< Both Rising and Falling edges cause an event trigger*/*} XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_t;/**8 * External Event trigger criteria - Level sensitivity */ 3typedef enum XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY{x XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH = 0U, /**< Level sensitive functions react to a high signal level*/w XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW = 1U, /**< Level sensitive functions react to a low signal level*/F /* Below enum items can be utilised specific to the functionality */„ XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_LOW = 0U, /**< Timer counts up, during Low state of the control signal */ ˆ XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_HIGH = 1U /**< Timer counts up, during High state of the control signal */ +} XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_t;/**s * Low pass filter Configuration. The External Event input should be stable for a selected number of clock cycles. */ (typedef enum XMC_CCU4_SLICE_EVENT_FILTER{H XMC_CCU4_SLICE_EVENT_FILTER_DISABLED = 0U, /**< No Low Pass Filter */D XMC_CCU4_SLICE_EVENT_FILTER_3_CYCLES , /**< 3 clock cycles */D XMC_CCU4_SLICE_EVENT_FILTER_5_CYCLES , /**< 5 clock cycles */D XMC_CCU4_SLICE_EVENT_FILTER_7_CYCLES /**< 7 clock cycles */ } XMC_CCU4_SLICE_EVENT_FILTER_t;/**b * External Event Input list. This list depicts the possible input connections to the CCU4 slice.. * Interconnects are specific to each device. */ 'typedef uint8_t XMC_CCU4_SLICE_INPUT_t;/**O * Actions that can be performed upon detection of an external Timer STOP event */ $typedef enum XMC_CCU4_SLICE_END_MODE{i XMC_CCU4_SLICE_END_MODE_TIMER_STOP = 0U, /**< Stops the timer, without clearing TIMER register */j XMC_CCU4_SLICE_END_MODE_TIMER_CLEAR , /**< Without stopping timer, clears the TIMER register */f XMC_CCU4_SLICE_END_MODE_TIMER_STOP_CLEAR /**< Stops the timer and clears the TIMER register */} XMC_CCU4_SLICE_END_MODE_t;/**Q * Actions that can be performed upon detection of an external Timer START event */ &typedef enum XMC_CCU4_SLICE_START_MODE{t XMC_CCU4_SLICE_START_MODE_TIMER_START = 0U, /**< Start the timer from the current count of TIMER register */i XMC_CCU4_SLICE_START_MODE_TIMER_START_CLEAR /**< Clears the TIMER register and start the timer */} XMC_CCU4_SLICE_START_MODE_t;/**& * Modulation of timer output signals */ +typedef enum XMC_CCU4_SLICE_MODULATION_MODE{U XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_ST_OUT = 0U, /**< Clear ST and OUT signals */V XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_OUT /**< Clear only the OUT signal */#} XMC_CCU4_SLICE_MODULATION_MODE_t;/** * Trap exit mode */ *typedef enum XMC_CCU4_SLICE_TRAP_EXIT_MODE{r XMC_CCU4_SLICE_TRAP_EXIT_MODE_AUTOMATIC = 0U, /**< Clear trap state as soon as the trap signal is de-asserted */` XMC_CCU4_SLICE_TRAP_EXIT_MODE_SW /**< Clear only when acknowledged by software */"} XMC_CCU4_SLICE_TRAP_EXIT_MODE_t;/** * Timer clear on capture */ ,typedef enum XMC_CCU4_SLICE_TIMER_CLEAR_MODE{c XMC_CCU4_SLICE_TIMER_CLEAR_MODE_NEVER = 0U, /**< Never clear the timer on any capture event */u XMC_CCU4_SLICE_TIMER_CLEAR_MODE_CAP_HIGH , /**< Clear only when timer value has been captured in C3V and C2V */u XMC_CCU4_SLICE_TIMER_CLEAR_MODE_CAP_LOW , /**< Clear only when timer value has been captured in C1V and C0V */s XMC_CCU4_SLICE_TIMER_CLEAR_MODE_ALWAYS /**< Always clear the timer upon detection of any capture event */$} XMC_CCU4_SLICE_TIMER_CLEAR_MODE_t;/**? * Multi Channel Shadow transfer request configuration options */ 'typedef enum XMC_CCU4_SLICE_MCMS_ACTION{u XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR = 0U, /**< Transfer Compare and Period Shadow register values tom the actual registers upon MCS xfer request */u XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP = 1U, /**< Transfer Compare, Period and Prescaler Compare Shadowv register values to the actual registers upon MCS xfer J request */w XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT = 3U /**< Transfer Compare, Period ,Prescaler Compare and Dither u Compare register values to the actual registers upon S MCS xfer request */} XMC_CCU4_SLICE_MCMS_ACTION_t;/** * Available Interrupt Event Ids */ "typedef enum XMC_CCU4_SLICE_IRQ_ID{R XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH = 0U , /**< Period match counting up */a XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH = 1U , /**< Period match -> One match counting down */S XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP = 2U , /**< Compare match counting up */U XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN = 3U , /**< Compare match counting down */L XMC_CCU4_SLICE_IRQ_ID_EVENT0 = 8U , /**< Event-0 occurrence */L XMC_CCU4_SLICE_IRQ_ID_EVENT1 = 9U , /**< Event-1 occurrence */L XMC_CCU4_SLICE_IRQ_ID_EVENT2 = 10U, /**< Event-2 occurrence */I XMC_CCU4_SLICE_IRQ_ID_TRAP = 11U /**< Trap occurrence */} XMC_CCU4_SLICE_IRQ_ID_t;/**L * Available Interrupt Event Ids, which is added to support multi event APIs */(typedef enum XMC_CCU4_SLICE_MULTI_IRQ_ID{[ XMC_CCU4_SLICE_MULTI_IRQ_ID_PERIOD_MATCH = 0x1U, /**< Period match counting up */j XMC_CCU4_SLICE_MULTI_IRQ_ID_ONE_MATCH = 0x2U, /**< Period match -> One match counting down */\ XMC_CCU4_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_UP = 0x4U, /**< Compare match counting up */^ XMC_CCU4_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_DOWN = 0x8U, /**< Compare match counting down */U XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT0 = 0x100U, /**< Event-0 occurrence */U XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT1 = 0x200U, /**< Event-1 occurrence */U XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT2 = 0x400U, /**< Event-2 occurrence */ } XMC_CCU4_SLICE_MULTI_IRQ_ID_t;/**s * Service Request Lines for CCU4. Event are mapped to these SR lines and these are used to generate the interrupt. */ !typedef enum XMC_CCU4_SLICE_SR_ID{J XMC_CCU4_SLICE_SR_ID_0 = 0U, /**< Service Request Line-0 selected */J XMC_CCU4_SLICE_SR_ID_1 , /**< Service Request Line-1 selected */J XMC_CCU4_SLICE_SR_ID_2 , /**< Service Request Line-2 selected */J XMC_CCU4_SLICE_SR_ID_3 /**< Service Request Line-3 selected */} XMC_CCU4_SLICE_SR_ID_t;/**" * Slice shadow transfer options. */%typedef enum XMC_CCU4_SHADOW_TRANSFER{t XMC_CCU4_SHADOW_TRANSFER_SLICE_0 = CCU4_GCSS_S0SE_Msk, /**< Transfer Period, Compare and Passive Level x shadow register values to actual registers forT SLICE-0 */w XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_0 = CCU4_GCSS_S0DSE_Msk, /**< Transfer Dither compare shadow register valuek to actual register for SLICE-0 */u XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_0 = CCU4_GCSS_S0PSE_Msk, /**< Transfer Prescaler shadow register value toh actual register for SLICE-0 */t XMC_CCU4_SHADOW_TRANSFER_SLICE_1 = CCU4_GCSS_S1SE_Msk, /**< Transfer Period, Compare and Passive Level x shadow register values to actual registers forT SLICE-1 */w XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_1 = CCU4_GCSS_S1DSE_Msk, /**< Transfer Dither compare shadow register valuel to actual registers for SLICE-1 */u XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_1 = CCU4_GCSS_S1PSE_Msk, /**< Transfer Prescaler shadow register value toh actual register for SLICE-1 */t XMC_CCU4_SHADOW_TRANSFER_SLICE_2 = CCU4_GCSS_S2SE_Msk, /**< Transfer Period, Compare and Passive Level x shadow register values to actual registers forT SLICE-2 */w XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_2 = CCU4_GCSS_S2DSE_Msk, /**< Transfer Dither compare shadow register valuek to actual register for SLICE-2 */u XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_2 = CCU4_GCSS_S2PSE_Msk, /**< Transfer Prescaler shadow register value toh actual register for SLICE-2 */t XMC_CCU4_SHADOW_TRANSFER_SLICE_3 = CCU4_GCSS_S3SE_Msk, /**< Transfer Period, Compare and Passive Level x shadow register values to actual registers forT SLICE-3 */w XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_3 = CCU4_GCSS_S3DSE_Msk, /**< Transfer Dither compare shadow register valuek to actual register for SLICE-3 */u XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_3 = CCU4_GCSS_S3PSE_Msk /**< Transfer Prescaler shadow register value toh actual register for SLICE-3 */} XMC_CCU4_SHADOW_TRANSFER_t;M#if defined(CCU4V3) || defined(DOXYGEN)/* Defined for XMC1400 devices only *//**' * Slice shadow transfer mode options.* * @note Only available for XMC1400 series */0typedef enum XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE{{ XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_IN_PERIOD_MATCH_AND_ONE_MATCH = 0U, /**< Shadow transfer is done in Period Match and] One match. */w XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_PERIOD_MATCH = 1U, /**< Shadow transfer is done only in Period Match. */p XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_ONE_MATCH = 2U /**< Shadow transfer is done only in One Match. */)} XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t;   /**/ * Immediate write into configuration register+ * @note Only available for XMC1400 series */&typedef enum XMC_CCU4_SLICE_WRITE_INTO{v XMC_CCU4_SLICE_WRITE_INTO_PERIOD_CONFIGURATION = CCU4_CC4_STC_IRPC_Msk, /**< Immediate or Coherent r Write into Period p Configuration */v XMC_CCU4_SLICE_WRITE_INTO_COMPARE_CONFIGURATION = CCU4_CC4_STC_IRCC_Msk, /**< Immediate or Coherent s Write into Compare p Configuration */v XMC_CCU4_SLICE_WRITE_INTO_PASSIVE_LEVEL_CONFIGURATION = CCU4_CC4_STC_IRLC_Msk, /**< Immediate or Coherent x Write into Passive Levelm Configuration */v XMC_CCU4_SLICE_WRITE_INTO_DITHER_VALUE_CONFIGURATION = CCU4_CC4_STC_IRDC_Msk, /**< Immediate or Coherent w Write into Dither Valuem Configuration */v XMC_CCU4_SLICE_WRITE_INTO_FLOATING_PRESCALER_VALUE_CONFIGURATION = CCU4_CC4_STC_IRFC_Msk /**< Immediate or Coherent ~ Write into Floating Prescaler v Value Configuration */} XMC_CCU4_SLICE_WRITE_INTO_t;/**G * Automatic Shadow Transfer request when writing into shadow register+ * @note Only available for XMC1400 series */?typedef enum XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO{| XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_PERIOD_SHADOW = CCU4_CC4_STC_ASPC_Msk, /**< Automatic Shadow~ Transfer request when writing into Period~ Shadow Register */| XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_COMPARE_SHADOW = CCU4_CC4_STC_ASCC_Msk, /**< Automatic Shadowy transfer requestz when writing intoƒ Compare Shadow Register */… XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_PASSIVE_LEVEL = CCU4_CC4_STC_ASLC_Msk, /**< Automatic Shadow transfer} request when writing‰ into Passive Level Register*/… XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_DITHER_SHADOW = CCU4_CC4_STC_ASDC_Msk, /**< Automatic Shadow transfer€ request when writingŠ into Dither Shadow Register */… XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_FLOATING_PRESCALER_SHADOW = CCU4_CC4_STC_ASFC_Msk /**< Automatic Shadow transfer} request when writingŠ into Floating Prescaler Shadoww register */7} XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t;#endif/**O * Used to create Mask needed for Multi-channel Shadow transfer enable/disable */ typedef enum XMC_CCU4_SLICE_MASK{5 XMC_CCU4_SLICE_MASK_SLICE_0 = 1U , /**< SLICE-0 */5 XMC_CCU4_SLICE_MASK_SLICE_1 = 2U , /**< SLICE-1 */5 XMC_CCU4_SLICE_MASK_SLICE_2 = 4U , /**< SLICE-2 */5 XMC_CCU4_SLICE_MASK_SLICE_3 = 8U /**< SLICE-3 */} XMC_CCU4_SLICE_MASK_t;v/********************************************************************************************************************* * DATA STRUCTURESv ********************************************************************************************************************//**C * Configuration data structure of an External Event(Event-0/1/2).A * Needed to configure the various aspects of an External Event.Q * This structure will not connect the external event with an external function. */ *typedef struct XMC_CCU4_SLICE_EVENT_CONFIG{d XMC_CCU4_SLICE_INPUT_t mapped_input; /**< Required input signal for the Event */h XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_t edge; /**< Select the event edge of the input signal.w This is needed for an edge sensitive External function.*/i XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_t level; /**< Select the event level of the input signal.x This is needed for an level sensitive External function.*/w XMC_CCU4_SLICE_EVENT_FILTER_t duration; /**< Low Pass filter duration in terms of fCCU clock cycles */ } XMC_CCU4_SLICE_EVENT_CONFIG_t;)/*Anonymous structure/union guard start*/#if defined(__CC_ARM) #pragma push #pragma anon_unions#elif defined(__TASKING__) #pragma warning 586#endif/**r * Configuration data structure for CCU4 slice. Specifically configures the CCU4 slice to compare mode operation.3 * This excludes event and function configuration. */ ,typedef struct XMC_CCU4_SLICE_COMPARE_CONFIG{ union { struct {K uint32_t timer_mode : 1; /**< Edge aligned or Centre Aligned.` Accepts enum ::XMC_CCU4_SLICE_TIMER_COUNT_MODE_t */L uint32_t monoshot : 1; /**< Single shot or Continuous mode .a Accepts enum :: XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t*/i uint32_t shadow_xfer_clear : 1; /**< Should PR and CR shadow xfer happen when timer is cleared? */ uint32_t : 10;R uint32_t dither_timer_period: 1; /**< Can the period of the timer dither? */Y uint32_t dither_duty_cycle : 1; /**< Can the compare match of the timer dither? */ uint32_t : 1;N uint32_t prescaler_mode: 1; /**< Normal or floating prescaler mode.^ Accepts enum :: XMC_CCU4_SLICE_PRESCALER_MODE_t*/ uint32_t : 8;I uint32_t mcm_enable : 1; /**< Multi-Channel mode enable? */ uint32_t : 6; }; uint32_t tc; };L uint32_t prescaler_initval : 4; /**< Initial prescaler divider value Y Accepts enum :: XMC_CCU4_SLICE_PRESCALER_t */i uint32_t float_limit : 4; /**< The max value which the prescaler divider can increment to */c uint32_t dither_limit : 4; /**< The value that determines the spreading of dithering */W uint32_t passive_level : 1; /**< Configuration of ST and OUT passive levels.d Accepts enum :: XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t*/] uint32_t timer_concatenation : 1; /**< Enables the concatenation of the timer if true.*/"} XMC_CCU4_SLICE_COMPARE_CONFIG_t;/**r * Configuration data structure for CCU4 slice. Specifically configures the CCU4 slice to capture mode operation.3 * This excludes event and function configuration. */ ,typedef struct XMC_CCU4_SLICE_CAPTURE_CONFIG{ union { struct { uint32_t : 4;s uint32_t fifo_enable : 1; /**< Should the capture registers be setup as a FIFO?(Extended capture mode)*/s uint32_t timer_clear_mode : 2; /**< How should the timer register be cleared upon detection of capture event?\ Accepts enum ::XMC_CCU4_SLICE_TIMER_CLEAR_MODE_t*/ uint32_t : 4;s uint32_t same_event : 1; /**< Should the capture event for C1V/C0V and C3V/C2V be same capture edge? */h uint32_t ignore_full_flag : 1; /**< Should updates to capture registers follow full flag rules? */ uint32_t : 3;x uint32_t prescaler_mode: 1; /**< Normal or floating prescaler Accepts enum :: XMC_CCU4_SLICE_PRESCALER_MODE_t*/ uint32_t : 15; }; uint32_t tc; };D uint32_t prescaler_initval : 4; /**< Prescaler divider value */g uint32_t float_limit : 4; /**< The max value which the prescaler divider can increment to */S uint32_t timer_concatenation : 1; /**< Enables the concatenation of the timer */"} XMC_CCU4_SLICE_CAPTURE_CONFIG_t;'/*Anonymous structure/union guard end*/#if defined(__CC_ARM) #pragma pop#elif defined(__TASKING__) #pragma warning restore#endifv/********************************************************************************************************************* * API Prototypesv ********************************************************************************************************************/#ifdef __cplusplus extern "C" {#endifR__STATIC_INLINE bool XMC_CCU4_IsValidModule(const XMC_CCU4_MODULE_t *const module){ bool tmp = false;  tmp = (module == CCU40); #if defined(CCU41) ! tmp = tmp || (module == CCU41);#endif#if defined(CCU42)! tmp = tmp || (module == CCU42);#endif#if defined(CCU43)! tmp = tmp || (module == CCU43);#endif  return tmp; } O__STATIC_INLINE bool XMC_CCU4_IsValidSlice(const XMC_CCU4_SLICE_t *const slice){ bool tmp = false;  tmp = (slice == CCU40_CC40);#if defined(CCU40_CC41) % tmp = tmp || (slice == CCU40_CC41);#endif#if defined(CCU40_CC42) % tmp = tmp || (slice == CCU40_CC42);#endif#if defined(CCU40_CC43) % tmp = tmp || (slice == CCU40_CC43);#endif#if defined(CCU41) % tmp = tmp || (slice == CCU41_CC40);#if defined(CCU41_CC41) % tmp = tmp || (slice == CCU41_CC41);#endif#if defined(CCU41_CC42) % tmp = tmp || (slice == CCU41_CC42);#endif#if defined(CCU41_CC43) % tmp = tmp || (slice == CCU41_CC43);#endif#endif #if defined(CCU42) % tmp = tmp || (slice == CCU42_CC40);#if defined(CCU42_CC41) % tmp = tmp || (slice == CCU42_CC41);#endif#if defined(CCU42_CC42) % tmp = tmp || (slice == CCU42_CC42);#endif#if defined(CCU42_CC43) % tmp = tmp || (slice == CCU42_CC43);#endif#endif#if defined(CCU43) % tmp = tmp || (slice == CCU43_CC40);#if defined(CCU43_CC41) % tmp = tmp || (slice == CCU43_CC41);#endif#if defined(CCU43_CC42) % tmp = tmp || (slice == CCU43_CC42);#endif#if defined(CCU43_CC43) % tmp = tmp || (slice == CCU43_CC43);#endif#endif   return tmp; } /**0 * @param module Constant pointer to CCU4 moduleH * @param mcs_action multi-channel shadow transfer request configuration * @return
 * None
 * * \parDescription:
2 * Initialization of global register GCTRL.
\nL * As part of module initialization, behaviour of the module upon detection[ * Multi-Channel Mode trigger is configured. Will also invoke the XMC_CCU4_EnableModule().[ * The API call would bring up the required CCU4 module and also initialize the module for/ * the required multi-channel shadow transfer. * * \parRelated APIs:
A * XMC_CCU4_SLICE_CompareInit()
XMC_CCU4_SLICE_CaptureInit(). */cvoid XMC_CCU4_Init(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_SLICE_MCMS_ACTION_t mcs_action);/**0 * @param module Constant pointer to CCU4 module3 * @param clock Choice of input clock to the module * @return
 * None
 * * \parDescription:
B * Selects the Module Clock by configuring GCTRL.PCIS bits.
\n\ * There are 3 potential clock sources. This API helps to select the required clock source.8 * Call to this API is valid after the XMC_CCU4_Init(). * * \parRelated APIs:
* None.
 */\void XMC_CCU4_SetModuleClock(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_CLOCK_t clock);/**0 * @param module Constant pointer to CCU4 module * @return
 * None
 * * \parDescription:
? * Enables the CCU4 module and brings it to active state.
\ng * Also disables the gating of the clock signal (if applicable depending on the device being selected).d * Invoke this API before any operations are done on the CCU4 module. Invoked from XMC_CCU4_Init(). * * \parRelated APIs:
X * XMC_CCU4_SetModuleClock()
XMC_CCU4_DisableModule()
XMC_CCU4_StartPrescaler(). */<void XMC_CCU4_EnableModule(XMC_CCU4_MODULE_t *const module);/**0 * @param module Constant pointer to CCU4 module * @return
 * None
 * * \parDescription:
g * Brings the CCU4 module to reset state and enables gating of the clock signal(if applicable depending' * on the device being selected).
\nF * Invoke this API when a CCU4 module needs to be disabled completely.Q * Any operation on the CCU4 module will have no effect after this API is called. * * \parRelated APIs:
8 * XMC_CCU4_EnableModule()
XMC_CCU4_DisableModule(). */=void XMC_CCU4_DisableModule(XMC_CCU4_MODULE_t *const module);/**0 * @param module Constant pointer to CCU4 module * @return
 * None
 * * \parDescription:
b * Starts the prescaler and restores clocks to the timer slices, by setting GIDLC.SPRB bit.
\ng * Once the input to the prescaler has been chosen and the prescaler divider of all slices programmed,O * the prescaler itself may be started. Invoke this API after XMC_CCU4_Init()S * (Mandatory to fully initialize the module).Directly accessed register is GIDLC. * * \parRelated APIs:
k * XMC_CCU4_Init()
XMC_CCU4_EnableClock()
XMC_CCU4_DisableClock()
XMC_CCU4_StartPrescaler()
 * XMC_CCU4_StopPrescaler(). */M__STATIC_INLINE void XMC_CCU4_StartPrescaler(XMC_CCU4_MODULE_t *const module){_ XMC_ASSERT("XMC_CCU4_StartPrescaler:Invalid Module Pointer", XMC_CCU4_IsValidModule(module));2 module->GIDLC |= (uint32_t) CCU4_GIDLC_SPRB_Msk;}/**0 * @param module Constant pointer to CCU4 module * @return
 * None
 * * \parDescription:
^ * Stops the prescaler and blocks clocks to the timer slices, by setting GIDLS.CPRB bit.
\n* * Opposite of the StartPrescaler routine.X * Clears the run bit of the prescaler. Ensures that the module clock is not supplied toA * the slices of the module.Registers directly accessed is GIDLS. * * \parRelated APIs:
q * XMC_CCU4_EnableClock()
XMC_CCU4_DisableClock()
XMC_CCU4_StartPrescaler()
XMC_CCU4_StopPrescaler(). */L__STATIC_INLINE void XMC_CCU4_StopPrescaler(XMC_CCU4_MODULE_t *const module){^ XMC_ASSERT("XMC_CCU4_StopPrescaler:Invalid Module Pointer", XMC_CCU4_IsValidModule(module));2 module->GIDLS |= (uint32_t) CCU4_GIDLS_CPRB_Msk;}/**0 * @param module Constant pointer to CCU4 module * @return
 * None
 * * \parDescription:
F * Returns the state of the prescaler, by reading GSTAT.PRB bit.
\ne * This will return true if the prescaler is running. If clock is being supplied to the slices of the * module then returns as true. * * \parRelated APIs:
q * XMC_CCU4_StartPrescaler()
XMC_CCU4_StopPrescaler()
XMC_CCU4_EnableClock()
XMC_CCU4_DisableClock(). */Q__STATIC_INLINE bool XMC_CCU4_IsPrescalerRunning(XMC_CCU4_MODULE_t *const module){c XMC_ASSERT("XMC_CCU4_IsPrescalerRunning:Invalid Module Pointer", XMC_CCU4_IsValidModule(module));b return((bool)((module->GSTAT & (uint32_t) CCU4_GSTAT_PRB_Msk) == (uint32_t)CCU4_GSTAT_PRB_Msk));}/**0 * @param module Constant pointer to CCU4 moduleJ * @param clock_mask Slices whose clocks are to be enabled simultaneously.P * Bit location 0/1/2/3 represents slice-0/1/2/3 respectively.( * Range: [0x1 to 0xF] * @return
 * None
 * * \parDescription:
c * Enables clocks of multiple slices at a time, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I,  * GIDLC.CS3I bits.\n\ng * Takes an input clock_mask, which determines the slices that would receive the clock. Bring them out $ * of the idle state simultaneously. * * \parRelated APIs:
6 * XMC_CCU4_EnableClock()
XMC_CCU4_DisableClock(). */m__STATIC_INLINE void XMC_CCU4_EnableMultipleClocks(XMC_CCU4_MODULE_t *const module, const uint8_t clock_mask){e XMC_ASSERT("XMC_CCU4_EnableMultipleClocks:Invalid Module Pointer", XMC_CCU4_IsValidModule(module));S XMC_ASSERT("XMC_CCU4_EnableMultipleClocks:Wrong clock mask", (clock_mask < 16U)); ) module->GIDLC |= (uint32_t) clock_mask;}/**0 * @param module Constant pointer to CCU4 moduleC * @param slice_number Slice for which the clock should be Enabled.( * Range: [0x0 to 0x3] * @return
 * None
 * * \parDescription:
V * Enables the slice timer clock, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, B * GIDLC.CS3I bits according to the selected \a slice_number.\n\nh * It is possible to enable/disable clock at slice level. This uses the \b slice_number to indicate the* * slice whose clock needs to be enabled. * * \parRelated APIs:
z * XMC_CCU4_DisableClock()
XMC_CCU4_EnableMultipleClocks()
XMC_CCU4_StartPrescaler()
XMC_CCU4_StopPrescaler(). */f__STATIC_INLINE void XMC_CCU4_EnableClock(XMC_CCU4_MODULE_t *const module, const uint8_t slice_number){\ XMC_ASSERT("XMC_CCU4_EnableClock:Invalid Module Pointer", XMC_CCU4_IsValidModule(module));O XMC_ASSERT("XMC_CCU4_EnableClock:Invalid Slice Number", (slice_number < 4U));2 module->GIDLC |= ((uint32_t) 1) << slice_number;}/**0 * @param module Constant pointer to CCU4 moduleD * @param slice_number Slice for which the clock should be disabled.( * Range: [0x0 to 0x3] * @return
 * None
 *  * \parDescription:
X * Disables the slice timer clock, by configuring GIDLS.SS0I, GIDLS.SSS1I, GIDLS.SSS2I, C * GIDLS.SSS3I bits according to the selected \a slice_number .\n\nK * It is possible to disable clock at slice level using the module pointer.O * \b slice_number is used to disable the clock to a given slice of the module.' * Directly accessed Register is GIDLS. * * \parRelated APIs:
y * XMC_CCU4_EnableClock()
XMC_CCU4_EnableMultipleClocks()
XMC_CCU4_StartPrescaler()
XMC_CCU4_StopPrescaler(). */g__STATIC_INLINE void XMC_CCU4_DisableClock(XMC_CCU4_MODULE_t *const module, const uint8_t slice_number){] XMC_ASSERT("XMC_CCU4_DisableClock:Invalid Module Pointer", XMC_CCU4_IsValidModule(module));P XMC_ASSERT("XMC_CCU4_DisableClock:Invalid Slice Number", (slice_number < 4U));2 module->GIDLS |= ((uint32_t) 1) << slice_number;}/**- * @param slice Constant pointer to CC4 Slice? * @param compare_init Pointer to slice configuration structure * @return
 * None
 * * \parDescription:
n * Initialization of a CC4 slice to compare mode, by configuring CC4yTC, CC4yCMC, CC4yPSC, CC4yDITH, CC4yPSL, $ * CC4yFPCS, CC4yCHC registers.\n\n E * CC4 slice is configured with Timer configurations in this routine.l * After initialization user has to explicitly enable the shadow transfer for the required values by calling9 * XMC_CCU4_EnableShadowTransfer() with appropriate mask. * * \parRelated APIs:
 * None. */>void XMC_CCU4_SLICE_CompareInit(XMC_CCU4_SLICE_t *const slice,[ const XMC_CCU4_SLICE_COMPARE_CONFIG_t *const compare_init);/**- * @param slice Constant pointer to CC4 Slice? * @param capture_init Pointer to slice configuration structure * @return
 * None
 * * \parDescription:
q * Initialization of a CC4 slice to capture mode, by configuring CC4yTC, CC4yCMC, CC4yPSC,CC4yFPCS registers.\n\ns * CC4 slice is configured with Capture configurations in this routine.After initialization user has to explicitlya * enable the shadow transfer for the required values by calling XMC_CCU4_EnableShadowTransfer() * with appropriate mask. * * \parRelated APIs:
G * XMC_CCU4_SLICE_Capture0Config()
XMC_CCU4_SLICE_Capture1Config(). */>void XMC_CCU4_SLICE_CaptureInit(XMC_CCU4_SLICE_t *const slice,[ const XMC_CCU4_SLICE_CAPTURE_CONFIG_t *const capture_init);/**- * @param slice Constant pointer to CC4 SliceD * @param event Map an External event to the External Start FunctionK * @param start_mode Behavior of slice when the start function is activated * @return
 * None
 * * \parDescription:
e * Configures the Start Function of the slice, by configuring CC4yCMC.ENDS and CC4yTC.ENDM bits.\n\nt * Start function is mapped with one of the 3 events. An external signal can control when a CC4 timer should start.i * Additionally, the behaviour of the slice upon activation of the start function is configured as well. * * \parRelated APIs:
a * XMC_CCU4_SLICE_StopConfig()
XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). */>void XMC_CCU4_SLICE_StartConfig(XMC_CCU4_SLICE_t *const slice,C const XMC_CCU4_SLICE_EVENT_t event,N const XMC_CCU4_SLICE_START_MODE_t start_mode);/**- * @param slice Constant pointer to CC4 SliceC * @param event Map an External event to the External Stop FunctionH * @param end_mode Behavior of slice when the stop function is activated * @return
 * None
 * * \parDescription:
e * Configures the Stop function for the slice, by configuring CC4yCMC.STRTS and CC4yTC.STRM bits.\n\nr * Stop function is mapped with one of the 3 events. An external signal can control when a CCU4 timer should stop.g * Additionally, the behaviour of the slice upon activation of the stop function is configured as well. * * \parRelated APIs:
b * XMC_CCU4_SLICE_StartConfig()
XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). */=void XMC_CCU4_SLICE_StopConfig(XMC_CCU4_SLICE_t *const slice,B const XMC_CCU4_SLICE_EVENT_t event,I const XMC_CCU4_SLICE_END_MODE_t end_mode);/**- * @param slice Constant pointer to CC4 SliceC * @param event Map an External event to the External load Function * @return
 * None
 * * \parDescription:
S * Configures the Load Function for the slice, by configuring CC4yCMC.LDS bit.\n\nV * Load function is mapped with one of the 3 events. Up on occurrence of the event,\nc * if CC4yTCST.CDIR set to 0,CC4yTIMER register is reloaded with the value from compare register\nb * if CC4yTCST.CDIR set to 1,CC4yTIMER register is reloaded with the value from period register\n * * \parRelated APIs:
B * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). */bvoid XMC_CCU4_SLICE_LoadConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);/**- * @param slice Constant pointer to CC4 SliceI * @param event Map an External event to the External Modulation Function* * @param mod_mode Desired Modulation modeH * @param synch_with_pwm Option to synchronize modulation with PWM starta * Pass \b true if the modulation needs to be synchronized with PWM signal. * @return
 * None
 *  * \parDescription:
f * Configures the Output Modulation Function of the slice, by configuring CCeyCMC.MOS, CC4yTC.EMT and  * CC4yTC.EMS bits.\n\n[ * Modulation function is mapped with one of the 3 events. The output signal of the CCU canh * be modulated according to a external input. Additionally, the behaviour of the slice upon activation4 * of the modulation function is configured as well. * * \parRelated APIs:
B * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). */Cvoid XMC_CCU4_SLICE_ModulationConfig(XMC_CCU4_SLICE_t *const slice,H const XMC_CCU4_SLICE_EVENT_t event,U const XMC_CCU4_SLICE_MODULATION_MODE_t mod_mode,@ const bool synch_with_pwm);/**- * @param slice Constant pointer to CC4 SliceD * @param event Map an External event to the External Count Function * @return
 * None
 *  * \parDescription:
S * Configures the Count Function of the slice, by configuring CC4yCMC.CNTS bit.\n\nU * Count function is mapped with one of the 3 events. CCU4 slice can take an externalF * signal to act as the counting event. The CCU4 slice would count the* * edges present on the \b event selected. * * \parRelated APIs:
B * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). */cvoid XMC_CCU4_SLICE_CountConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);/**- * @param slice Constant pointer to CC4 SliceF * @param event Map an External event to the External Gating Function * @return
 * None
 *  * \parDescription:
U * Configures the Gating Function of the slice, by configuring CC4yCMC.GATES bit.\n\ng * Gating function is mapped with one of the 3 events. A CCU4 slice can use an input signal that wouldn * operate as counter gating. If the configured Active level is detected the counter will gate all the pulses. * * \parRelated APIs:
B * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). */bvoid XMC_CCU4_SLICE_GateConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);/**- * @param slice Constant pointer to CC4 Slice? * @param event Map an External event to the Capture-0 Function * @return
 * None
 *  * \parDescription:
X * Configures the Capture-0 Function of the slice, by configuring CC4yCMC.CAP0S bit.\n\nk * Capture function is mapped with one of the 3 events. A CCU4 slice can be configured into capture-0 modek * with the selected \b event. In this mode the CCU4 will capture the timer value into CC4yC0V and CC4yC1V. * * \parRelated APIs:
B * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). */fvoid XMC_CCU4_SLICE_Capture0Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);/**- * @param slice Constant pointer to CC4 Slice? * @param event Map an External event to the Capture-1 Function * @return
 * None
 *  * \parDescription:
X * Configures the Capture-1 Function of the slice, by configuring CC4yCMC.CAP1S bit.\n\ne * Capture function is mapped with one of the 3 events. A CCU4 slice can be configured into capture-1p * mode with the selected \b event. In this mode the CCU4 will capture the timer value into CC4yC2V and CC4yC3V. * * \parRelated APIs:
B * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). */fvoid XMC_CCU4_SLICE_Capture1Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);/**- * @param slice Constant pointer to CC4 Slice * @return
R * bool would return true if the extended capture read back mode is enabled
 * * \parDescription:
n * Checks if Extended capture mode read is enabled for particular slice or not, by reading CC4yTC.ECM bit.\n\n\ * In this mode the there is only one associated read address for all the capture registers.C * Individual capture registers can still be accessed in this mode. * * \parRelated APIs:
( * XMC_CCU4_GetCapturedValueFromFifo(). */a__STATIC_INLINE bool XMC_CCU4_SLICE_IsExtendedCapReadEnabled(const XMC_CCU4_SLICE_t *const slice){m XMC_ASSERT("XMC_CCU4_SLICE_IsExtendedCapReadEnabled:Invalid Module Pointer", XMC_CCU4_IsValidSlice(slice));` return((bool)((slice->TC & (uint32_t) CCU4_CC4_TC_ECM_Msk) == (uint32_t)CCU4_CC4_TC_ECM_Msk));}U#if defined(CCU4V1) /* Defined for XMC4500, XMC4400, XMC4200, XMC4100 devices only *//**0 * @param module Constant pointer to CCU4 moduleS * @param slice_number to check whether read value belongs to required slice or not * @return
\ * int32_t Returns -1 if the FIFO value being retrieved is not from the \b slice_number.n * Returns the value captured in the \b slice_number, if captured value is from the correct slice.- * Range: [0x0 to 0xFFFF] * * \parDescription:
4 * Read captured value from FIFO(ECRD register).\n\nx * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured w * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the t * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be - * derived/inferred from the captured values. * * \parRelated APIs:
. * XMC_CCU4_SLICE_IsExtendedCapReadEnabled().J * @note Only available for XMC4500, XMC4400, XMC4200 and XMC4100 series  */mint32_t XMC_CCU4_GetCapturedValueFromFifo(const XMC_CCU4_MODULE_t *const module, const uint8_t slice_number);#else/**- * @param slice Constant pointer to CC4 SliceW * @param set The capture register set from which the captured value is to be retrieved * @return
@ * uint32_t Returns the value captured in the \b slice_number% * Range: [0x0 to 0xFFFF] * * \parDescription:
> * Read captured value from FIFO(CC4yECRD0 and CC4yECRD1).\n\nx * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured w * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the t * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be - * derived/inferred from the captured values. * * \parRelated APIs:
. * XMC_CCU4_SLICE_IsExtendedCapReadEnabled().• * @note Defined for XMC4800, XMC4700, XMC4500, XMC4400, XMC4200, XMC4100 devices only. For other devices use XMC_CCU4_GetCapturedValueFromFifo() API */Uuint32_t XMC_CCU4_SLICE_GetCapturedValueFromFifo(const XMC_CCU4_SLICE_t *const slice,W const XMC_CCU4_SLICE_CAP_REG_SET_t set);#endif/**- * @param slice Constant pointer to CC4 SliceN * @param event Map an External event to the External Count Direction Function * @return
 * None
 *  * \parDescription:
S * Configures the Count Direction of the slice, by configuring CC4yCMC.UDS bit.\n\nh * Count direction function is mapped with one of the 3 events. A slice can be configured to change the = * CC4yTIMER count direction depending on an external signal. * * \parRelated APIs:
B * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). */gvoid XMC_CCU4_SLICE_DirectionConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);/**- * @param slice Constant pointer to CC4 Slice * @return
 * None
 * * \parDescription:
` * Configures the status bit override Function of the slice, by configuring CC4yCMC.OFS bit.\n\nk * Status bit override function is mapped with one of the 3 events. A slice can be configured to change theH * output of the timer's CC4yST signal depending on an external signal.  * * \parRelated APIs:
5 * XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(). */Kvoid XMC_CCU4_SLICE_StatusBitOverrideConfig(XMC_CCU4_SLICE_t *const slice);/**- * @param slice Constant pointer to CC4 SliceH * @param exit_mode How should a previously logged trap state be exited?X * @param synch_with_pwm Should exit of trap state be synchronized with PWM cycle start? * @return
 * None
 * * \parDescription:
q * Configures the Trap Function of the slice, by configuring CC4yCMC.TS, CC4yTC.TRPSE, and CC4yTC.TRPSW bits.\n\n[ * Trap function is mapped with Event-2. Criteria for exiting the trap state is configured.O * This trap function allows PWM outputs to react on the state of an input pin.L * Thus PWM output can be forced to inactive state upon detection of a trap.h * It is also possible to synchronize the trap function with the PWM signal using the \b synch_with_pwm. * * \parRelated APIs:
B * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). */=void XMC_CCU4_SLICE_TrapConfig(XMC_CCU4_SLICE_t *const slice,O const XMC_CCU4_SLICE_TRAP_EXIT_MODE_t exit_mode,4 bool synch_with_pwm);/**- * @param slice Constant pointer to CC4 Slice: * @param ev1_config Pointer to event 1 configuration data: * @param ev2_config Pointer to event 2 configuration data * @return
 * None
 * * * \parDescription:
m * Map Status bit override function with an Event1 & Event 2 of the slice and configure CC4yINS register.\n\nu * Details such as the input mapped to the event, event detection criteria and Low Pass filter options are programmedc * by this routine for the events 1 & 2. Event-1 input would be the trigger to override the value.- * Event-2 input would be the override value. * * \parRelated APIs:
- * XMC_CCU4_SLICE_StatusBitOverrideConfig(). */Rvoid XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU4_SLICE_t *const slice,j const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev1_config,k const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev2_config);/**- * @param slice Constant pointer to CC4 Slice@ * @param event The External Event which needs to be configured.5 * @param config Pointer to event configuration data. * @return
 * None
 * * \parDescription:
P * Configures an External Event of the slice, by updating CC4yINS register .\n\n^ * Details such as the input mapped to the event, event detection criteria and low pass filterc * options are programmed by this routine. The Event \b config will configure the input selection,R * the edge selection, the level selection and the Low pass filter for the event. * * \parRelated APIs:
d * XMC_CCU4_SLICE_StartConfig()
XMC_CCU4_SLICE_StopConfig()
XMC_CCU4_SLICE_LoadConfig()
j * XMC_CCU4_SLICE_ModulationConfig()
XMC_CCU4_SLICE_CountConfig()
XMC_CCU4_SLICE_GateConfig()
p * XMC_CCU4_SLICE_Capture0Config()
XMC_CCU4_SLICE_Capture1Config()
XMC_CCU4_SLICE_DirectionConfig()
M * XMC_CCU4_SLICE_StatusBitOverrideConfig()
XMC_CCU4_SLICE_TrapConfig(). */Avoid XMC_CCU4_SLICE_ConfigureEvent(XMC_CCU4_SLICE_t *const slice,F const XMC_CCU4_SLICE_EVENT_t event,V const XMC_CCU4_SLICE_EVENT_CONFIG_t *const config);/**- * @param slice Constant pointer to CC4 Slice@ * @param event The External Event which needs to be configured.L * @param input One of the 16 inputs meant to be mapped to the desired event * @return
 * None
 * *  * \parDescription:
O * Selects an input for an external event, by configuring CC4yINS register.\n\nS * It is possible to select one of the possible 16 input signals for a given Event.< * This configures the CC4yINS.EVxIS for the selected event. * * \parRelated APIs:
d * XMC_CCU4_SLICE_StartConfig()
XMC_CCU4_SLICE_StopConfig()
XMC_CCU4_SLICE_LoadConfig()
j * XMC_CCU4_SLICE_ModulationConfig()
XMC_CCU4_SLICE_CountConfig()
XMC_CCU4_SLICE_GateConfig()
p * XMC_CCU4_SLICE_Capture0Config()
XMC_CCU4_SLICE_Capture1Config()
XMC_CCU4_SLICE_DirectionConfig()
M * XMC_CCU4_SLICE_StatusBitOverrideConfig()
XMC_CCU4_SLICE_TrapConfig(). */;void XMC_CCU4_SLICE_SetInput(XMC_CCU4_SLICE_t *const slice,@ const XMC_CCU4_SLICE_EVENT_t event,A const XMC_CCU4_SLICE_INPUT_t input);/**- * @param slice Constant pointer to CC4 Slice * @return
 * None
 * * \parDescription:
v * Enables the trap feature, by setting CC4yTC.TRAPE0, CC4yTC.TRAPE1, CC4yTC.TRAPE2 and CC4yTC.TRAPE3 bit based on the * \a out_mask.\n\nv * A particularly useful feature where the PWM output can be forced inactive upon detection of a trap. The trap signalc * can be the output of a sensing element which has just detected an abnormal electrical condition. * * \parRelated APIs:
h * XMC_CCU4_SLICE_TrapConfig()
XMC_CCU4_SLICE_DisableTrap()
XMC_CCU4_SLICE_ConfigureEvent()
 * XMC_CCU4_SLICE_SetInput(). */M__STATIC_INLINE void XMC_CCU4_SLICE_EnableTrap(XMC_CCU4_SLICE_t *const slice){^ XMC_ASSERT("XMC_CCU4_SLICE_EnableTrap:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));0 slice->TC |= (uint32_t) CCU4_CC4_TC_TRAPE_Msk;}/**- * @param slice Constant pointer to CC4 Slice * @return
 * None
 * * \parDescription:
x * Disables the trap feature, by clearing CC4yTC.TRAPE0, CC4yTC.TRAPE1, CC4yTC.TRAPE2 and CC4yTC.TRAPE3 bit based on the * \a out_mask.\n\n.\n\nH * This API will revert the changes done by XMC_CCU4_SLICE_EnableTrap().U * This Ensures that the TRAP function has no effect on the output of the CCU4 slice. * * \parRelated APIs:
* XMC_CCU4_SLICE_EnableTrap(). */N__STATIC_INLINE void XMC_CCU4_SLICE_DisableTrap(XMC_CCU4_SLICE_t *const slice){_ XMC_ASSERT("XMC_CCU4_SLICE_DisableTrap:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));3 slice->TC &= ~((uint32_t) CCU4_CC4_TC_TRAPE_Msk);}/**- * @param slice Constant pointer to CC4 Slice * @return
L * bool returns \b true if the Timer is running else it returns \b false. * * \parDescription:
a * Returns the state of the timer (Either Running or stopped(idle)), by reading CC4yTCST.TRB bit. * * \parRelated APIs:
? * XMC_CCU4_SLICE_StartTimer()
XMC_CCU4_SLICE_StopTimer(). */W__STATIC_INLINE bool XMC_CCU4_SLICE_IsTimerRunning(const XMC_CCU4_SLICE_t *const slice){b XMC_ASSERT("XMC_CCU4_SLICE_GetTimerStatus:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));R return (bool)(((slice->TCST) & CCU4_CC4_TCST_TRB_Msk) == CCU4_CC4_TCST_TRB_Msk);}/**- * @param slice Constant pointer to CC4 Slice * @return
] * ::XMC_CCU4_SLICE_TIMER_COUNT_DIR_t returns the direction in which the timer is counting. * * \parDescription:
J * Returns the timer counting direction, by reading CC4yTCST.CDIR bit.\n\nE * This API will return the direction in which the timer is currentlyi * incrementing(XMC_CCU4_SLICE_TIMER_COUNT_DIR_UP) or decrementing (XMC_CCU4_SLICE_TIMER_COUNT_DIR_DOWN). * * \parRelated APIs:
* None. */s__STATIC_INLINE XMC_CCU4_SLICE_TIMER_COUNT_DIR_t XMC_CCU4_SLICE_GetCountingDir(const XMC_CCU4_SLICE_t *const slice){b XMC_ASSERT("XMC_CCU4_SLICE_GetCountingDir:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));q return((XMC_CCU4_SLICE_TIMER_COUNT_DIR_t)(((slice->TCST) & CCU4_CC4_TCST_CDIR_Msk) >> CCU4_CC4_TCST_CDIR_Pos));}/**- * @param slice Constant pointer to CC4 Slice * @return
 * None
 * * \parDescription:
J * Starts the timer counting operation, by setting CC4yTCSET.TRBS bit.\n\nN * It is necessary to have configured the CC4 slice before starting its timer.N * Before the Timer is started ensure that the clock is provided to the slice. * * \parRelated APIs:
 * XMC_CCU4_SLICE_StopTimer(). */M__STATIC_INLINE void XMC_CCU4_SLICE_StartTimer(XMC_CCU4_SLICE_t *const slice){^ XMC_ASSERT("XMC_CCU4_SLICE_StartTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));) slice->TCSET = CCU4_CC4_TCSET_TRBS_Msk;}/**- * @param slice Constant pointer to CC4 Slice * @return
 * None
 * * \parDescription:
 * Stops the Timer.
\n_ * Timer counting operation can be stopped by invoking this API, by setting CC4yTCCLR.TRBC bit. * * \parRelated APIs:
* XMC_CCU4_SLICE_StartTimer(). */L__STATIC_INLINE void XMC_CCU4_SLICE_StopTimer(XMC_CCU4_SLICE_t *const slice){] XMC_ASSERT("XMC_CCU4_SLICE_StopTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));5 slice->TCCLR |= (uint32_t) CCU4_CC4_TCCLR_TRBC_Msk;}/**- * @param slice Constant pointer to CC4 Slice * @return
 * None
 * * \parDescription:
D * Resets the timer count to zero, by setting CC4yTCCLR.TCC bit.\n\nJ * A timer which has been stopped can still retain the last counted value.; * After invoking this API the timer value will be cleared. * * \parRelated APIs:
* XMC_CCU4_SLICE_StartTimer(). */M__STATIC_INLINE void XMC_CCU4_SLICE_ClearTimer(XMC_CCU4_SLICE_t *const slice){^ XMC_ASSERT("XMC_CCU4_SLICE_ClearTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));4 slice->TCCLR |= (uint32_t) CCU4_CC4_TCCLR_TCC_Msk;}/**- * @param slice Constant pointer to CC4 Slice * @return
k * ::XMC_CCU4_SLICE_MODE_t returns XMC_CCU4_SLICE_MODE_COMPARE if the slice is operating in compare modei * returns XMC_CCU4_SLICE_MODE_CAPTURE if the slice is operating in capture mode * * \parDescription:
j * Retrieves the current mode of operation in the slice (either Capture mode or Compare mode), by reading  * CC4yTC.CMOD bit.\n\no * Ensure that before invoking this API the CCU4 slice should be configured otherwise the output of this API is * invalid. * * \parRelated APIs:
* None. */f__STATIC_INLINE XMC_CCU4_SLICE_MODE_t XMC_CCU4_SLICE_GetSliceMode(const XMC_CCU4_SLICE_t *const slice){` XMC_ASSERT("XMC_CCU4_SLICE_GetSliceMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));` return((XMC_CCU4_SLICE_MODE_t)(((slice->TC) & CCU4_CC4_TC_CMOD_Msk) >> CCU4_CC4_TC_CMOD_Pos));}/**- * @param slice Constant pointer to CC4 SliceI * @param mode Desired repetition mode (Either single shot or Continuous) * @return
 * None
 * * \parDescription:
j * Configures the Timer to either Single shot mode or continuous mode, by configuring CC4yTC.TSSM bit.\n\nx * The timer will count up to the terminal count as specified in the period register and stops immediately if the repeatx * mode has been set to single shot. In the continuous mode of operation, the timer starts counting all over again after * reaching the terminal count. * * \parRelated APIs:
( * XMC_CCU4_SLICE_GetTimerRepeatMode(). */uvoid XMC_CCU4_SLICE_SetTimerRepeatMode(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t mode);/**- * @param slice Constant pointer to CC4 Slice * @return
w * ::XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t returns XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT if continuous mode is selectedv * returns XMC_CCU4_SLICE_TIMER_REPEAT_MODE_SINGLE if single shot mode is selected * * \parDescription:
o * Retrieves the Timer repeat mode, either Single shot mode or continuous mode, by reading CC4yTC.TSSM bit.\n\nx * The timer will count up to the terminal count as specified in the period register and stops immediately if the repeath * mode has been set to single shot mode. In the continuous mode of operation, the timer starts counting4 * all over again after reaching the terminal count. * * \parRelated APIs:
( * XMC_CCU4_SLICE_SetTimerRepeatMode(). */U__STATIC_INLINE XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t XMC_CCU4_SLICE_GetTimerRepeatMode(r const XMC_CCU4_SLICE_t *const slice){f XMC_ASSERT("XMC_CCU4_SLICE_GetTimerRepeatMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));m return((XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t)(((slice->TC) & CCU4_CC4_TC_TSSM_Msk) >> CCU4_CC4_TC_TSSM_Pos));}/**- * @param slice Constant pointer to CC4 SliceL * @param mode Desired counting mode (Either Edge Aligned or Center Aligned) * @return
 * None
 * * \parDescription:
o * Configures the timer counting mode either Edge Aligned or Center Aligned, by configuring CC4yTC.TCM bit.\n\nu * In the edge aligned mode, the timer counts from 0 to the terminal count. Once the timer count has reached a presetu * compare value, the timer status output asserts itself. It will now deassert only after the timer count reaches thex * terminal count.\n In the center aligned mode, the timer first counts from 0 to the terminal count and then back to 0.r * During this upward and downward counting, the timer status output stays asserted as long as the timer value is " * greater than the compare value. * * \parRelated APIs:
* * XMC_CCU4_SLICE_GetTimerCountingMode(). */vvoid XMC_CCU4_SLICE_SetTimerCountingMode(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_TIMER_COUNT_MODE_t mode);/**- * @param slice Constant pointer to CC4 Slice * @return
s * ::XMC_CCU4_SLICE_TIMER_COUNT_MODE_t returns XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA if edge aligned mode is selectedt * returns XMC_CCU4_SLICE_TIMER_COUNT_MODE_CA if center aligned mode is selected * * \parDescription:
f * Retrieves timer counting mode either Edge aligned or Center Aligned, by reading CC4yTC.TCM bit.\n\n * * \parRelated APIs:
* * XMC_CCU4_SLICE_SetTimerCountingMode(). */V__STATIC_INLINE XMC_CCU4_SLICE_TIMER_COUNT_MODE_t XMC_CCU4_SLICE_GetTimerCountingMode(q const XMC_CCU4_SLICE_t *const slice){h XMC_ASSERT("XMC_CCU4_SLICE_GetTimerCountingMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));j return((XMC_CCU4_SLICE_TIMER_COUNT_MODE_t)(((slice->TC) & CCU4_CC4_TC_TCM_Msk) >> CCU4_CC4_TC_TCM_Pos));}/**- * @param slice Constant pointer to CC4 Slice' * @param period_val Timer period value * Range: [0x0 to 0xFFFF] * @return
 * None
 * * \parDescription:
> * Programs the timer period, by writing CC4yPRS register.\n\nq * The frequency of counting/ PWM frequency is determined by this value. The period value is written to a shadow V * register. Explicitly enable the shadow transfer for the the period value by callingq * XMC_CCU4_EnableShadowTransfer() with appropriate mask. If shadow transfer is enabled and the timer is running,] * a period match transfers the value from the shadow register to the actual period register. * * \parRelated APIs:
) * XMC_CCU4_SLICE_GetTimerPeriodMatch(). */q__STATIC_INLINE void XMC_CCU4_SLICE_SetTimerPeriodMatch(XMC_CCU4_SLICE_t *const slice, const uint16_t period_val){g XMC_ASSERT("XMC_CCU4_SLICE_SetTimerPeriodMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));% slice->PRS = (uint32_t) period_val;}/**- * @param slice Constant pointer to CC4 Slice * @return
4 * uint16_t returns the current timer period value$ * Range: [0x0 to 0xFFFF] * * \parDescription:
X * Retrieves the timer period value currently effective, by reading CC4yPR register.\n\nc * If the timer is active then the value being returned is currently being used for the PWM period. * * \parNote:
` * The XMC_CCU4_SLICE_SetTimerPeriodMatch() would set the new period value to a shadow register.i * This would only transfer the new values into the actual period register if the shadow transfer requestl * is enabled and if a period match occurs. Hence a consecutive call to XMC_CCU4_SLICE_GetTimerPeriodMatch()H * would not reflect the new values until the shadow transfer completes. * * \parRelated APIs:
) * XMC_CCU4_SLICE_SetTimerPeriodMatch(). */`__STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerPeriodMatch(const XMC_CCU4_SLICE_t *const slice){g XMC_ASSERT("XMC_CCU4_SLICE_SetTimerPeriodMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); return((uint16_t)slice->PR);}/**- * @param slice Constant pointer to CC4 Slice) * @param compare_val Timer compare value * @return
 * None
 * * \parDescription:
G * Programs the timer compare value, by writing CC4yCRS register.
\n3 * The PWM duty cycle is determined by this value._ * The compare value is written to a shadow register. Explicitly enable the shadow transfer forO * the the period/compare value by calling XMC_CCU4_EnableShadowTransfer() withK * appropriate mask.If shadow transfer is enabled and the timer is running,^ * a period match transfers the value from the shadow register to the actual compare register. * * \parRelated APIs:
) * XMC_CCU4_SLICE_GetTimerPeriodMatch(). */s__STATIC_INLINE void XMC_CCU4_SLICE_SetTimerCompareMatch(XMC_CCU4_SLICE_t *const slice, const uint16_t compare_val){h XMC_ASSERT("XMC_CCU4_SLICE_SetTimerCompareMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));& slice->CRS = (uint32_t) compare_val;}/**- * @param slice Constant pointer to CC4 Slice * @return
5 * uint16_t returns the current timer compare value$ * Range: [0x0 to 0xFFFF] * * \parDescription:
Z * Retrieves the timer compare value currently effective, by reading CC4yCRS register.\n\nx * If the timer is active then the value being returned is currently being for the PWM duty cycle( timer compare value). * * \parNote:
b * The XMC_CCU4_SLICE_SetTimerCompareMatch() would set the new compare value to a shadow register.j * This would only transfer the new values into the actual compare register if the shadow transfer requestm * is enabled and if a period match occurs. Hence a consecutive call to XMC_CCU4_SLICE_GetTimerCompareMatch()H * would not reflect the new values until the shadow transfer completes.( * Directly accessed Register is CC4yCR. * * \parRelated APIs:
* * XMC_CCU4_SLICE_SetTimerCompareMatch(). */a__STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerCompareMatch(const XMC_CCU4_SLICE_t *const slice){h XMC_ASSERT("XMC_CCU4_SLICE_GetTimerCompareMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); return((uint16_t)slice->CR);}/**0 * @param module Constant pointer to CCU4 moduleQ * @param shadow_transfer_msk Shadow transfer request mask for various transfers.f * Use ::XMC_CCU4_SHADOW_TRANSFER_t enum items to create a mask of choice,> * using a bit wise OR operation. * @return
 * None
 * * \parDescription:
h * Requests of shadow transfer for Period, Compare, Passive level, dither and prescaler, by configuring  * the GCSS register.\n\nq * The transfer from the shadow registers to the actual registers is done in the immediate next occurrence of the3 * shadow transfer trigger after the API is called. *a * Any call to XMC_CCU4_SLICE_SetTimerPeriodMatch()
XMC_CCU4_SLICE_SetTimerCompareMatch()
c * XMC_CCU4_SLICE_SetPrescaler()
XMC_CCU4_SLICE_CompareInit()
XMC_CCU4_SLICE_CaptureInit().! * must be succeeded by this API.& * Directly accessed Register is GCSS. * * \parRelated APIs:
* None. */w__STATIC_INLINE void XMC_CCU4_EnableShadowTransfer(XMC_CCU4_MODULE_t *const module, const uint32_t shadow_transfer_msk){d XMC_ASSERT("XMC_CCU4_EnableShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidModule(module));1 module->GCSS = (uint32_t)shadow_transfer_msk; }/**- * @param slice Constant pointer to CC4 Slice * @return
- * uint16_t returns the current timer value$ * Range: [0x0 to 0xFFFF] * * \parDescription:
A * Retrieves the latest timer value, from CC4yTIMER register.\n\n * * \parRelated APIs:
# * XMC_CCU4_SLICE_SetTimerValue(). */Z__STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerValue(const XMC_CCU4_SLICE_t *const slice){a XMC_ASSERT("XMC_CCU4_SLICE_GetTimerValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));! return((uint16_t)slice->TIMER);}/**- * @param slice Constant pointer to CC4 SliceV * @param timer_val The new timer value that has to be loaded into the TIMER register.* * Range: [0x0 to 0xFFFF] * @return
 * None
 * * \parDescription:
? * Loads a new timer value, by setting CC4yTIMER register.\n\n *  * \parNote:
7 * Request to load is ignored if the timer is running. * * \parRelated APIs:
# * XMC_CCU4_SLICE_GetTimerValue(). */j__STATIC_INLINE void XMC_CCU4_SLICE_SetTimerValue(XMC_CCU4_SLICE_t *const slice, const uint16_t timer_val){a XMC_ASSERT("XMC_CCU4_SLICE_SetTimerValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));& slice->TIMER = (uint32_t) timer_val;}/**- * @param slice Constant pointer to CC4 SliceH * @param period_dither Boolean instruction on dithering of period matchG * @param duty_dither Boolean instruction on dithering of compare match% * @param spread Dither compare value * @return
 * None
 * * \parDescription:
h * Enables dithering of PWM frequency and duty cycle, by configuring CC4yTC.DITHE and CC4yDITS bits.\n\nt * Some control loops are slow in updating PWM frequency and duty cycle. In such a case, a Bresenham style dithering^ * can help reduce long term errors. Dithering can be applied to period and duty individually,P * this can be selected using the parameter \b period_dither and \b duty_dither.v * The \b spread would provide the dither compare value. If the dither counter value is less than this \b spread then l * the period/compare values would be dithered according to the dither mode selected. This API would invoke * * XMC_CCU4_SLICE_SetDitherCompareValue(). * * \parNote:
^ * After this API call, XMC_CCU4_EnableShadowTransfer() has to be called with appropriate mask * to transfer the dither value. * * \parRelated APIs:
& * XMC_CCU4_SLICE_DisableDithering(). */Bvoid XMC_CCU4_SLICE_EnableDithering(XMC_CCU4_SLICE_t *const slice,= const bool period_dither,; const bool duty_dither,: const uint8_t spread);/**- * @param slice Constant pointer to CC4 Slice * @return
 * None
 * * \parDescription:
Y * Disables dithering of PWM frequency and duty cycle, by clearing CC4yTC.DITHE bits.\n\nR * This disables the Dither mode that was set in XMC_CCU4_SLICE_EnableDithering().4 * This API will not clear the dither compare value. * * \parRelated APIs:
% * XMC_CCU4_SLICE_EnableDithering(). */S__STATIC_INLINE void XMC_CCU4_SLICE_DisableDithering(XMC_CCU4_SLICE_t *const slice){d XMC_ASSERT("XMC_CCU4_SLICE_DisableDithering:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));3 slice->TC &= ~((uint32_t) CCU4_CC4_TC_DITHE_Msk);}/**- * @param slice Constant pointer to CC4 Slice * @return
 * None
 * * \parDescription:
A * Enables the floating prescaler, by setting CC4yTC.FPE bit.\n\ns * The prescaler divider starts with an initial value and increments upon every period match. It keeps incrementingx * until a ceiling (prescaler compare value) is hit and thereafter rolls back to the original prescaler divider value.\nq * It is necessary to have programmed an initial divider value and a compare value before the feature is enabled. * * \parRelated APIs:
g * XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue()
XMC_CCU4_SLICE_DisableFloatingPrescaler()
" * XMC_CCU4_SLICE_SetPrescaler(). */Z__STATIC_INLINE void XMC_CCU4_SLICE_EnableFloatingPrescaler(XMC_CCU4_SLICE_t *const slice){k XMC_ASSERT("XMC_CCU4_SLICE_EnableFloatingPrescaler:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));. slice->TC |= (uint32_t) CCU4_CC4_TC_FPE_Msk;}/**- * @param slice Constant pointer to CC4 Slice * @return
 * None
 * * \parDescription:
C * Disables the floating prescaler, by clearing CC4yTC.FPE bit.\n\n6 * This would return the prescaler to the normal mode.G * The prescaler that would be applied is the value present in CC4yPSC. * * \parRelated APIs:
- * XMC_CCU4_SLICE_EnableFloatingPrescaler(). */[__STATIC_INLINE void XMC_CCU4_SLICE_DisableFloatingPrescaler(XMC_CCU4_SLICE_t *const slice){l XMC_ASSERT("XMC_CCU4_SLICE_DisableFloatingPrescaler:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));1 slice->TC &= ~((uint32_t) CCU4_CC4_TC_FPE_Msk);}/**- * @param slice Constant pointer to CC4 Slice' * @param comp_val Dither compare value& * Range: [0x0 to 0xF] * @return
 * None
 * * \parDescription:
K * Sets the dither spread/compare value, by setting CC4yDITS.DCVS bits.\n\nj * This value is the cornerstone of PWM dithering feature. Dithering is applied/done when the value in thej * dithering counter is less than this compare/spread value. For all dithering counter values greater thanm * the spread value, there is no dithering. After setting the value XMC_CCU4_EnableShadowTransfer() has to be * called with appropriate mask. * * \parRelated APIs:
% * XMC_CCU4_SLICE_EnableDithering(). */p__STATIC_INLINE void XMC_CCU4_SLICE_SetDitherCompareValue(XMC_CCU4_SLICE_t *const slice, const uint8_t comp_val){i XMC_ASSERT("XMC_CCU4_SLICE_SetDitherCompareValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); slice->DITS = comp_val;}/**- * @param slice Constant pointer to CC4 Slice) * @param div_val Prescaler divider value& * Range: [0x0 to 0xF] * @return
 * None
 * * \parDescription:
g * Programs the slice specific prescaler divider, by configuring the CC4yPSC and CC4yFPC registers.\n\n\ * The prescaler divider may only be programmed after the prescaler run bit has been cleared' * by calling XMC_CCU4_StopPrescaler(). * * \parRelated APIs:
6 * XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue(). */Wvoid XMC_CCU4_SLICE_SetPrescaler(XMC_CCU4_SLICE_t *const slice, const uint8_t div_val);/**- * @param slice Constant pointer to CC4 Slice1 * @param cmp_val Prescaler divider compare value& * Range: [0x0 to 0xF] * @return
 * None
 * * \parDescription:
e * Programs the slice specific prescaler divider compare value, by configuring CC4yFPCS register.\n\ns * The compare value is applicable only in floating mode of operation. The prescaler divider starts with an initiale * value and increments to the compare value steadily upon every period match. Once prescaler dividery * equals the prescaler divider compare value, the value in the former resets back to the PVAL (from FPC). After setting U * the value, XMC_CCU4_EnableShadowTransfer() has to be called with appropriate mask. * * \parRelated APIs:
" * XMC_CCU4_SLICE_SetPrescaler(). */c__STATIC_INLINE void XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue(XMC_CCU4_SLICE_t *const slice,[ const uint8_t cmp_val){t XMC_ASSERT("XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));% /* write to the shadow register */# slice->FPCS = (uint32_t) cmp_val;}/**- * @param slice Constant pointer to CC4 Slice * @return
 * None
 * * \parDescription:
C * Enables the multichannel mode, by setting CC4yTC.MCME bit.
\n_ * The output state of the Timer slices can be controlled in parallel by a single input signal.w * A particularly useful feature in motor control applications where the PWM output of multiple slices of a module can x * be gated and ungated by multi-channel gating inputs connected to the slices. A peripheral like POSIF connected to thex * motor knows exactly which of the power drive switches are to be turned on and off at any instant. It can thus throughg * a gating bus (known as multi-channel inputs) control which of the slices output stays gated/ungated. * * \parRelated APIs:
^ * XMC_CCU4_SLICE_DisableMultiChannelMode()
XMC_CCU4_SetMultiChannelShadowTransferMode(). */Y__STATIC_INLINE void XMC_CCU4_SLICE_EnableMultiChannelMode(XMC_CCU4_SLICE_t *const slice){j XMC_ASSERT("XMC_CCU4_SLICE_EnableMultiChannelMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));/ slice->TC |= (uint32_t) CCU4_CC4_TC_MCME_Msk;}/**- * @param slice Constant pointer to CC4 Slice * @return
 * None
 * * \parDescription:
E * Disables the multichannel mode, by clearing CC4yTC.MCME bit.
\n= * This would return the slices to the normal operation mode. * * \parRelated APIs:
, * XMC_CCU4_SLICE_EnableMultiChannelMode(). */Z__STATIC_INLINE void XMC_CCU4_SLICE_DisableMultiChannelMode(XMC_CCU4_SLICE_t *const slice){k XMC_ASSERT("XMC_CCU4_SLICE_DisableMultiChannelMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));2 slice->TC &= ~((uint32_t) CCU4_CC4_TC_MCME_Msk);}/**0 * @param module Constant pointer to CCU4 moduleN * @param slice_mode_msk Slices for which the configuration has to be applied.n * Use ::XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_t enum items to create a mask of choice,= * using a bit wise OR operation. * @return
 * None
 * * \parDescription:
r * Enables the Multi-channel shadow transfer request trigger signal either by software or hardware by configuring L * GCTRL.MSE0, GCTRL.MSE1, GCTRL.MSE2, and GCTRL.MSE3 based on the mask.\n\nj * The shadow transfer would take place either if it was requested by software or by the CCU4x.MCSS input. * * \parRelated APIs:
* None.*/pvoid XMC_CCU4_SetMultiChannelShadowTransferMode(XMC_CCU4_MODULE_t *const module, const uint32_t slice_mode_msk);/**- * @param slice Constant pointer to CC4 SliceW * @param reg_num The capture register from which the captured value is to be retrieved * Range: [0,3] * @return
3 * uint32_t Returns the Capture register value.& * Range: [0 to 0x1FFFFF] * * \parDescription:
v * Retrieves timer value which has been captured in the Capture registers, by reading CC4yCV[\b reg_num] register.\n\nv * The signal whose timing characteristics are to be measured must be mapped to an event which in turn must be mapped w * to the capture function. Based on the capture criteria, the timer values are captured into capture registers. Timingv * characteristics of the input signal may then be derived/inferred from the captured values. The full flag will help 8 * to find out if there is a new captured value present. * * \parRelated APIs:
/ * XMC_CCU4_SLICE_GetLastCapturedTimerValue(). */luint32_t XMC_CCU4_SLICE_GetCaptureRegisterValue(const XMC_CCU4_SLICE_t *const slice, const uint8_t reg_num);/**- * @param slice Constant pointer to CC4 Slice@ * @param set The capture register set, which must be evaluatedc * @param val_ptr Out Parameter of the API.Stores the captured timer value into this out parameter. * @return
n * ::XMC_CCU4_STATUS_t Returns XMC_CCU4_STATUS_OK if there was new value present in the capture registers.n * returns XMC_CCU4_STATUS_ERROR if there was no new value present in the capture registers. * * \parDescription:
N * Retrieves the latest captured timer value, by reading CC4yCV registers.\n\n\ * Retrieve the timer value last stored by the slice. When separate capture events are used,t * users must specify the capture set to evaluate. If single capture event mode is used, all 4 capture registers are * evaluated.\ns * The lowest register is evaluated first followed by the next higher ordered register and this continues until all) * capture registers have been evaluated. * * \parRelated APIs:
- * XMC_CCU4_SLICE_GetCaptureRegisterValue(). */_XMC_CCU4_STATUS_t XMC_CCU4_SLICE_GetLastCapturedTimerValue(const XMC_CCU4_SLICE_t *const slice,b const XMC_CCU4_SLICE_CAP_REG_SET_t set,N uint32_t *val_ptr);/**- * @param slice Constant pointer to CC4 SliceJ * @param event Event whose assertion can potentially lead to an interrupt * @return
 * None
 * * \parDescription:
d * Enables the generation of an interrupt pulse for the event, by configuring CC4yINTE register.\n\nx * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The correspondingu * NVIC node must be enabled as well. This API merely enables the event. Binding with SR is performed by another API. * * \parRelated APIs:
u * XMC_CCU4_SLICE_SetInterruptNode()
XMC_CCU4_SLICE_EnableMultipleEvents()
XMC_CCU4_SLICE_DisableEvent()
+ * XMC_CCU4_SLICE_DisableMultipleEvents(). */N__STATIC_INLINE void XMC_CCU4_SLICE_EnableEvent(XMC_CCU4_SLICE_t *const slice,T const XMC_CCU4_SLICE_IRQ_ID_t event){_ XMC_ASSERT("XMC_CCU4_SLICE_EnableEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));c XMC_ASSERT("XMC_CCU4_SLICE_EnableEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event));6 slice->INTE |= ((uint32_t) 1) << ((uint32_t) event);}/**- * @param slice Constant pointer to CC4 SliceH * @param intr_mask Event mask such that multiple events can be enabled.^ * Use ::XMC_CCU4_SLICE_MULTI_IRQ_ID_t enum items to create a mask of choice,2 * using a bit wise OR operation. * @return
 * None
 * * \parDescription:
n * Enables the generation of an interrupt pulse for the required events, by configuring CC4yINTE register.\n\nx * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The correspondingv * NVIC node must be enabled as well. This API merely enables the events. Binding with SR is performed by another API. * * \parRelated APIs:
l * XMC_CCU4_SLICE_SetInterruptNode()
XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_DisableEvent()
+ * XMC_CCU4_SLICE_DisableMultipleEvents(). */q__STATIC_INLINE void XMC_CCU4_SLICE_EnableMultipleEvents(XMC_CCU4_SLICE_t *const slice, const uint16_t intr_mask){h XMC_ASSERT("XMC_CCU4_SLICE_EnableMultipleEvents:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));% slice->INTE |= (uint32_t)intr_mask;}/**- * @param slice Constant pointer to CC4 SliceJ * @param event Event whose assertion can potentially lead to an interrupt * @return
 * None
 * * \parDescription:
b * Disables the generation of an interrupt pulse for the event, by clearing CC4yINTE register.\n\n) * Prevents the event from being asserted * * \parRelated APIs:
t * XMC_CCU4_SLICE_SetInterruptNode()
XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_EnableMultipleEvents()
+ * XMC_CCU4_SLICE_DisableMultipleEvents(). */O__STATIC_INLINE void XMC_CCU4_SLICE_DisableEvent(XMC_CCU4_SLICE_t *const slice,U const XMC_CCU4_SLICE_IRQ_ID_t event){` XMC_ASSERT("XMC_CCU4_SLICE_DisableEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));d XMC_ASSERT("XMC_CCU4_SLICE_DisableEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event));9 slice->INTE &= ~(((uint32_t) 1) << ((uint32_t) event));}/**- * @param slice Constant pointer to CC4 SliceC * @param mask Event mask such that multiple events can be enabled.Y * Use ::XMC_CCU4_SLICE_MULTI_IRQ_ID_t enum items to create a mask of choice,- * using a bit wise OR operation. * @return
 * None
 * * \parDescription:
m * Disables the generation of an interrupt pulse for the required events, by clearing CC4yINTE register.\n\n> * Prevents selected events of the slice from being asserted. * * \parRelated APIs:
t * XMC_CCU4_SLICE_SetInterruptNode()
XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_EnableMultipleEvents()
" * XMC_CCU4_SLICE_DisableEvent(). */m__STATIC_INLINE void XMC_CCU4_SLICE_DisableMultipleEvents(XMC_CCU4_SLICE_t *const slice, const uint16_t mask){i XMC_ASSERT("XMC_CCU4_SLICE_DisableMultipleEvents:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));$ slice->INTE &= ~((uint32_t) mask);}/**- * @param slice Constant pointer to CC4 SliceJ * @param event Event whose assertion can potentially lead to an interrupt * @return
 * None
 * * \parDescription:
I * Manually asserts the requested event, by setting CC4ySWS register.\n\nx * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The correspondingT * NVIC node must be enabled as well. This API manually asserts the requested event. * * \parRelated APIs:
q * XMC_CCU4_SLICE_SetInterruptNode()
XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_EnableMultipleEvents(). */p__STATIC_INLINE void XMC_CCU4_SLICE_SetEvent(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_IRQ_ID_t event){\ XMC_ASSERT("XMC_CCU4_SLICE_SetEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));` XMC_ASSERT("XMC_CCU4_SLICE_SetEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event));5 slice->SWS |= ((uint32_t) 1) << ((uint32_t) event);}/**- * @param slice Constant pointer to CC4 Slice: * @param event Asserted event which must be acknowledged. * @return
 * None
 * * \parDescription:
U * Acknowledges an asserted event, by setting CC4ySWR with respective event flag.\n\n * * \parRelated APIs:
] * XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_SetEvent()
XMC_CCU4_SLICE_GetEvent(). */r__STATIC_INLINE void XMC_CCU4_SLICE_ClearEvent(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_IRQ_ID_t event){^ XMC_ASSERT("XMC_CCU4_SLICE_ClearEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));b XMC_ASSERT("XMC_CCU4_SLICE_ClearEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event));5 slice->SWR |= ((uint32_t) 1) << ((uint32_t) event);}/**- * @param slice Constant pointer to CC4 Slice3 * @param event Event to be evaluated for assertion * @return
E * bool Returns true if event is set else false is returned. * * \parDescription:
S * Evaluates if a given event is asserted or not, by reading CC4yINTS register.\n\nP * Return true if the event is asserted. For a event to be asserted it has to beN * first enabled. Only if that event is enabled the call to this API is valid.M * If the Event is enabled and has not yet occurred then a false is returned. * * \parRelated APIs:
? * XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_SetEvent(). */v__STATIC_INLINE bool XMC_CCU4_SLICE_GetEvent(const XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_IRQ_ID_t event){\ XMC_ASSERT("XMC_CCU4_SLICE_GetEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));` XMC_ASSERT("XMC_CCU4_SLICE_GetEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event));M return(((uint32_t)(slice->INTS & ((uint32_t)1 << (uint32_t)event))) != 0U);}/**- * @param slice Constant pointer to CC4 SliceC * @param event Event which must be bound to a service request lineD * @param sr The Service request line which is bound to the \b event * @return
 * None
 * * \parDescription:
n * Binds requested event to a service request line, by configuring CC4ySRS register with respective event.\n\nx * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The correspondingx * NVIC node must be enabled as well. This API binds the requested event with the requested service request line(\b sr). * * \parRelated APIs:
? * XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_SetEvent(). */Cvoid XMC_CCU4_SLICE_SetInterruptNode(XMC_CCU4_SLICE_t *const slice,I const XMC_CCU4_SLICE_IRQ_ID_t event,F const XMC_CCU4_SLICE_SR_ID_t sr);% /**- * @param slice Constant pointer to CC4 Slice* * @param level Slice output passive level * @return
 * None
 * * \parDescription:
V * Configures the passive level for the slice output, by setting CC4yPSL register.\n\na * Defines the passive level for the timer slice output pin. Selects either level high is passivei * or level low is passive. This is the level of the output before the compare match is value changes it. * * \parRelated APIs:
? * XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_SetEvent(). */Bvoid XMC_CCU4_SLICE_SetPassiveLevel(XMC_CCU4_SLICE_t *const slice,W const XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t level);N#if defined(CCU4V3) || defined(DOXYGEN) /* Defined for XMC1400 devices only *//**- * @param slice Constant pointer to CC4 Slice * * @return
 * None
 * * \parDescription:
s * Cascades the shadow transfer operation throughout the CCU4 timer slices, by setting CSE bit in STC register.\n\n *y * The shadow transfer enable bits needs to be set in all timer slices, that are being used in the cascaded architecture,v * at the same time. The shadow transfer enable bits, also need to be set for all slices even if the shadow values of m * some slices were not updated. It is possible to to cascade with the adjacent slices only. CC40 slice is a ! * master to start the operation. *  * \parNote:
x * XMC_CCU4_EnableShadowTransfer() must be called to enable the shadow transfer of the all the slices, which needs to be * cascaded. *  * \parRelated APIs:
X * XMC_CCU4_EnableShadowTransfer(), XMC_CCU4_SLICE_DisableCascadedShadowTransfer()
.+ * @note Only available for XMC1400 series */___STATIC_INLINE void XMC_CCU4_SLICE_EnableCascadedShadowTransfer(XMC_CCU4_SLICE_t *const slice){p XMC_ASSERT("XMC_CCU4_SLICE_EnableCascadedShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));0 slice->STC |= (uint32_t) CCU4_CC4_STC_CSE_Msk;}/**- * @param slice Constant pointer to CC4 Slice * * @return
 * None
 * * \parDescription:
` * Disables the cascaded the shadow transfer operation, by clearing CSE bit in STC register.\n\n *{ * If in any slice the cascaded mode disabled, other slices from there onwards does not update the values in cascaded mode. *  * \parRelated APIs:
6 * XMC_CCU4_SLICE_EnableCascadedShadowTransfer()
.+ * @note Only available for XMC1400 series */`__STATIC_INLINE void XMC_CCU4_SLICE_DisableCascadedShadowTransfer(XMC_CCU4_SLICE_t *const slice){q XMC_ASSERT("XMC_CCU4_SLICE_DisableCascadedShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));1 slice->STC &= ~(uint32_t) CCU4_CC4_STC_CSE_Msk;}/**- * @param slice Constant pointer to CC4 Slice4 * @param shadow_transfer_mode mode to be configuredJ * Use :: XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t enum items for mode * @return
 * None
 * * \parDescription:
\ * Configures when the shadow transfer has to occur, by setting STM bit in STC register.\n\n * w * After requesting for shadow transfer mode using XMC_CCU4_EnableShadowTransfer(), actual transfer occurs based on thej * selection done using this API (i.e. on period and One match, on Period match only, on One match only).  * * \parNote:
I * This is effective when the timer is configured in centre aligned mode. *  * \parRelated APIs:
& * XMC_CCU4_EnableShadowTransfer()
+ * @note Only available for XMC1400 series*/X__STATIC_INLINE void XMC_CCU4_SLICE_SetShadowTransferMode(XMC_CCU4_SLICE_t *const slice,{ const XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t shadow_transfer_mode){i XMC_ASSERT("XMC_CCU4_SLICE_SetShadowTransferMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));o slice->STC = ((slice->STC) & ~(uint32_t)((uint32_t)CCU4_CC4_STC_STM_Msk << (uint32_t)CCU4_CC4_STC_STM_Pos)) |a ((shadow_transfer_mode << CCU4_CC4_STC_STM_Pos) & (uint32_t)CCU4_CC4_STC_STM_Msk);} /**- * @param slice Constant pointer to CC4 SliceN * @param coherent_write specifies for what fields this mode has to be appliedr * Use :: XMC_CCU4_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. * @return
 * None
 * * \parDescription:
x * Configures the specified fields shadow value to be updated in synchronous with PWM after shadow transfer request, by J * clearing IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n * v * When coherent shadow is enabled, after calling XMC_CCU4_EnableShadowTransfer(), the value which are written in the x * respective shadow registers get updated according the configuration done using XMC_CCU4_SLICE_SetShadowTransferMode() * API. \parNote:
 *  * \parRelated APIs:
N * XMC_CCU4_EnableShadowTransfer(), XMC_CCU4_SLICE_SetShadowTransferMode()
* * @note Only available for XMC1400 series */^__STATIC_INLINE void XMC_CCU4_SLICE_WriteCoherentlyWithPWMCycle(XMC_CCU4_SLICE_t *const slice,^ const uint32_t coherent_write){o XMC_ASSERT("XMC_CCU4_SLICE_WriteCoherentlyWithPWMCycle:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));* slice->STC &= ~(uint32_t)coherent_write;} /**- * @param slice Constant pointer to CC4 SliceO * @param immediate_write specifies for what fields this mode has to be appliedr * Use :: XMC_CCU4_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. * @return
 * None
 * * \parDescription:
t * Configures the specified fields shadow value to be updated immediately after shadow transfer request, by setting A * IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n * s * When immediate shadow is enabled, by calling XMC_CCU4_EnableShadowTransfer() the value which are written in the Y * shadow registers get updated to the actual registers immediately. \parNote:
 *  * \parRelated APIs:
& * XMC_CCU4_EnableShadowTransfer()
+ * @note Only available for XMC1400 series */d__STATIC_INLINE void XMC_CCU4_SLICE_WriteImmediateAfterShadowTransfer(XMC_CCU4_SLICE_t *const slice,e const uint32_t immediate_write){u XMC_ASSERT("XMC_CCU4_SLICE_WriteImmediateAfterShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); slice->STC |= immediate_write;} /**- * @param slice Constant pointer to CC4 Slicev * @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request is generatedu * Use :: XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a ' * bit wise OR operation. * @return
 * None
 * * \parDescription:
x * Configure on which shadow register update, automatic shadow transfer request generation has to be enabled. By settingA * ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n * { * By updating the configured shadow register, the shadow transfer request is generated to update all the shadow registers. * \parNote:
 *  * \parRelated APIs:
; * XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest().+ * @note Only available for XMC1400 series */g__STATIC_INLINE void XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest(XMC_CCU4_SLICE_t *const slice,r const uint32_t automatic_shadow_transfer){x XMC_ASSERT("XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));* slice->STC |= automatic_shadow_transfer;} /**- * @param slice Constant pointer to CC4 Slicew * @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request should not be- * generatedu * Use :: XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a ' * bit wise OR operation. * @return
 * None
 * * \parDescription:
r * Configure on which shadow register update, automatic shadow transfer request generation has to be disabled. By J * clearing ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n * g * This disables the generation of automatic shadow transfer request for the specified register update. * \parNote:
 *  * \parRelated APIs:
: * XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest().+ * @note Only available for XMC1400 series */h__STATIC_INLINE void XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest(XMC_CCU4_SLICE_t *const slice,s const uint32_t automatic_shadow_transfer){y XMC_ASSERT("XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));5 slice->STC &= ~(uint32_t)automatic_shadow_transfer;}#endif#ifdef __cplusplus}#endif /** * @} */ /** * @} */ #endif /* defined(CCU40) */#endif /* CCU4_H */ xmc_gpio.hÝ/** * @file xmc_gpio.h * @date 2015-06-20 * * @condw *********************************************************************************************************************1 * XMClib v2.1.6 - XMC Peripheral Driver Library  *4 * Copyright (c) 2015-2016, Infineon Technologies AG/ * All rights reserved. / * s * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the # * following conditions are met: P * t * Redistributions of source code must retain the above copyright notice, this list of conditions and the following & * disclaimer.  * w * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following p * disclaimer in the documentation and/or other materials provided with the distribution.  * q * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote | * products derived from this software without specific prior written permission. P * v * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, v * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE w * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, t * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR u * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, w * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE y * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. P * w * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with i * Infineon Technologies AG dave@infineon.com). v ********************************************************************************************************************* * * Change History * -------------- * * 2015-02-20: * - Initial draft
$ * - Documentation improved
 *  * 2015-06-20:G * - Removed version macros and declaration of GetDriverVersion API * * @endcond * */#ifndef XMC_GPIO_H#define XMC_GPIO_Hw/********************************************************************************************************************** * HEADER FILESw *********************************************************************************************************************/#include "xmc_common.h"/**, * @addtogroup XMClib XMC Peripheral Library * @{ *//** * @addtogroup GPIOX * @brief General Purpose Input Output (GPIO) driver for the XMC microcontroller family. *n * GPIO driver provide a generic and very flexible software interface for all standard digital I/O port pins. r * Each port slice has individual interfaces for the operation as General Purpose I/O and it further provides the V * connectivity to the on-chip periphery and the control for the pad characteristics.  *4 * The driver is divided into Input and Output mode. * * Input mode features:[ * -# Configuration structure XMC_GPIO_CONFIG_t and initialization function XMC_GPIO_Init()ˆ * -# Allows the selection of weak pull-up or pull-down device. Configuration structure XMC_GPIO_MODE_t and function XMC_GPIO_SetMode() * \if XMC1M * -# Allows the selection of input hysteresis. XMC_GPIO_SetInputHysteresis() * \endif * *  * Output mode features:‘ * -# Allows the selection of push pull/open drain and Alternate output. Configuration structure XMC_GPIO_MODE_t and function XMC_GPIO_SetMode() * \if XMC4 * -# Allows the selection of pad driver strength. Configuration structure XMC_GPIO_OUTPUT_STRENGTH_t and function XMC_GPIO_SetOutputStrength() * \endif *Š * -# Allows the selection of initial output level. Configuration structure XMC_GPIO_OUTPUT_LEVEL_t and function XMC_GPIO_SetOutputLevel() * *@{ */ w/********************************************************************************************************************** * MACROSw *********************************************************************************************************************/,#define PORT_IOCR_PC_Pos PORT0_IOCR0_PC0_Pos,#define PORT_IOCR_PC_Msk PORT0_IOCR0_PC0_Msk"#define PORT_IOCR_PC_Size (8U) U#define XMC_GPIO_CHECK_OUTPUT_LEVEL(level) ((level == XMC_GPIO_OUTPUT_LEVEL_LOW) || \R (level == XMC_GPIO_OUTPUT_LEVEL_HIGH)), P#define XMC_GPIO_CHECK_HWCTRL(hwctrl) ((hwctrl == XMC_GPIO_HWCTRL_DISABLED) || \S (hwctrl == XMC_GPIO_HWCTRL_PERIPHERAL1) || \t (hwctrl == XMC_GPIO_HWCTRL_PERIPHERAL2)) , w/********************************************************************************************************************** * ENUMSw *********************************************************************************************************************//**T * Defines output level of a pin. Use type \a XMC_GPIO_OUTPUT_LEVEL_t for this enum. */"typedef enum XMC_GPIO_OUTPUT_LEVEL{; XMC_GPIO_OUTPUT_LEVEL_LOW = 0x10000U, /**< Reset bit */6 XMC_GPIO_OUTPUT_LEVEL_HIGH = 0x1U, /**< Set bit */} XMC_GPIO_OUTPUT_LEVEL_t;/**l * Defines direct hardware control characteristics of the pin . Use type \a XMC_GPIO_HWCTRL_t for this enum. */typedef enum XMC_GPIO_HWCTRL{E XMC_GPIO_HWCTRL_DISABLED = 0x0U, /**< Software control only */n XMC_GPIO_HWCTRL_PERIPHERAL1 = 0x1U, /**< HWI0/HWO0 control path can override the software configuration */n XMC_GPIO_HWCTRL_PERIPHERAL2 = 0x2U /**< HWI1/HWO1 control path can override the software configuration */} XMC_GPIO_HWCTRL_t;w/********************************************************************************************************************** * DEVICE FAMILY EXTENSIONSw *********************************************************************************************************************/ #if UC_FAMILY == XMC1#include "xmc1_gpio.h"#elif UC_FAMILY == XMC4#include "xmc4_gpio.h"#else0#error "xmc_gpio.h: family device not supported"#endifw/********************************************************************************************************************** * API PROTOTYPESw *********************************************************************************************************************/#ifdef __cplusplus extern "C" {#endif/**r * @param port Constant pointer pointing to GPIO port, to access port registers like Pn_OUT,Pn_OMR,Pn_IOCR etc.! * @param pin Port pin number.m * @param config GPIO configuration data structure. Refer data structure @ref XMC_GPIO_CONFIG_t for details. * * @return None * * \parDescription:
* \if XMC1p * Initializes input / output mode settings like, pull up / pull down devices,hysteresis, push pull /open drain.t * Also configures alternate function outputs and clears hardware port control for a selected \a port \a and \a pin.z * \a config provides selected I/O settings. It configures hardware registers Pn_IOCR,Pn_OUT, Pn_OMR,Pn_PDISC and Pn_PHCR. * \endif * \if XMC4y * Initializes input / output mode settings like, pull up / pull down devices,push pull /open drain, and pad driver mode.p * Also configures alternate function outputs and clears hardware port control for selected \a port and \a pin .P * It configures hardware registers Pn_IOCR,Pn_OUT,Pn_OMR,Pn_PDISC and Pn_PDR.\n * \endif * * \parRelated APIs:
 * None * * \parNote:
q * This API is called in definition of DAVE_init by code generation and therefore should not be explicitly calledv * for the normal operation. Use other APIs only after DAVE_init is called successfully (returns DAVE_STATUS_SUCCESS). * * */ jvoid XMC_GPIO_Init(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_CONFIG_t *const config); /** *\ * @param port Constant pointer pointing to GPIO port, to access hardware register Pn_IOCR. * @param pin Port pin number.d * @param mode input / output functionality selection. Refer @ref XMC_GPIO_MODE_t for valid values. * * @return None * * \parDescription:
t * Sets digital input and output driver functionality and characteristics of a GPIO port pin. It configures hardwarev * registers Pn_IOCR. \a mode is initially configured during initialization in XMC_GPIO_Init(). Call this API to alterC * the port direction functionality as needed later in the program. * * \parRelated APIs:
 * None * */bvoid XMC_GPIO_SetMode(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_MODE_t mode);/** *\ * @param port Constant pointer pointing to GPIO port, to access hardware register Pn_OMR. * @param pin Port pin number.] * @param level output level selection. Refer @ref XMC_GPIO_OUTPUT_LEVEL_t for valid values. * * @return None * * \parDescription:
i * Set port pin output level to high or low.It configures hardware registers Pn_OMR.\a level is initially{ * configured during initialization in XMC_GPIO_Init(). Call this API to alter output level as needed later in the program. * * \parRelated APIs:
6 * XMC_GPIO_SetOutputHigh(), XMC_GPIO_SetOutputLow(). * * \parNote:
] * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). * */__STATIC_INLINE void XMC_GPIO_SetOutputLevel(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_OUTPUT_LEVEL_t level){X XMC_ASSERT("XMC_GPIO_SetOutputLevel: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port));b XMC_ASSERT("XMC_GPIO_SetOutputLevel: Invalid output level", XMC_GPIO_CHECK_OUTPUT_LEVEL(level)); % port->OMR = (uint32_t)level << pin;}/**[ * @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR. * @param pin Port pin number. * * @return None * * \parDescription:
J * Sets port pin output to high. It configures hardware registers Pn_OMR. * * \parRelated APIs:
 * XMC_GPIO_SetOutputLow() * * \parNote:
_ * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode().\nh * Register Pn_OMR is virtual and does not contain any flip-flop. A read action delivers the value of 0. * */[__STATIC_INLINE void XMC_GPIO_SetOutputHigh(XMC_GPIO_PORT_t *const port, const uint8_t pin){W XMC_ASSERT("XMC_GPIO_SetOutputHigh: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port));$ port->OMR = (uint32_t)0x1U << pin;}/** *[ * @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR. * @param pin port pin number. * * @return None * *\parDescription:
J * Sets port pin output to low. It configures hardware registers Pn_OMR.\n * * \parRelated APIs:
> * XMC_GPIO_SetOutputHigh() * *\parNote:
] * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode().j * Register Pn_OMR is virtual and does not contain any flip-flop. A read action delivers the value of 0.\n * */Z__STATIC_INLINE void XMC_GPIO_SetOutputLow(XMC_GPIO_PORT_t *const port, const uint8_t pin){V XMC_ASSERT("XMC_GPIO_SetOutputLow: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); port->OMR = 0x10000U << pin;}/** *Z * @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR. * @param pin port pin number. * * @return None * * \parDescription:
Q * Configures port pin output to Toggle. It configures hardware registers Pn_OMR. * * \parRelated APIs:
5 * XMC_GPIO_SetOutputHigh(), XMC_GPIO_SetOutputLow(). * * \parNote:
x * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). Register Pn_OMR is virtualM * and does not contain any flip-flop. A read action delivers the value of 0. * */Z__STATIC_INLINE void XMC_GPIO_ToggleOutput(XMC_GPIO_PORT_t *const port, const uint8_t pin){V XMC_ASSERT("XMC_GPIO_ToggleOutput: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); port->OMR = 0x10001U << pin;}/** *Y * @param port constant pointer pointing to GPIO port, to access hardware register Pn_IN. * @param pin Port pin number. *+ * @return uint32_t pin logic level status. * *\parDescription:
R * Reads the Pn_IN register and returns the current logical value at the GPIO pin. * * \parRelated APIs:
 * None * * \parNote:
\ * Prior to this api, user has to configure port pin to input mode using XMC_GPIO_SetMode(). * */Z__STATIC_INLINE uint32_t XMC_GPIO_GetInput(XMC_GPIO_PORT_t *const port, const uint8_t pin){K XMC_ASSERT("XMC_GPIO_GetInput: Invalid port", XMC_GPIO_CHECK_PORT(port));& return (((port->IN) >> pin) & 0x1U);}/**Z * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PPS. * @param pin port pin number. * * @return None * * \parDescription:
u * Enables pin power save mode and configures Pn_PPS register.This configuration is useful when the controller entersx * Deep Sleep mode.Port pin enabled with power save mode option are set to a defined state and the input Schmitt-Triggerv * as well as the output driver stage are switched off. By default port pin does not react to power save mode request. * * \parRelated APIs:
" * XMC_GPIO_DisablePowerSaveMode() * * Note:
u * Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). Doing so^ * may result in an undefined behavior of the pin when the device enters the Deep Sleep state. * */a__STATIC_INLINE void XMC_GPIO_EnablePowerSaveMode(XMC_GPIO_PORT_t *const port, const uint8_t pin){V XMC_ASSERT("XMC_GPIO_EnablePowerSaveMode: Invalid port", XMC_GPIO_CHECK_PORT(port));% port->PPS |= (uint32_t)0x1U << pin;}/** *Z * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PPS. * @param pin port pin number. * * @return None * * \parDescription:
v * Disables pin power save mode and configures Pn_PPS register.This configuration is useful when the controller enterst * Deep Sleep mode. This configuration enables input Schmitt-Trigger and output driver stage(if pin is enabled power[ * save mode previously). By default port \a pin does not react to power save mode request. * * \parRelated APIs:
" * XMC_GPIO_EnablePowerSaveMode() * *\parNote:
u * Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). Doing so^ * may result in an undefined behavior of the pin when the device enters the Deep Sleep state. * */b__STATIC_INLINE void XMC_GPIO_DisablePowerSaveMode(XMC_GPIO_PORT_t *const port, const uint8_t pin){W XMC_ASSERT("XMC_GPIO_DisablePowerSaveMode: Invalid port", XMC_GPIO_CHECK_PORT(port));2 port->PPS &= ~(uint32_t)((uint32_t)0x1U << pin);}/**] * @param port constant pointer pointing to GPIO port, to access hardware register Pn_HWSEL. * @param pin port pin number.b * @param hwctrl direct hardware control selection. Refer @ref XMC_GPIO_HWCTRL_t for valid values. * * @return None * * \parDescription:
s * Selects direct hard ware control and configures Pn_HWSEL register.This configuration is useful for the port pins` * overlaid with peripheral functions for which the connected peripheral needs hardware control. * * \parRelated APIs:
 * None * *\parNote:
l * Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B).g * Doing so may result in an undefined behavior of the pin when the device enters the Deep Sleep state. * */qvoid XMC_GPIO_SetHardwareControl(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_HWCTRL_t hwctrl);/**\ * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PDISC. * @param pin port pin number. * * @return None * * \parRelated APIs:
 * None * * \parDescription:
w * Enable digital input path for analog pins and configures Pn_PDISC register.This configuration is applicable only for * analog port pins. * */`__STATIC_INLINE void XMC_GPIO_EnableDigitalInput(XMC_GPIO_PORT_t *const port, const uint8_t pin){c XMC_ASSERT("XMC_GPIO_EnableDigitalInput: Invalid analog port", XMC_GPIO_CHECK_ANALOG_PORT(port)); 4 port->PDISC &= ~(uint32_t)((uint32_t)0x1U << pin);}/**] * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PDISC. * @param pin port pin number. * * @return None * * \parRelated APIs:
 * None * * \parDescription:
t * Disable digital input path for analog pins and configures Pn_PDISC register.This configuration is applicable only * for analog port pins. * */a__STATIC_INLINE void XMC_GPIO_DisableDigitalInput(XMC_GPIO_PORT_t *const port, const uint8_t pin){c XMC_ASSERT("XMC_GPIO_EnableDigitalInput: Invalid analog port", XMC_GPIO_CHECK_ANALOG_PORT(port)); ' port->PDISC |= (uint32_t)0x1U << pin;}#ifdef __cplusplus}#endif/** * @} (end addtogroup GPIO) *//** * @} (end addtogroup XMClib) */#endif /* XMC_GPIO_H */ xmc_scu.hV/** * @file xmc_scu.h * @date 2016-03-09 * * @condv *********************************************************************************************************************1 * XMClib v2.1.6 - XMC Peripheral Driver Library  *4 * Copyright (c) 2015-2016, Infineon Technologies AG/ * All rights reserved. / * s * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the # * following conditions are met: P * t * Redistributions of source code must retain the above copyright notice, this list of conditions and the following & * disclaimer.  * w * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following p * disclaimer in the documentation and/or other materials provided with the distribution.  * q * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote | * products derived from this software without specific prior written permission. P * v * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, v * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE w * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, t * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR u * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, w * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE y * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. P * w * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with i * Infineon Technologies AG dave@infineon.com). v ********************************************************************************************************************* * * Change History * -------------- * * 2015-02-20: * - Initial
 * * 2015-05-20:$ * - Documentation improved
F * - XMC_ASSERT() hanging issues have fixed for XMC4 devices.
 * * 2015-06-20:G * - Removed version macros and declaration of GetDriverVersion APIO * - Removed STATIC_INLINE property for the below APIs and declared as voidG * XMC_SCU_INTERRUPT_EnableEvent, XMC_SCU_INTERRUPT_DisableEvent,I * XMC_SCU_INTERRUPT_TriggerEvent, XMC_SCU_INTERUPT_GetEventStatus,* * XMC_SCU_INTERUPT_ClearEventStatus * * 2015-11-30:$ * - Documentation improved
 *  * 2016-03-09:- * - Optimization of write only registers * * @endcond  * */#ifndef XMC_SCU_H#define XMC_SCU_H v/********************************************************************************************************************* * HEADER FILESv ********************************************************************************************************************/#include /**, * @addtogroup XMClib XMC Peripheral Library * @{ */ /** * @addtogroup SCUI * @brief System Control Unit(SCU) driver for XMC microcontroller family. *d * System control unit is the SoC power, reset and a clock manager with additional responsibility ofK * providing system stability protection and other auxiliary functions.
' * SCU provides the following features, * -# Power control \if XMC4  * -# Hibernate control  \endif * -# Reset control * -# Clock controlF * -# Miscellaneous control(boot mode, system interrupts etc.)

 *k * The SCU driver is divided in to clock control logic, reset control logic, system interrupt control logic \if XMC4G * , hibernate control logic, trap control logic, parity control logic  \endif' * and miscellaneous control logic.
 * * Clock driver features:h * -# Allows clock configuration using the structure XMC_SCU_CLOCK_CONFIG_t and API XMC_SCU_CLOCK_Init() \if XMC4U * -# Provides structure XMC_SCU_CLOCK_SYSPLL_CONFIG_t for configuring the system PLL^ * -# Allows selection of clock source for system PLL, XMC_SCU_CLOCK_GetSystemPllClockSource() * -# Provides APIs for configuring different module clock frequencies XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_SetUsbClockDivider()h * -# Allows selection of clock source for external output, XMC_SCU_CLOCK_SetExternalOutputClockSource()¹ * -# Provides APIs for enabling external high power oscillator and ultra low power oscillator, XMC_SCU_CLOCK_EnableHighPerformanceOscillator(), XMC_SCU_CLOCK_EnableLowPowerOscillator()g * -# Provides APIs for getting various clock frequencies XMC_SCU_CLOCK_GetPeripheralClockFrequency(), R XMC_SCU_CLOCK_GetCpuClockFrequency(), XMC_SCU_CLOCK_GetSystemClockFrequency()
 \endif \if XMC1b * -# Allows selection of peripheral clock frequency, XMC_SCU_CLOCK_SetFastPeripheralClockSource()i * -# Provides API to get the peripheral clock frequency, XMC_SCU_CLOCK_GetFastPeripheralClockFrequency() \endif * * Reset driver features: \if XMC4v * -# Allows to handle peripheral reset XMC_SCU_RESET_AssertPeripheralReset(), XMC_SCU_RESET_DeassertPeripheralReset()f * -# Allows configuration of NMI generation for selected events, XMC_SCU_INTERRUPT_EnableNmiRequest() \endif \if XMC1F * -# Allows to trigger device reset XMC_SCU_RESET_AssertMasterReset()X * -# Allows to configure multiple sources for reset, XMC_SCU_RESET_EnableResetRequest() \endif
 * * Interrupt driver features:h * -# Provides APIs for enabling/ disabling interrupt event generation XMC_SCU_INTERRUPT_EnableEvent(), ! XMC_SCU_INTERRUPT_DisableEvent()g * -# Provides API for registering callback function for events XMC_SCU_INTERRUPT_SetEventHandler()
 * \if XMC4 * Hibernate driver features:x * -# Allows configuration of hibernate domain XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_HIB_DisableHibernateDomain()S * -# Allows selection of standby clock source, XMC_SCU_HIB_SetStandbyClockSource()K * -# Allows selection of RTC clock source, XMC_SCU_HIB_SetRtcClockSource()t * -# Provides API for enabling slow internal clock used for backup clock, XMC_SCU_HIB_EnableInternalSlowClock()
 * * Trap driver features:i * -# Allows handling of trap XMC_SCU_TRAP_Enable(), XMC_SCU_TRAP_GetStatus(), XMC_SCU_TRAP_Trigger()
 * * Parity driver features:q * -# Parity error generated by on-chip RAM can be monitored, XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_GetStatus()q * -# Allows configuration of trap generation on detection of parity error, XMC_SCU_PARITY_EnableTrapGeneration() * * Power driver features:Z * -# Allows to power the USB module XMC_SCU_POWER_EnableUsb(), XMC_SCU_POWER_DisableUsb() \endif * * Miscellaneous features:v * -# Allows to trigger multiple capture compare unit(CCU) channels to be started together XMC_SCU_SetCcuTriggerHigh() \if XMC4a * -# Enables configuration of out of range comparator (ORC) XMC_SCU_EnableOutOfRangeComparator()} * -# Enables configuration of die temperature sensor XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor()I * -# Enables configuration of device boot mode XMC_SCU_SetBootMode()
 \endif \if XMC1p * -# Enables configuration of die temperature sensor XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits()| * -# Allows configuring supply monitor unit using the structure XMC_SCU_SUPPLYMONITOR_t and API XMC_SCU_SupplyMonitorInit()f * -# Allows handling of protected bits XMC_SCU_LockProtectedBits(), XMC_SCU_UnlockProtectedBits()
 \endif * @{ */ v/********************************************************************************************************************* * MACROSv ********************************************************************************************************************/v/********************************************************************************************************************* * ENUMSv ********************************************************************************************************************//**V * Defines the status of SCU API execution, used to verify the SCU related API calls. */typedef enum XMC_SCU_STATUS {Q XMC_SCU_STATUS_OK = 0UL, /**< SCU related operation successfully completed.*/{ XMC_SCU_STATUS_ERROR, /**< SCU related operation failed. When API cannot fulfill request, this value is returned. */Z XMC_SCU_STATUS_BUSY, /**< Cannot execute the SCU related operation request becausew another operation is in progress. \a XMC_SCU_STATUS_BUSY is returned when API is busy@ processing another request. */} XMC_SCU_STATUS_t;v/********************************************************************************************************************* * DATA TYPESv ********************************************************************************************************************//**Y * Function pointer type used for registering callback functions on SCU event occurrence. */8typedef void (*XMC_SCU_INTERRUPT_EVENT_HANDLER_t)(void);v/********************************************************************************************************************* * DEVICE EXTENSIONSv ********************************************************************************************************************/#if (UC_FAMILY == XMC1)#include #elif (UC_FAMILY == XMC4)#include #else#error "Unspecified chipset"#endifv/********************************************************************************************************************* * API Prototypesv ********************************************************************************************************************/#ifdef __cplusplus extern "C" {#endif/** *t * @param trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits2 * in the register CCUCON.
 * \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be 5 * combined using \a OR operation. * * @return None * * \parDescription
Z * Generates active edge(low to high) trigger for multiple CCU units at the same time.\n\nZ * Before executing this API, all the required CCU timers should configure external start.B * The edge of the start signal should be selected as active edge.F * The input signal for the CCU slice should be selected as SCU input.f * The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig(). Y * CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering * the timer using this API.
 * \parRelated APIs:
\ * XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerLow()\n\n\n */F__STATIC_INLINE void XMC_SCU_SetCcuTriggerHigh(const uint32_t trigger){+ SCU_GENERAL->CCUCON |= (uint32_t)trigger;}/** *r * @param trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits2 * in the register CCUCON.
 * \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be 5 * combined using \a OR operation. * * @return None * * \parDescription
[ * Generates passive edge(high to low) trigger for multiple CCU units at the same time.\n\nZ * Before executing this API, all the required CCU timers should configure external start.C * The edge of the start signal should be selected as passive edge.F * The input signal for the CCU slice should be selected as SCU input.f * The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig(). Y * CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering * the timer using this API.
 * \parRelated APIs:
] * XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerHigh()\n\n\n */E__STATIC_INLINE void XMC_SCU_SetCcuTriggerLow(const uint32_t trigger){, SCU_GENERAL->CCUCON &= (uint32_t)~trigger;}/** *` * @param config Pointer to structure holding the clock prescaler values and divider values for @ * configuring clock generators and clock tree.\nf * \b Range: Configure the members of structure @ref XMC_SCU_CLOCK_CONFIG_t for various, * parameters of clock setup. * * @return None * * \parDescription
3 * Initializes clock generators and clock tree.\n\n * \if XMC1_ * Peripheral clock and system clock are configured based on the input configuration \a config.a * The system clock frequency is tuned by configuring the FDIV and IDIV values of CLKCR register.N * The values of FDIV and IDIV can be provided as part of input configuration.R * The PCLK divider determines the ratio of peripheral clock to the system clock. D * The source of RTC clock is set based on the input configuration. @ * \a SystemCoreClock variable will be updated with the value ofQ * system clock frequency. Access to protected bit fields are handled internally. * \endif * \if XMC4p * Enables the high precision oscillator(fOHP) input and configures the system and peripheral clock frequencies.n * Based on the system clock source selected in \a config, either fPLL or fOFI will be chosen as system clock.g * Based on PLL mode(normal or prescaler mode) used, PLL ramps up in steps to achieve target frequency.f * The clock dividers for CPU, CCU and peripheral clocks will be set based on the input configuration.S * The \a SystemCoreClock variable is set with the value of system clock frequency. * \endif * \parRelated APIs:
[ * XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GetCpuClockFrequency() \n\n\n */Dvoid XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config);/** *c * @param event Bit mask of the event to enable. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_tk * for providing the input value. Multiple events can be combined using the \a OR operation. * * @return None * * \parDescription
@ * Enables the generation of interrupt for the input events.\n\nX * The events are enabled by setting the respective bit fields in the SRMSK register. \n` * Note: User should separately enable the NVIC node responsible for handling the SCU interrupt.D * The interrupt will be generated when the respective event occurs. * \parRelated APIs:
; * NVIC_EnableIRQ(), XMC_SCU_INTERRUPT_DisableEvent()\n\n\n */Jvoid XMC_SCU_INTERRUPT_EnableEvent(const XMC_SCU_INTERRUPT_EVENT_t event);/** *d * @param event Bit mask of the event to disable. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_tk * for providing the input value. Multiple events can be combined using the \a OR operation. * * @return None * * \parDescription
I * Disables generation of interrupt on occurrence of the input event.\n\n[ * The events are disabled by resetting the respective bit fields in the SRMSK register. \n * \parRelated APIs:
; * NVIC_DisableIRQ(), XMC_SCU_INTERRUPT_EnableEvent()\n\n\n */Kvoid XMC_SCU_INTERRUPT_DisableEvent(const XMC_SCU_INTERRUPT_EVENT_t event);/** *h * @param event Bit mask of the event to be triggered. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_tk * for providing the input value. Multiple events can be combined using the \a OR operation. * * @return None * * \parDescription
7 * Triggers the event as if the hardware raised it.\n\nV * Event will be triggered by setting the respective bitfield in the SRSET register.\ne * Note: User should enable the NVIC node that handles the respective event for interrupt generation. * \parRelated APIs:
c * NVIC_EnableIRQ(), XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_ClearEventStatus() \n\n\n */Lvoid XMC_SCU_INTERRUPT_TriggerEvent(const XMC_SCU_INTERRUPT_EVENT_t event);/**. * @return uint32_t Status of the SCU events. * * \parDescription
- * Provides the status of all SCU events.\n\nS * The status is read from the SRRAW register. To check the status of a particular Y * event, the returned value should be masked with the bit mask of the event. The bitmask\ * of events can be obtained using the type @ref XMC_SCU_INTERRUPT_EVENT_t. Multiple events'K * status can be checked by combining the bit masks using \a OR operation. j * After detecting the event, the event status should be cleared using software to detect the event again. * \parRelated APIs:
u * XMC_SCU_INTERRUPT_ClearEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n */@XMC_SCU_INTERRUPT_EVENT_t XMC_SCU_INTERUPT_GetEventStatus(void);/** *c * @param event Bit mask of the events to clear. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_tk * for providing the input value. Multiple events can be combined using the \a OR operation. * * @return None * * \parDescription
5 * Clears the event status bit in SRRAW register.\n\nZ * The events are cleared by writing value 1 to their bit positions in the SRCLR register._ * The API can be used when polling method is used. After detecting the event, the event status> * should be cleared using software to detect the event again. * * \parRelated APIs:
M * XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent() \n\n\n */Ovoid XMC_SCU_INTERRUPT_ClearEventStatus(const XMC_SCU_INTERRUPT_EVENT_t event);/** *E * @return uint32_t Status representing the reason for device reset. * * \parDescription
C * Provides the value representing the reason for device reset.\n\nx * The return value is an encoded word, which can indicate multiple reasons for the last reset. Each bit position of thet * returned word is representative of a last reset cause. The returned value should be appropriately masked to check * the cause of reset. < * The cause of the last reset gets automatically stored in J * the \a SCU_RSTSTAT register. The reset status shall be reset after eachP * startup in order to ensure consistent source indication after the next reset.f * \b Range: The type @ref XMC_SCU_RESET_REASON_t can be used to get the bit masks of the reset cause. * * \parRelated APIs:
0 * XMC_SCU_RESET_ClearDeviceResetReason() \n\n\n */A__STATIC_INLINE uint32_t XMC_SCU_RESET_GetDeviceResetReason(void){@ return ((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_RSTSTAT_Msk);}/** * @return None  * * \parDescription
B * Clears the reset reason bits in the reset status register. \n\nw * Clearing of the reset status information in the \a SCU_RSTSTAT register via register bit \a RSTCLR.RSCLR is stronglyG * recommended to ensure a clear indication of the cause of next reset. * * \parRelated APIs:
. * XMC_SCU_RESET_GetDeviceResetReason() \n\n\n */?__STATIC_INLINE void XMC_SCU_RESET_ClearDeviceResetReason(void){& /* Clear RSTSTAT.RSTSTAT bitfield */; SCU_RESET->RSTCLR = (uint32_t)SCU_RESET_RSTCLR_RSCLR_Msk;} /**2 * @return uint32_t Value of CPU clock frequency. * * \parDescription
1 * Provides the vlaue of CPU clock frequency.\n\nB * The value is stored in a global variable \a \b SystemCoreClock.M * It is updated when the clock configuration is done using the SCU LLD APIs.F * The value represents the frequency of clock used for CPU operation.R * \b Range: Value is of type uint32_t, and gives the value of frequency in Hertz. * * \parRelated APIs:
Z * XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n */A__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetCpuClockFrequency(void){ return SystemCoreClock;}/**B * @return uint32_t Value of peripheral clock frequency in Hertz. * * \parDescription
R * Provides the vlaue of clock frequency at which the peripherals are working.\n\np * The value is derived from the CPU frequency. \b Range: Value is of type uint32_t. It is represented in Hertz. * \parRelated APIs:
R * XMC_SCU_CLOCK_GetCpuClockFrequency(),XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n */:uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void); #if(UC_SERIES != XMC45) /** *| * @param peripheral The peripheral for which the clock has to be gated. \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_tC * to identify the peripheral clock to be gated. * * @return None * * \parDescription
= * Blocks the supply of clock to the selected peripheral.\n\nt * Clock gating helps in reducing the power consumption. User can selectively gate the clocks of unused peripherals. * \if XMC1o * fPCLK is the source of clock to various peripherals. Some peripherals support clock gate. Such a gate blocks0 * the clock supply for the selected peripheral.g * Software can request for individual gating of such peripheral clocks by enabling the \a SCU_CGATSET0{ * register bit field. Every bit in \a SCU_CGATSET0 register is protected by the bit protection scheme. Access to protected% * bit fields are handled internally. * \endif * \if XMC4o * fPERI is the source of clock to various peripherals. Some peripherals support clock gate. Such a gate blocks0 * the clock supply for the selected peripheral.a * Software can request for individual gating of such peripheral clocks by enabling one of the \aG * SCU_CGATSET0, \a SCU_CGATSET1 or \a SCU_CGATSET2 register bitfields. * * \endif[ * Note: Clock gating shall not be activated unless the module is in reset state. So use \a[ * XMC_SCU_CLOCK_IsPeripheralClockGated() API before enabling the gating of any peripheral. * \parRelated APIs:
W * XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_UngatePeripheralClock() \n\n\n */Tvoid XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral); /** * * @param peripheral The peripheral for which the clock has to be ungated. \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t1 * to identify the peripheral. * * @return None * * \parDescription
> * Enables the supply of clock to the selected peripheral.\n\nT * By default when the device powers on, the peripheral clock will be gated for the ) * peripherals that support clock gating.P * The peripheral clock should be enabled before using it for any functionality. * \if XMC1\ * fPCLK is the source of clock to various peripherals. Some peripherals support clock gate.d * Software can request for individual ungating of such peripheral clocks by setting respective bits# * in the \a SCU_CGATCLR0 register. * \endif * \if XMC4\ * fPERI is the source of clock to various peripherals. Some peripherals support clock gate.u * Software can request for individual ungating of such peripheral clocks by setting the respective bits in one of \a> * SCU_CGATCLR0, \a SCU_CGATCLR1 or \a SCU_CGATCLR2 registers. * \endif * * \parRelated APIs:
U * XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n */Vvoid XMC_SCU_CLOCK_UngatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral);/** *[ * @param peripheral The peripheral for which the check for clock gating has to be done. d * \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t to identify the peripheral. *g * @return bool Status of the peripheral clock gating. \b Range: true if the peripheral clock is gated.H * false if the peripheral clock ungated(gate de-asserted). * * \parDescription
3 * Gives the status of peripheral clock gating.\n\n * \if XMC1M * Checks the status of peripheral clock gating using the register CGATSTAT0. * \endif * \if XMC4i * Checks the status of peripheral clock gating using one of CGATSTAT0, CGATSTAT1 or CGATSTAT2 registers. * \endif+ * It is recommended to use this API before] * enabling the gating of any peripherals through \a XMC_SCU_CLOCK_GatePeripheralClock() API. * * \parRelated APIs:
T * XMC_SCU_CLOCK_UngatePeripheralClock(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n */Wbool XMC_SCU_CLOCK_IsPeripheralClockGated(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral);#endif/**= * @return uint32_t Status of the register mirror update.\nt * \b Range: Use the bit mask of the SCU_GENERAL_MIRRSTS register for the mirror update event of n * interest. e.g.: SCU_GENERAL_MIRRSTS_RTC_CTR_Msk. Multiple update events can be combined , * using \a OR operation. * * \parDescription
r * Provides the status of hibernate domain register update, when the respective mirror registers are changed. \n\ns * The hibernate domain is connected to the core domain via SPI serial communication. MIRRSTS is a status register m * representing the communication of changed value of a mirror register to its corresponding register in the < * hibernate domain. The bit fields of the register indicatew * that a corresponding register of the hibernate domain is ready to accept a write or that the communication interface3 * is busy with executing the previous operation.\ne * Note: There is no hibernate domain in XMC1x devices. This register is retained for legacy purpose. */6__STATIC_INLINE uint32_t XMC_SCU_GetMirrorStatus(void){ return(SCU_GENERAL->MIRRSTS);}/**Q * @param event The event for which the interrupt handler is to be configured. \nV * \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t for identifying the event.T * @param handler Name of the function to be executed when the event if detected. \nM * \b Range: The function accepts no arguments and returns no value.f * @return XMC_SCU_STATUS_t Status of configuring the event handler function for the selected event.\n] * \b Range: \a XMC_SCU_STATUS_OK if the event handler is successfully configured.\nF * \a XMC_SCU_STATUS_ERROR if the input event is invalid.\n * \parDescription
] * Assigns the event handler function to be executed on occurrence of the selected event.\n\n_ * If the input event is valid, the handler function will be assigned to a table to be executedo * when the interrupt is generated and the event status is set in the event status register. By using this API,u * polling for a particular event can be avoided. This way the CPU utilization will be optimized. Multiple SCU eventst * can generate a common interrupt. When the interrupt is generated, a common interrupt service routine is executed.w * It checks for status flags of events which can generate the interrupt. The handler function will be executed if the  * event flag is set. * * \parRelated APIs:
M * XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERUPT_GetEventStatus() \n\n\n */‹XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler(const XMC_SCU_INTERRUPT_EVENT_t event, const XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler);/**R * @param sr_num Service request number identifying the SCU interrupt generated.\nl * \b Range: 0 to 2. XMC4x devices have one common SCU interrupt, so the value should be 0.\nP * But XMC1x devices support 3 interrupt nodes. * @return None * \parDescription
K * A common function to execute callback functions for multiple events.\n\ni * It checks for the status of events which can generate the interrupt with the selected service request.t * If the event is set, the corresponding callback function will be executed. It also clears the event status bit.\nZ * \b Note: This is an internal function. It should not be called by the user application. * * \parRelated APIs:
- * XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n */)void XMC_SCU_IRQHandler(uint32_t sr_num);#ifdef __cplusplus}#endif/** * @} */ /** * @} */ #endif /* SCU_H */ xmc1_gpio.ch/** * @file xmc1_gpio.c * @date 2015-06-20 * * @condw *********************************************************************************************************************1 * XMClib v2.1.6 - XMC Peripheral Driver Library  *4 * Copyright (c) 2015-2016, Infineon Technologies AG/ * All rights reserved. / * s * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the # * following conditions are met: P * t * Redistributions of source code must retain the above copyright notice, this list of conditions and the following & * disclaimer.  * w * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following p * disclaimer in the documentation and/or other materials provided with the distribution.  * q * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote | * products derived from this software without specific prior written permission. P * v * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, v * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE w * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, t * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR u * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, w * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE y * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. P * w * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with i * Infineon Technologies AG dave@infineon.com). v ********************************************************************************************************************* * * Change History * -------------- * * 2015-02-20: * - Initial draft
 *  * 2015-06-20:G * - Removed version macros and declaration of GetDriverVersion API * * @endcond * */#include "xmc_gpio.h"#if UC_FAMILY == XMC1P/******************************************************************************* * MACROSQ *******************************************************************************/5#define PORT_PHCR_Msk PORT0_PHCR0_PH0_Msk5#define PORT_PHCR_Size PORT0_PHCR0_PH0_Msk5#define PORT_HWSEL_Msk PORT0_HWSEL_HW0_MskP/******************************************************************************* * API IMPLEMENTATIONQ *******************************************************************************/ivoid XMC_GPIO_Init(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_CONFIG_t *const config){G XMC_ASSERT("XMC_GPIO_Init: Invalid port", XMC_GPIO_CHECK_PORT(port));P XMC_ASSERT("XMC_GPIO_Init: Invalid mode", XMC_GPIO_IsModeValid(config->mode));s XMC_ASSERT("XMC_GPIO_Init: Invalid input hysteresis", XMC_GPIO_CHECK_INPUT_HYSTERESIS(config->input_hysteresis));  /* Switch to input */i port->IOCR[pin >> 2U] &= ~(uint32_t)((uint32_t)PORT_IOCR_PC_Msk << (PORT_IOCR_PC_Size * (pin & 0x3U)));# /* HW port control is disabled */P port->HWSEL &= ~(uint32_t)((uint32_t)PORT_HWSEL_Msk << ((uint32_t)pin << 1U)); /* Set input hysteresis */ port->PHCR[(uint32_t)pin >> 3U] &= ~(uint32_t)((uint32_t)PORT_PHCR_Msk << ((uint32_t)PORT_PHCR_Size * ((uint32_t)pin & 0x7U))); port->PHCR[(uint32_t)pin >> 3U] |= (uint32_t)config->input_hysteresis << ((uint32_t)PORT_PHCR_Size * ((uint32_t)pin & 0x7U));  /* Enable digital input */' if (XMC_GPIO_CHECK_ANALOG_PORT(port)) { 6 port->PDISC &= ~(uint32_t)((uint32_t)0x1U << pin); } /* Set output level */4 port->OMR = (uint32_t)config->output_level << pin;  /* Set mode */X port->IOCR[pin >> 2U] |= (uint32_t)config->mode << (PORT_IOCR_PC_Size * (pin & 0x3U));}>void XMC_GPIO_SetInputHysteresis(XMC_GPIO_PORT_t *const port, 4 const uint8_t pin, N const XMC_GPIO_INPUT_HYSTERESIS_t hysteresis){U XMC_ASSERT("XMC_GPIO_SetInputHysteresis: Invalid port", XMC_GPIO_CHECK_PORT(port));s XMC_ASSERT("XMC_GPIO_SetInputHysteresis: Invalid input hysteresis", XMC_GPIO_CHECK_INPUT_HYSTERESIS(hysteresis)); port->PHCR[(uint32_t)pin >> 3U] &= ~(uint32_t)((uint32_t)PORT_PHCR_Msk << ((uint32_t)PORT_PHCR_Size * ((uint32_t)pin & 0x7U)));q port->PHCR[(uint32_t)pin >> 3U] |= (uint32_t)hysteresis << ((uint32_t)PORT_PHCR_Size * ((uint32_t)pin & 0x7U));}#endif /* UC_FAMILY == XMC1 */ xmc1_scu.c§/** * @file xmc1_scu.c * @date 2016-04-15 * * @condv *********************************************************************************************************************1 * XMClib v2.1.6 - XMC Peripheral Driver Library  *4 * Copyright (c) 2015-2016, Infineon Technologies AG * All rights reserved. *r * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: *s * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. *v * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the followingY * disclaimer in the documentation and/or other materials provided with the distribution. *p * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promoteQ * products derived from this software without specific prior written permission. *u * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,t * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AREv * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,r * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ORt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,v * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USEG * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *v * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with/ * Infineon Technologies AG dave@infineon.com).v ********************************************************************************************************************* * * Change History * -------------- * * 2015-02-20: * - Initial
 * * 2015-05-20:5 * - XMC_SCU_StartTempMeasurement API is modifiedM * - XMC_ASSERT statements are added in XMC_SCU_INTERRUPT_SetEventHandler * * 2015-06-20:F * - XMC_SCU_INTERRUPT_EnableEvent,XMC_SCU_INTERRUPT_DisableEvent,H * - XMC_SCU_INTERRUPT_TriggerEvent,XMC_SCU_INTERUPT_GetEventStatus,: * - XMC_SCU_INTERRUPT_ClearEventStatus APIs are added * * 2015-09-23: * - XMC1400 support added * * 2015-11-30: * - Documentation improved * * 2016-02-29:/ * - Fixed XMC_SCU_CLOCK_ScaleMCLKFrequency; * It solves issues with down clock frequency scaling * * 2016-04-15:- * - Fixed XMC_SCU_CLOCK_Init for XMC1400X * It solves issues when trying to disable the OSCHP and use the XTAL pins as GPIO * * * @endcond * *//** *` * @brief SCU low level driver API prototype definition for XMC1 family of microcontrollers
 *+ * Detailed description of file
P * APIs provided in this file cover the following functional blocks of SCU:
0 * -- GCU (APIs prefixed with XMC_SCU_GEN_)
@ * ----Temperature Monitoring, Voltage Monitoring, CCU Start etc *1 * -- CCU (APIs prefixed with XMC_SCU_CLOCK_)
@ * ---- Clock initialization, Clock Gating, Sleep Management etc *2 * -- RCU (APIs prefixed with XMC_SCU_RESET_)
; * ---- Reset Init, Cause, Manual Reset Assert/Deassert etc *; * -- INTERRUPT (APIs prefixed with XMC_SCU_INTERRUPT_)
? * ---- Initialization, Manual Assert/Deassert, Acknowledge etc * */v/********************************************************************************************************************* * HEADER FILESv ********************************************************************************************************************/#include #if UC_FAMILY == XMC1v/********************************************************************************************************************* * MACROSv ********************************************************************************************************************/r#define SCU_IRQ_NUM (3U) /**< array index value for list of events that can generate SCU interrupt */T#define SCU_GCU_PASSWD_PROT_ENABLE (195UL) /**< Password for enabling protection */U#define SCU_GCU_PASSWD_PROT_DISABLE (192UL) /**< Password for disabling protection */]#define XMC_SCU_CHECK_RTCCLKSRC(source) ( (source == XMC_SCU_CLOCK_RTCCLKSRC_DCO2) || \b (source == XMC_SCU_CLOCK_RTCCLKSRC_ERU_IOUT0) || \b (source == XMC_SCU_CLOCK_RTCCLKSRC_ACMP0_OUT) || \b (source == XMC_SCU_CLOCK_RTCCLKSRC_ACMP1_OUT) || \s (source == XMC_SCU_CLOCK_RTCCLKSRC_ACMP2_OUT) ) /**< Used to verifyt whether provided RTCu clock source is validi or not */n#define SCU_GENERAL_INTCR_INTSEL_Msk SCU_GENERAL_INTCR0_INTSEL0_Msk /**< Mask value of Interrupt Source SelectV for Node 0 */w#define SCU_GENERAL_INTCR_INTSEL_Size SCU_GENERAL_INTCR0_INTSEL1_Pos /**< Bit position value of Interrupt Source SelectV for Node 1 */u#define ANA_TSE_T1 (0x10000F30U) /**< d is a constant data can be retrieved from Flash sector 0 to calculate OFFSETE value for DCO calibration */u#define ANA_TSE_T2 (0x10000F31U) /**< e is a constant data can be retrieved from Flash sector 0 to calculate OFFSETE value for DCO calibration */u#define DCO_ADJLO_T1 (0x10000F32U) /**< b is a constant data can be retrieved from Flash sector 0 to calculate OFFSETE value for DCO calibration */u#define DCO_ADJLO_T2 (0x10000F33U) /**< a is a constant data can be retrieved from Flash sector 0 to calculate OFFSETE value for DCO calibration */#if UC_SERIES == XMC14`#define XMC_SCU_INTERRUPT_EVENT_MAX (64U) /**< Maximum supported SCU events for XMC14 device. */#elseg#define XMC_SCU_INTERRUPT_EVENT_MAX (32U) /**< Maximum supported SCU events for XMC11/12/13 device. */#endif#if UC_SERIES == XMC14v#define DCO1_DIV2_FREQUENCY_KHZ_Q22_10 (48000U << 10) /**< used to configures main clock (MCLK) frequency to requestedl frequency value during runtime for XMC14 device. */#elset#define DCO1_DIV2_FREQUENCY_KHZ_Q24_8 (32000U << 8) /**< used to configures main clock (MCLK) frequency to requesteds frequency value during runtime for XMC11/12/13 device. */#endif #define ROM_BmiInstallationReq \w (*((uint32_t (**)(uint32_t requestedBmiValue))0x00000108U)) /**< Pointer to Request BMI installation routine isa available inside ROM. */#define ROM_CalcTemperature \d (*((uint32_t (**)(void))0x0000010cU)) /**< Pointer to Calculate chip temperature routine isL available inside ROM. */#define ROM_CalcTSEVAR \u (*((uint32_t (**)(uint32_t temperature))0x00000120U)) /**< Pointer to Calculate target level for temperaturer comparison routine is available inside ROM. */ v/********************************************************************************************************************* * LOCAL DATAv ********************************************************************************************************************/wstatic XMC_SCU_INTERRUPT_EVENT_HANDLER_t event_handler_list[XMC_SCU_INTERRUPT_EVENT_MAX]; /**< For registering callbackn functions on SCU eventf occurrence. */;static XMC_SCU_INTERRUPT_EVENT_t event_masks[SCU_IRQ_NUM] ={( (XMC_SCU_INTERRUPT_EVENT_FLASH_ERROR |, XMC_SCU_INTERRUPT_EVENT_FLASH_COMPLETED |# XMC_SCU_INTERRUPT_EVENT_PESRAM |$ XMC_SCU_INTERRUPT_EVENT_PEUSIC0 |#if defined(USIC1)$ XMC_SCU_INTERRUPT_EVENT_PEUSIC1 |#endif#if defined(CAN)# XMC_SCU_INTERRUPT_EVENT_PEMCAN |#endif#if UC_SERIES == XMC14+ XMC_SCU_INTERRUPT_EVENT_LOSS_EXT_CLOCK |#endif! XMC_SCU_INTERRUPT_EVENT_LOCI),) (XMC_SCU_INTERRUPT_EVENT_STDBYCLKFAIL |#if UC_SERIES == XMC14* XMC_SCU_INTERRUPT_EVENT_DCO1_OUT_SYNC |#endif" XMC_SCU_INTERRUPT_EVENT_VDDPI |" XMC_SCU_INTERRUPT_EVENT_VDROP |" XMC_SCU_INTERRUPT_EVENT_VCLIP |% XMC_SCU_INTERRUPT_EVENT_TSE_DONE |% XMC_SCU_INTERRUPT_EVENT_TSE_HIGH |$ XMC_SCU_INTERRUPT_EVENT_TSE_LOW |% XMC_SCU_INTERRUPT_EVENT_WDT_WARN |) XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC |& XMC_SCU_INTERRUPT_EVENT_RTC_ALARM |+ XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED |- XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED |- XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED |, XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED |, XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED), (#if UC_SERIES != XMC11! XMC_SCU_INTERRUPT_EVENT_ORC0 |! XMC_SCU_INTERRUPT_EVENT_ORC1 |! XMC_SCU_INTERRUPT_EVENT_ORC2 |! XMC_SCU_INTERRUPT_EVENT_ORC3 |! XMC_SCU_INTERRUPT_EVENT_ORC4 |! XMC_SCU_INTERRUPT_EVENT_ORC5 |! XMC_SCU_INTERRUPT_EVENT_ORC6 |! XMC_SCU_INTERRUPT_EVENT_ORC7 |#endif#if defined(COMPARATOR)" XMC_SCU_INTERRUPT_EVENT_ACMP0 |" XMC_SCU_INTERRUPT_EVENT_ACMP1 |" XMC_SCU_INTERRUPT_EVENT_ACMP2 |#if UC_SERIES == XMC14" XMC_SCU_INTERRUPT_EVENT_ACMP3 |#endif#endif 0)w}; /**< Defines list of events that can generate SCU interrupt and also indicates SCU events mapping to correspondingx service request number. These event mask values can be used to verify which event is triggered that correspondsx to service request number during runtime. All the event items are tabulated as per service request sources list table of SCU. */v/********************************************************************************************************************* * LOCAL ROUTINESv ********************************************************************************************************************/5/* Utility routine to perform frequency up scaling */Qstatic void XMC_SCU_CLOCK_lFrequencyUpScaling(uint32_t curr_idiv, uint32_t idiv);7/* Utility routine to perform frequency down scaling */Sstatic void XMC_SCU_CLOCK_lFrequencyDownScaling(uint32_t curr_idiv, uint32_t idiv);Y/* Calculates the value which must be installed in ANATSEIx register to get indication in_ SCU_INTERRUPT->SRRAW bit when the chip temperature is above/below some target/threshold. */8static uint32_t XMC_SCU_CalcTSEVAR(uint32_t temperature){ uint32_t limit;m XMC_ASSERT("XMC_SCU_CalcTSEVAR: temperature out of range", (temperature >= 233U) && (temperature <= 388U));& limit = ROM_CalcTSEVAR(temperature); if (limit == 0U) {- limit = ROM_CalcTSEVAR(temperature + 1U); if (limit == 0U) {/ limit = ROM_CalcTSEVAR(temperature - 1U); } }  return (limit);}#if UC_SERIES == XMC14p/* This is a local function used to generate the delay until register get updated with new configured value. */"static void delay(uint32_t cycles){ while(cycles > 0U) { __NOP(); cycles--; }}#endifv/********************************************************************************************************************* * API IMPLEMENTATIONv ********************************************************************************************************************/ #ifdef XMC_ASSERT_ENABLE>/* API to verify SCU event weather it is valid event or not */T__STATIC_INLINE bool XMC_SCU_INTERRUPT_IsValidEvent(XMC_SCU_INTERRUPT_EVENT_t event){8 return ((event == XMC_SCU_INTERRUPT_EVENT_WDT_WARN) ||< (event == XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC) ||9 (event == XMC_SCU_INTERRUPT_EVENT_RTC_ALARM) ||5 (event == XMC_SCU_INTERRUPT_EVENT_VDDPI) ||#if defined(USIC1)7 (event == XMC_SCU_INTERRUPT_EVENT_PEUSIC1) ||#endif#if defined(CAN)6 (event == XMC_SCU_INTERRUPT_EVENT_PEMCAN) ||#endif#if UC_SERIES == XMC14> (event == XMC_SCU_INTERRUPT_EVENT_LOSS_EXT_CLOCK) ||= (event == XMC_SCU_INTERRUPT_EVENT_DCO1_OUT_SYNC) ||#endif#if defined(COMPARATOR)5 (event == XMC_SCU_INTERRUPT_EVENT_ACMP0) ||5 (event == XMC_SCU_INTERRUPT_EVENT_ACMP1) ||5 (event == XMC_SCU_INTERRUPT_EVENT_ACMP2) ||#if UC_SERIES == XMC145 (event == XMC_SCU_INTERRUPT_EVENT_ACMP3) ||#endif#endif5 (event == XMC_SCU_INTERRUPT_EVENT_VDROP) ||#if UC_SERIES != XMC114 (event == XMC_SCU_INTERRUPT_EVENT_ORC0) ||4 (event == XMC_SCU_INTERRUPT_EVENT_ORC1) ||4 (event == XMC_SCU_INTERRUPT_EVENT_ORC2) ||4 (event == XMC_SCU_INTERRUPT_EVENT_ORC3) ||4 (event == XMC_SCU_INTERRUPT_EVENT_ORC4) ||4 (event == XMC_SCU_INTERRUPT_EVENT_ORC5) ||4 (event == XMC_SCU_INTERRUPT_EVENT_ORC6) ||4 (event == XMC_SCU_INTERRUPT_EVENT_ORC7) ||#endif4 (event == XMC_SCU_INTERRUPT_EVENT_LOCI) ||6 (event == XMC_SCU_INTERRUPT_EVENT_PESRAM) ||7 (event == XMC_SCU_INTERRUPT_EVENT_PEUSIC0) ||; (event == XMC_SCU_INTERRUPT_EVENT_FLASH_ERROR) ||? (event == XMC_SCU_INTERRUPT_EVENT_FLASH_COMPLETED) ||5 (event == XMC_SCU_INTERRUPT_EVENT_VCLIP) ||< (event == XMC_SCU_INTERRUPT_EVENT_STDBYCLKFAIL) ||> (event == XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED) ||@ (event == XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED) ||@ (event == XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED) ||? (event == XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED) ||? (event == XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED) ||8 (event == XMC_SCU_INTERRUPT_EVENT_TSE_DONE) ||8 (event == XMC_SCU_INTERRUPT_EVENT_TSE_HIGH) ||6 (event == XMC_SCU_INTERRUPT_EVENT_TSE_LOW));} #endif!/* API to enable the SCU event */Ivoid XMC_SCU_INTERRUPT_EnableEvent(const XMC_SCU_INTERRUPT_EVENT_t event){* SCU_INTERRUPT->SRMSK |= (uint32_t)event;#if UC_SERIES == XMC144 SCU_INTERRUPT->SRMSK1 |= (uint32_t)(event >> 32U);#endif}"/* API to disable the SCU event */Jvoid XMC_SCU_INTERRUPT_DisableEvent(const XMC_SCU_INTERRUPT_EVENT_t event){+ SCU_INTERRUPT->SRMSK &= ~(uint32_t)event;#if UC_SERIES == XMC145 SCU_INTERRUPT->SRMSK1 &= (uint32_t)~(event >> 32U);#endif}"/* API to trigger the SCU event */Jvoid XMC_SCU_INTERRUPT_TriggerEvent(const XMC_SCU_INTERRUPT_EVENT_t event){* SCU_INTERRUPT->SRSET |= (uint32_t)event;#if UC_SERIES == XMC144 SCU_INTERRUPT->SRSET1 |= (uint32_t)(event >> 32U);#endif}%/* API to get the SCU event status */?XMC_SCU_INTERRUPT_EVENT_t XMC_SCU_INTERUPT_GetEventStatus(void){ XMC_SCU_INTERRUPT_EVENT_t tmp; tmp = SCU_INTERRUPT->SRRAW;#if UC_SERIES == XMC141 tmp |= ((int64_t)SCU_INTERRUPT->SRRAW1 << 32U);#endif return (tmp);}'/* API to clear the SCU event status */Nvoid XMC_SCU_INTERRUPT_ClearEventStatus(const XMC_SCU_INTERRUPT_EVENT_t event){* SCU_INTERRUPT->SRCLR |= (uint32_t)event;#if UC_SERIES == XMC144 SCU_INTERRUPT->SRCLR1 |= (uint32_t)(event >> 32U);#endif}9/* API to lock protected bitfields from being modified */$void XMC_SCU_LockProtectedBits(void){3 SCU_GENERAL->PASSWD = SCU_GCU_PASSWD_PROT_ENABLE;}@/* API to make protected bitfields available for modification */&void XMC_SCU_UnlockProtectedBits(void){4 SCU_GENERAL->PASSWD = SCU_GCU_PASSWD_PROT_DISABLE;? while(((SCU_GENERAL->PASSWD) & SCU_GENERAL_PASSWD_PROTS_Msk)) {( /* Loop until the lock is removed */ }}4/* API to initialize power supply monitoring unit */Bvoid XMC_SCU_SupplyMonitorInit(const XMC_SCU_SUPPLYMONITOR_t *obj){ uint32_t anavdel; uint32_t irqmask; anavdel = 0UL;\ anavdel |= (uint32_t)((obj-> ext_supply_threshold) << SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos);` anavdel |= (uint32_t)((obj->ext_supply_monitor_speed) << SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos);# if(true == (obj->enable_at_init)) {8 anavdel |= (uint32_t)SCU_ANALOG_ANAVDEL_VDEL_EN_Msk; }, SCU_ANALOG->ANAVDEL = (uint16_t) anavdel; irqmask = 0UL;* if(true == (obj->enable_prewarning_int)) {7 irqmask |= (uint32_t)SCU_INTERRUPT_SRMSK_VDDPI_Msk; }% if(true == (obj->enable_vdrop_int)) {8 irqmask |= (uint32_t)SCU_INTERRUPT_SRMSK_VDROPI_Msk; }% if(true == (obj->enable_vclip_int)) {8 irqmask |= (uint32_t)SCU_INTERRUPT_SRMSK_VCLIPI_Msk; }, SCU_INTERRUPT->SRMSK |= (uint32_t)irqmask;},/* API to program lower temperature limit */8XMC_SCU_STATUS_t XMC_SCU_SetTempLowLimit(uint32_t limit){. XMC_SCU_STATUS_t status = XMC_SCU_STATUS_OK;$ limit = XMC_SCU_CalcTSEVAR(limit); if (limit != 0)  {+ SCU_ANALOG->ANATSEIL = (uint16_t)limit; } else {" status = XMC_SCU_STATUS_ERROR; } return (status);} -/* API to program higher temperature limit */9XMC_SCU_STATUS_t XMC_SCU_SetTempHighLimit(uint32_t limit){. XMC_SCU_STATUS_t status = XMC_SCU_STATUS_OK;$ limit = XMC_SCU_CalcTSEVAR(limit); if (limit != 0)  {+ SCU_ANALOG->ANATSEIH = (uint16_t)limit; } else {" status = XMC_SCU_STATUS_ERROR; }  return (status);}U/* API to program temperature limits as raw digital values into temperature sensor */Svoid XMC_SCU_SetRawTempLimits(const uint32_t lower_temp, const uint32_t upper_temp){Q SCU_ANALOG->ANATSEIH = (uint16_t)(upper_temp & SCU_ANALOG_ANATSEIH_TSE_IH_Msk);Q SCU_ANALOG->ANATSEIL = (uint16_t)(lower_temp & SCU_ANALOG_ANATSEIL_TSE_IL_Msk);}*/* API to start temperature measurement */'void XMC_SCU_StartTempMeasurement(void){G SCU_ANALOG->ANATSECTRL |= (uint16_t)SCU_ANALOG_ANATSECTRL_TSE_EN_Msk;})/* API to stop temperature measurement */&void XMC_SCU_StopTempMeasurement(void){H SCU_ANALOG->ANATSECTRL &= (uint16_t)~SCU_ANALOG_ANATSECTRL_TSE_EN_Msk;}?/* API to check if the temperature has gone past the ceiling */"bool XMC_SCU_HighTemperature(void){i return ((SCU_INTERRUPT->SRRAW & SCU_INTERRUPT_SRRAW_TSE_HIGH_Msk) == SCU_INTERRUPT_SRRAW_TSE_HIGH_Msk);}:/* API to check if the temperature is lower than normal */!bool XMC_SCU_LowTemperature(void){g return ((SCU_INTERRUPT->SRRAW & SCU_INTERRUPT_SRRAW_TSE_LOW_Msk) == SCU_INTERRUPT_SRRAW_TSE_LOW_Msk);},/* API to retrieve the device temperature */%uint32_t XMC_SCU_GetTemperature(void){ uint32_t temperature;2 temperature = (uint32_t)(SCU_ANALOG->ANATSEMON); return (temperature);}=/* Calculates the die temperature value using ROM function */&uint32_t XMC_SCU_CalcTemperature(void){! return (ROM_CalcTemperature());}7/* API which initializes the clock tree ofthe device */Cvoid XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config){ /* Remove protection */ XMC_SCU_UnlockProtectedBits();#if (UC_SERIES == XMC14)) /* OSCHP source selection - OSC mode */> if (config->oschp_mode != XMC_SCU_CLOCK_OSCHP_MODE_DISABLED) {) if (OSCHP_GetFrequency() > 20000000U) {P SCU_ANALOG->ANAOSCHPCTRL |= (uint16_t)SCU_ANALOG_ANAOSCHPCTRL_HYSCTRL_Msk; }Ž SCU_ANALOG->ANAOSCHPCTRL = (uint16_t)(SCU_ANALOG->ANAOSCHPCTRL & ~(SCU_ANALOG_ANAOSCHPCTRL_SHBY_Msk | SCU_ANALOG_ANAOSCHPCTRL_MODE_Msk)) |4 config->oschp_mode;* /* Enable OSC_HP oscillator watchdog*/1 SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_XOWDEN_Msk; do {. /* Restart OSC_HP oscillator watchdog */= SCU_INTERRUPT->SRCLR1 = SCU_INTERRUPT_SRCLR1_LOECI_Msk;4 SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_XOWDRES_Msk;O /* Wait a few DCO2 cycles for the update of the clock detection result */ delay(2500); /* check clock is ok */ }B while(SCU_INTERRUPT->SRRAW1 & SCU_INTERRUPT_SRRAW1_LOECI_Msk); }F else /* (config->oschp_mode == XMC_SCU_CLOCK_OSCHP_MODE_DISABLED) */ {A SCU_ANALOG->ANAOSCHPCTRL |= SCU_ANALOG_ANAOSCHPCTRL_MODE_Msk; }: SCU_ANALOG->ANAOSCLPCTRL = (uint16_t)config->osclp_mode;E SCU_CLK->CLKCR1 = (SCU_CLK->CLKCR1 & ~SCU_CLK_CLKCR1_DCLKSEL_Msk) |% config->dclk_src;#endif" /* Update PCLK selection mux. */l SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_PCLKSEL_Msk | SCU_CLK_CLKCR_RTCCLKSEL_Msk)) |$ config->rtc_src |$ config->pclk_src;$ /* Close the lock opened above. */ XMC_SCU_LockProtectedBits(); /* Update the dividers now */? XMC_SCU_CLOCK_ScaleMCLKFrequency(config->idiv, config->fdiv);}\/* API which selects one of the available parent clock nodes for a given child clock node */Lvoid XMC_SCU_CLOCK_SetRtcClockSource(const XMC_SCU_CLOCK_RTCCLKSRC_t source){d XMC_ASSERT("XMC_SCU_CLOCK_SetRtcSourceClock:Wrong Parent Clock", XMC_SCU_CHECK_RTCCLKSRC(source)); XMC_SCU_UnlockProtectedBits();N SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~SCU_CLK_CLKCR_RTCCLKSEL_Msk) | source; XMC_SCU_LockProtectedBits();}F/* API to program the divider placed between fperiph and its parent */Uvoid XMC_SCU_CLOCK_SetFastPeripheralClockSource(const XMC_SCU_CLOCK_PCLKSRC_t source){ XMC_SCU_UnlockProtectedBits();L SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~SCU_CLK_CLKCR_PCLKSEL_Msk) | source; XMC_SCU_LockProtectedBits();}0/* API which gates a clock node at its source */Svoid XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral){ XMC_SCU_UnlockProtectedBits();, SCU_CLK->CGATSET0 |= (uint32_t)peripheral; XMC_SCU_LockProtectedBits();}2/* API which ungates a clock note at its source */Uvoid XMC_SCU_CLOCK_UngatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral){ XMC_SCU_UnlockProtectedBits();, SCU_CLK->CGATCLR0 |= (uint32_t)peripheral;7 while ((SCU_CLK->CLKCR) & SCU_CLK_CLKCR_VDDC2LOW_Msk) {* /* Wait voltage suply stabilization */ } XMC_SCU_LockProtectedBits();}2/* Checks the status of peripheral clock gating */Vbool XMC_SCU_CLOCK_IsPeripheralClockGated(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral){8 return (bool)((SCU_CLK->CGATSTAT0 & peripheral) != 0);}S/* This API configures main clock (MCLK) frequency to requested frequency value. */6void XMC_SCU_CLOCK_SetMCLKFrequency(uint32_t freq_khz){ uint32_t ratio; uint32_t ratio_int; uint32_t ratio_frac;#if UC_SERIES == XMC14= if (((SCU_CLK->CLKCR1) & SCU_CLK_CLKCR1_DCLKSEL_Msk) == 0U) {7 ratio = DCO1_DIV2_FREQUENCY_KHZ_Q22_10 / freq_khz; } else {@ ratio = ((OSCHP_GetFrequency() / 1000U) << 10U) / freq_khz; } /* Manage overflow */ if (ratio > 0xffffffU) { ratio = 0xffffffU; } ratio_int = ratio >> 10U; ratio_frac = ratio & 0x3ffU;#else5 ratio = DCO1_DIV2_FREQUENCY_KHZ_Q24_8 / freq_khz; /* Manage overflow */ if (ratio > 0xffffU) { ratio = 0xffffU; } ratio_int = ratio >> 8U; ratio_frac = ratio & 0xffU;#endif: XMC_SCU_CLOCK_ScaleMCLKFrequency(ratio_int, ratio_frac);}F/* A utility routine which updates the fractional dividers in steps */Cvoid XMC_SCU_CLOCK_ScaleMCLKFrequency(uint32_t idiv, uint32_t fdiv){1 /* Find out current and target value of idiv */ uint32_t curr_idiv; XMC_SCU_UnlockProtectedBits();= /* Take a snapshot of value already programmed into IDIV */R curr_idiv = (SCU_CLK->CLKCR & SCU_CLK_CLKCR_IDIV_Msk) >> SCU_CLK_CLKCR_IDIV_Pos;#if (UC_SERIES == XMC14)N SCU_CLK->CLKCR1 = (SCU_CLK->CLKCR1 & (uint32_t)~(SCU_CLK_CLKCR1_FDIV_Msk)) |G (uint32_t)((fdiv >> 8U) << SCU_CLK_CLKCR1_FDIV_Pos);f SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_FDIV_Msk | SCU_CLK_CLKCR_CNTADJ_Msk)) |I (uint32_t)((fdiv & 0xffU) << SCU_CLK_CLKCR_FDIV_Pos) |B (uint32_t)(1023UL << SCU_CLK_CLKCR_CNTADJ_Pos);#elsef SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_FDIV_Msk | SCU_CLK_CLKCR_CNTADJ_Msk)) |? (uint32_t)(fdiv << SCU_CLK_CLKCR_FDIV_Pos) |B (uint32_t)(1023UL << SCU_CLK_CLKCR_CNTADJ_Pos);#endif6 while ((SCU_CLK->CLKCR)& SCU_CLK_CLKCR_VDDC2LOW_Msk) {/ /* Spin until the core supply stabilizes */ } if(curr_idiv <= idiv) {^ /* Requested IDIV is greater than currently programmed IDIV. So downscale the frequency */9 XMC_SCU_CLOCK_lFrequencyDownScaling(curr_idiv, idiv); } else {Z /* Requested IDIV is lower than currently programmed IDIV. So upscale the frequency */7 XMC_SCU_CLOCK_lFrequencyUpScaling(curr_idiv, idiv); }f SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_IDIV_Msk | SCU_CLK_CLKCR_CNTADJ_Msk)) |o (uint32_t)(idiv << SCU_CLK_CLKCR_IDIV_Pos) | (uint32_t)(1023UL << SCU_CLK_CLKCR_CNTADJ_Pos);7 while ((SCU_CLK->CLKCR) & SCU_CLK_CLKCR_VDDC2LOW_Msk) {* /* Wait voltage suply stabilization */ } XMC_SCU_LockProtectedBits(); SystemCoreClockUpdate();}5/* Utility routine to perform frequency up scaling */Wstatic void XMC_SCU_CLOCK_lFrequencyUpScaling(uint32_t curr_idiv, uint32_t target_idiv){) while (curr_idiv > (target_idiv * 4UL)) {B curr_idiv = (uint32_t)(curr_idiv >> 2UL); /* Divide by 4. */h SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_IDIV_Msk | SCU_CLK_CLKCR_CNTADJ_Msk)) |G (uint32_t)(curr_idiv << SCU_CLK_CLKCR_IDIV_Pos) | D (uint32_t)(1023UL << SCU_CLK_CLKCR_CNTADJ_Pos);7 while (SCU_CLK->CLKCR & SCU_CLK_CLKCR_VDDC2LOW_Msk) {* /* Wait voltage suply stabilization */ } }}7/* Utility routine to perform frequency down scaling */Ystatic void XMC_SCU_CLOCK_lFrequencyDownScaling(uint32_t curr_idiv, uint32_t target_idiv){) while ((curr_idiv * 4UL) < target_idiv) { if(0U == curr_idiv) { curr_idiv = 1U; }E curr_idiv = (uint32_t)(curr_idiv << 2UL); /* Multiply by 4. */h SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_IDIV_Msk | SCU_CLK_CLKCR_CNTADJ_Msk)) |F (uint32_t)(curr_idiv << SCU_CLK_CLKCR_IDIV_Pos) |D (uint32_t)(1023UL << SCU_CLK_CLKCR_CNTADJ_Pos);7 while (SCU_CLK->CLKCR & SCU_CLK_CLKCR_VDDC2LOW_Msk) {* /* Wait voltage suply stabilization */ } }}/*g * API to retrieve clock frequency of peripherals on the peripheral bus using a shared functional clock */8uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void){ return (SystemCoreClock);}p/* Provides the clock frequency of peripherals on the peripheral bus that are using a shared functional clock */<uint32_t XMC_SCU_CLOCK_GetFastPeripheralClockFrequency(void){j return (SystemCoreClock << ((SCU_CLK->CLKCR & SCU_CLK_CLKCR_PCLKSEL_Msk) >> SCU_CLK_CLKCR_PCLKSEL_Pos));}X/* DCO1 clock frequency can be calibrated during runtime to achieve a better accuracy */Hvoid XMC_SCU_CLOCK_CalibrateOscillatorOnTemperature(int32_t temperature){ int32_t a; int32_t b; int32_t d; int32_t e; int32_t offset; a = *((uint8_t*)DCO_ADJLO_T2); b = *((uint8_t*)DCO_ADJLO_T1); d = *((uint8_t*)ANA_TSE_T1); e = *((uint8_t*)ANA_TSE_T2);9 offset = b + (((a - b) * (temperature - d)) / (e - d));1 offset &= SCU_ANALOG_ANAOFFSET_ADJL_OFFSET_Msk; XMC_SCU_UnlockProtectedBits();+ SCU_ANALOG->ANAOFFSET = (uint16_t)offset; XMC_SCU_LockProtectedBits();}/*^ * API to assign the event handler function to be executed on occurrence of the selected event */~XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler(XMC_SCU_INTERRUPT_EVENT_t event, XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler){ uint32_t index; XMC_SCU_STATUS_t status;h XMC_ASSERT("XMC_SCU_INTERRUPT_SetEventHandler: Invalid event", XMC_SCU_INTERRUPT_IsValidEvent(event));T XMC_ASSERT("XMC_SCU_INTERRUPT_SetEventHandler: Invalid handler", handler != NULL); index = 0U;l while (((event & ((XMC_SCU_INTERRUPT_EVENT_t)1 << index)) == 0U) && (index < XMC_SCU_INTERRUPT_EVENT_MAX)) { index++; }+ if (index == XMC_SCU_INTERRUPT_EVENT_MAX) {" status = XMC_SCU_STATUS_ERROR; } else {( event_handler_list[index] = handler; status = XMC_SCU_STATUS_OK; } return (status);}/*F * A common function to execute callback functions for multiple events */(void XMC_SCU_IRQHandler(uint32_t sr_num){I XMC_ASSERT("XMC_SCU_IRQHandler: Invalid sr_num", sr_num < SCU_IRQ_NUM); uint32_t index;" XMC_SCU_INTERRUPT_EVENT_t event;2 XMC_SCU_INTERRUPT_EVENT_HANDLER_t event_handler; index = 0U;B event = XMC_SCU_INTERUPT_GetEventStatus() & event_masks[sr_num];, XMC_SCU_INTERRUPT_ClearEventStatus(event);? while ((event != 0) && (index < XMC_SCU_INTERRUPT_EVENT_MAX)) {@ if ((event & ((XMC_SCU_INTERRUPT_EVENT_t)1 << index)) != 0U) {8 event &= ~((XMC_SCU_INTERRUPT_EVENT_t)1 << index);0 event_handler = event_handler_list[index]; if (event_handler != NULL) { event_handler(); }. /* break; XMC1: Only PULSE interrupts */ } index++; }}#if (UC_SERIES == XMC14)X/* DCO1 clock frequency can be calibrated during runtime to achieve a better accuracy */~void XMC_SCU_CLOCK_EnableDCO1ExtRefCalibration(XMC_SCU_CLOCK_SYNC_CLKSRC_t sync_clk, uint32_t prescaler, uint32_t syn_preload){ XMC_SCU_UnlockProtectedBits();T SCU_ANALOG->ANASYNC2 = (uint16_t)(prescaler << SCU_ANALOG_ANASYNC2_PRESCALER_Pos);1 SCU_ANALOG->ANASYNC1 = (uint16_t)(syn_preload |# sync_clk |> SCU_ANALOG_ANASYNC1_SYNC_DCO_EN_Msk); XMC_SCU_LockProtectedBits();}[/* This function stops the automatic DCO1 calibration based on the selected clock source */5void XMC_SCU_CLOCK_DisableDCO1ExtRefCalibration(void){ XMC_SCU_UnlockProtectedBits(); SCU_ANALOG->ANASYNC2 = 0U; SCU_ANALOG->ANASYNC1 = 0U; XMC_SCU_LockProtectedBits();}=/* This functions checks the status of the synchronisation */5bool XMC_SCU_CLOCK_IsDCO1ExtRefCalibrationReady(void){S return (bool)((SCU_ANALOG->ANASYNC2 & SCU_ANALOG_ANASYNC2_SYNC_READY_Msk) != 0U);}/**; * This function enables the watchdog on the DCO1 frequency */5void XMC_SCU_CLOCK_EnableDCO1OscillatorWatchdog(void){. SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_OWDEN_Msk;}/**< * This function disables the watchdog on the DCO1 frequency */6void XMC_SCU_CLOCK_DisableDCO1OscillatorWatchdog(void){/ SCU_CLK->OSCCSR &= ~SCU_CLK_OSCCSR_OWDEN_Msk;}/**H * This function clears the status of the watchdog on the DCO1 frequency */:void XMC_SCU_CLOCK_ClearDCO1OscillatorWatchdogStatus(void){/ SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_OWDRES_Msk;}/**O * This function checks if the DCO1 frequency is in the limits of the watchdog. */3bool XMC_SCU_CLOCK_IsDCO1ClockFrequencyUsable(void){[ return ((SCU_CLK->OSCCSR & (SCU_CLK_OSCCSR_OSC2L_Msk | SCU_CLK_OSCCSR_OSC2H_Msk)) == 0U);}L/* This function selects service request source for a NVIC interrupt node */Nvoid XMC_SCU_SetInterruptControl(uint8_t irq_number, XMC_SCU_IRQCTRL_t source){Q XMC_ASSERT("XMC_SCU_SetInterruptControl: Invalid irq_number", irq_number < 32);Y XMC_ASSERT("XMC_SCU_SetInterruptControl: Invalid source", (source >> 8) == irq_number); source &= 0x3U; if (irq_number < 16U) {ƒ SCU_GENERAL->INTCR0 = (SCU_GENERAL->INTCR0 & ~(SCU_GENERAL_INTCR_INTSEL_Msk << (irq_number * SCU_GENERAL_INTCR_INTSEL_Size))) |S (source << (irq_number * SCU_GENERAL_INTCR_INTSEL_Size)); } else { irq_number &= 0x0fU;„ SCU_GENERAL->INTCR1 = (SCU_GENERAL->INTCR1 & ~(SCU_GENERAL_INTCR_INTSEL_Msk << (irq_number * SCU_GENERAL_INTCR_INTSEL_Size))) |T (source << (irq_number * SCU_GENERAL_INTCR_INTSEL_Size)); }}#endif#endif /* UC_FAMILY == XMC1 */ xmc_ccu4.cy/** * @file xmc_ccu4.c * @date 2015-10-07 * * @condv ************************************************************