OBSS¸Circuit DescriptionV1.1010/02/94 20:07 CET.Component & analysis parameters of a circuit.TINA 12.0.0.0 SFB(c) Copyright 1993,94,95,96 DesignSoft Inc. All rights reserved.9 $Circuit$ÿÿÿÿð?Z[AT_Transient]R_LED1_PIN .color.y1=255R_LED1_PIN .min.y1=0R_LED1_PIN .max.y1=5R_LED1_PIN .divs.y1=1R_LED1_PIN .scale.y1=0R_LED1_PIN .precision.y1=2R_LED1_PIN .nformat.y1=1G_LED1_PIN .color.y1=65280G_LED1_PIN .min.y1=0G_LED1_PIN .max.y1=5G_LED1_PIN .divs.y1=1G_LED1_PIN .scale.y1=0G_LED1_PIN .precision.y1=2G_LED1_PIN .nformat.y1=1B_LED1_PIN .color.y1=16711680B_LED1_PIN .min.y1=0B_LED1_PIN .max.y1=5B_LED1_PIN .divs.y1=1B_LED1_PIN .scale.y1=0B_LED1_PIN .precision.y1=2B_LED1_PIN .nformat.y1=1I_R_LED1 .color.y1=255I_R_LED1 .min.y1=0I_R_LED1 .max.y1=0.02I_R_LED1 .divs.y1=1I_R_LED1 .scale.y1=0I_R_LED1 .precision.y1=2I_R_LED1 .nformat.y1=1I_G_LED1 .color.y1=65280I_G_LED1 .min.y1=0I_G_LED1 .max.y1=0.02I_G_LED1 .divs.y1=1I_G_LED1 .scale.y1=0I_G_LED1 .precision.y1=2I_G_LED1 .nformat.y1=1eye_bright .color.y1=39423eye_bright .min.y1=0eye_bright .max.y1=0.004eye_bright .divs.y1=1eye_bright .scale.y1=0eye_bright .precision.y1=2eye_bright .nformat.y1=1eye_R_bright .color.y1=255eye_R_bright .min.y1=0eye_R_bright .max.y1=0.003eye_R_bright .divs.y1=1eye_R_bright .scale.y1=0eye_R_bright .precision.y1=2eye_R_bright .nformat.y1=1eye_G_bright .color.y1=65280eye_G_bright .min.y1=0eye_G_bright .max.y1=0.003eye_G_bright .divs.y1=1eye_G_bright .scale.y1=0eye_G_bright .precision.y1=2eye_G_bright .nformat.y1=1 eye_B_bright .color.y1=16711680eye_B_bright .min.y1=0eye_B_bright .max.y1=0.003eye_B_bright .divs.y1=1eye_B_bright .scale.y1=0eye_B_bright .precision.y1=2eye_B_bright .nformat.y1=1R_LED1_PIN .width=1R_LED1_PIN .color=255G_LED1_PIN .width=1G_LED1_PIN .color=65280B_LED1_PIN .width=1B_LED1_PIN .color=16711680I_R_LED1 .width=1I_R_LED1 .color=255I_B_LED1 .color.y1=16711680I_B_LED1 .min.y1=0I_B_LED1 .max.y1=0.02I_B_LED1 .divs.y1=1I_B_LED1 .scale.y1=0I_B_LED1 .precision.y1=2I_B_LED1 .nformat.y1=1I_G_LED1 .width=1I_G_LED1 .color=65280eye_bright .width=1eye_bright .color=52479eye_R_bright .width=1eye_R_bright .color=255eye_G_bright .width=1eye_G_bright .color=65280eye_B_bright .width=1eye_B_bright .color=16711680L'æ`'æ ÿÿArialÿ6\a(Other circuits,http://www.infineon.com/ifxdesigner)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_B1C4A0E2-291D-450B-BD8B-E4DAD78CA9F5X'Å`'Å ÿÿArialÿ<\a(Development platform: DAVE"!,http://www.infineon.com/dave)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_CB17B03C-8667-4F35-BA44-D63B8458E768('¥`'¥ ÿÿArialÿ¤\a(DAVE code: RGB LED Example,http://www.infineon.com/dgdl/Infineon-BCCU-XMC1000-AP32275_Example_Code-SW-v01_00-EN.exe?fileId=5546d4624e765da5014ed8cad4fc1385&sd=t)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_78B0051E-B655-4994-92B3-D5DDEAAF3E38D'†`'† ÿÿArialÿ²\a(Application Note: Brightness and Color Control Unit (BCCU),http://www.infineon.com/dgdl/Infineon-BCCU-XMC1000-AP32275-AN-v01_01-EN.pdf?fileId=5546d4624e765da5014ed8cabae512ad)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_A21135C0-5545-4EDD-8291-0208CBA9971C'f`'f ÿÿArialÿ’\a(Reference manual: XMC1200 AB-Step,http://www.infineon.com/dgdl/Infineon-xmc1200-AB_rm-UM-v01_02-EN.pdf?fileId=5546d46249cd1014014a0a7b1f1f5e1b)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_2C41F7FA-16CA-4131-AFCE-7DE6B46CAC34x'E`'E ÿÿArialÿL\a(Product info: XMC1200-T038F0200 AB,http://www.infineon.com/cms/en/product/microcontroller/32-bit-industrial-microcontroller-based-on-arm-registered-cortex-registered-m/32-bit-xmc1000-industrial-microcontroller-arm-registered-cortex-registered-m0/XMC1200-T038F0200+AB/productType.html?productType=5546d4624cb7f111014d4334e7dc285c)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_DF685C05-66F6-4E33-81D8-05E6EAC08910,'&`'& ÿÿArialÿ&\a(Buy online,tdl://file.shoppingcart)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_D7C78C58-E692-4A68-A14F-65F472DE1686¾'5`'5 ÿÿArialo`c #How to program the microcontroller:1. Build project in DAVE2. Export project into a .zip&3. Click on the microcontroller symbol84. Click on the "MCU-code" details, then select "Upload".5. Drag and drop the .zip file created earlier"6. Click "Upload", then click "OK"M7. (optional) Launch debugger by clicking on the "TR" button on the top rightSymbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_4C69BD0D-B062-43E2-8CDE-18E39952ED890²`² ÿÿArialÿÿÿ(\a(Simulate Transient,tdl://analysis.tr)Symbol«7zà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_589476FB-7BC3-40B4-B862-340B89C91EADú¨ÿ7`¨ÿ7 ÿÿArialo`c Need support?Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_27609132-40D6-460F-97FA-1AC0741A86B7P¨ÿY`¨ÿY ÿÿArialÿ8\a(Technical Assistance,http://www.infineon.com/support)Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_80E8CB85-F667-4C5B-873F-6E8D5CC90A18&%öÿ`%öÿ ÿÿArialo`c#Controlling RGB LED Color with BCCUSymbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_A6C80F02-0033-437E-B1F5-04502ED7E9D9ò'!`'! ÿÿArialo`c IThis example demonstrates how easily the color of the light emitted by anARGB LED (3-channel LED) can be controlled by the BCCU in XMC1200,:based on the DAVE project "RGB_LED_Example_Color_Control".FThe following code lines have been changed to speed up the color walk:?(line 185) XMC_BCCU_CH_SetLinearWalkPrescaler(R_LED1_CH, 0x1);?(line 186) XMC_BCCU_CH_SetLinearWalkPrescaler(G_LED1_CH, 0x1);?(line 187) XMC_BCCU_CH_SetLinearWalkPrescaler(B_LED1_CH, 0x1);"(line 193) SysTick_Config(24000U);Symbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_DCCCA93F-80BD-4FFB-A285-C1131F01FC5D¨ÿ÷ÿ`¨ÿ÷ÿ ÿÿArialo`c&1. Wanna try it out? Click on simulate(2. Click on circuit components to change'3. If you like what you see, buy online4. Enjoy other circuitsSymbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_29EA33DE-6FC3-4E4C-BCA3-860C36ED79E7ø {` { ÿÿArial Human visionSymbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_262EFD60-CE21-4C7D-8CD6-04B59A7F3B98è[1`[1 ÿÿArialLEDsSymbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_CECE079C-01A6-4B73-B9CB-79125559CAF2î×1`×1 ÿÿArialDriversSymbolÿÿÿà?à?è?è?333333Ó?à?ÿÿÿÿÿÿÿÿÿÿ*Text_9DD16865-A425-41A4-A69F-E4C2CD8026A1I€È€ˆ€È€ˆÿÿÿÿ%EAF9B5C2-6161-4118-9E92-A875F2EFFD0BI€€€ˆ€€€ˆÿÿÿÿ%B5DC8095-E43C-4EBA-8D6D-876F0186D975I¸¸¸¸ÿÿÿÿ%59999D3D-D0F5-415E-9079-A0A5E5941258I@àxà@àxàÿÿÿÿ%21DECBF1-F255-4585-8E82-A0084991060CIp¸x¸p¸x¸ÿÿÿÿ%343C90CB-81A3-48AA-88C2-56C2A76E8878I€¸x¸€¸x¸ÿÿÿÿ%67EBB6C0-B20C-424E-BC60-35DA24CC0EFBI@¸H¸@¸H¸ÿÿÿÿ%A110590A-5987-47FB-97F2-7646C54BBF3DM È€ˆ È ˆ€ˆÿÿÿÿ%40737A12-36FC-4690-A2DB-4CEFC8BEDA5FIàPàXàPàXÿÿÿÿ%C16267AC-663F-4D21-9731-B597163ECAAFIPXPXÿÿÿÿ%5B06C92A-EB25-4553-873E-45D816B9E676Ià à(à à(ÿÿÿÿ%59B7BB6D-6333-4EDA-91F5-A58BC3216AA4I( ( ÿÿÿÿ%E0AAD8A1-2702-45B4-BD82-787A038C2531I¨(¨ ¨(¨ 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arch_name: RTL;3-- ports: VSS,VDD,P0.0(P0_0),P0.1(P0_1),P0.2(P0_2),@-- P0.3(P0_3),P0.4(P0_4),P0.5(P0_5),P0.6(P0_6),P0.7(P0_7) -- -- ;:-- P0.8(P0_8),P0.9(P0_9),P0.10(P0_10),P0.11(P0_11),>-- P0.12(P0_12),P0.13(P0_13),P0.14(P0_14),P0.15(P0_15), -- TSE -- ;A-- P1.0(P1_0),P1.1(P1_1),P1.2(P1_2),P1.3(P1_3),P1.4(P1_4),*-- P1.5(P1_5),P2.0(P2_0),P2.1(P2_1) -- ;A-- P2.2(P2_2),P2.3(P2_3),P2.4(P2_4),P2.5(P2_5),P2.6(P2_6),8-- P2.7(P2_7),P2.8(P2_8),P2.9(P2_9),P2.10(P2_10),-- P2.11(P2_11) -- ;-- Description: ARMCORTEX;-- Device: XMC1200_T038;-- !-- TINA HDL Macro Description End%------------------------------------ library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;use mcu.mcu_functions.all;entity XMC1200_T038 is port( clk : in std_logic; vss : in std_logic; vdd : in std_logic; p0_0 : inout std_logic; p0_1 : inout std_logic; p0_2 : inout std_logic; p0_3 : inout std_logic; p0_4 : inout std_logic; p0_5 : inout std_logic; p0_6 : inout std_logic; p0_7 : inout std_logic; p0_8 : inout std_logic; p0_9 : inout std_logic;! p0_10 : inout std_logic;! p0_11 : inout std_logic;! p0_12 : inout std_logic;! p0_13 : inout std_logic;! p0_14 : inout std_logic;! p0_15 : inout std_logic; tse : inout std_logic; p1_0 : inout std_logic; p1_1 : inout std_logic; p1_2 : inout std_logic; p1_3 : inout std_logic; p1_4 : inout std_logic; p1_5 : inout std_logic; p2_0 : inout std_logic; p2_1 : inout std_logic; p2_2 : inout std_logic; p2_3 : inout std_logic; p2_4 : inout std_logic; p2_5 : inout std_logic; p2_6 : inout std_logic; p2_7 : inout std_logic; p2_8 : inout std_logic; p2_9 : inout std_logic;! p2_10 : inout std_logic; p2_11 : inout std_logic );end XMC1200_T038;#architecture RTL of XMC1200_T038 isbegin ARMCORTEX_model: process ( : vss,vdd,p0_0,p0_1,p0_2,p0_3,p0_4,p0_5,p0_6,p0_7,< p0_8,p0_9,p0_10,p0_11,p0_12,p0_13,p0_14,p0_15,tse,2 p1_0,p1_1,p1_2,p1_3,p1_4,p1_5,p2_0,p2_1,= p2_2,p2_3,p2_4,p2_5,p2_6,p2_7,p2_8,p2_9,p2_10,p2_11 )  begin _ARM_class( clk ); end process;end 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:00000001FF noname.lst noname.hex noname.asm€„.AU1main.cè/*D * Copyright (C) 2015 Infineon Technologies AG. All rights reserved. *N * Infineon Technologies AG (Infineon) is supplying this software for use with * Infineon's microcontrollers.H * This file can be freely distributed within development tools that are$ * supporting such microcontrollers. *M * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIEDE * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OFO * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.O * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,7 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * *//** * @file * @date 20 May, 2015 * @version 1.0.0 * * @brief RGB LED Color Control *d * This example demonstrates how easily the color of the light emitted by an RGB LED (3-channel LED), * can be controlled by the BCCU in XMC1200. *= * For this example the XMC1200 Boot Kit (KIT_XMC12_BOOT_001)_ * and the Colour LED Card of the LED Lighting Application Kit (KIT_XMC1X_AK_LED_001) are used. * * Hardware setup:[ * To download and debug the project, connect USB to XMC1200 Boot Kit (KIT_XMC12_BOOT_001) * Micro USB connector.K * Connect the Colour LED Card to the XMC1200 Boot Kit via edge connector. * * Download and start project.O * LED1 on the Colour LED Card will initially change color from yellow to blue.Y * Then, LED1 will start cycling its color from white to magenta to cyan every 7 seconds. * * Following resources are used: * BCCU channel 0, 7 and 8% * PORT P0.4, P0.11 and P0.1 for LED1A * PORT P0.5, P0.6, P0.7, P0.8, P0.9, P0.10 as GPIO (unused LEDs) * System Timer (SYSTICK) * * History
 * * Version 1.0.0 Initial
 * */v/********************************************************************************************************************* * HEADER FILESv ********************************************************************************************************************/?#include //SFR declarations of the selected device#include #include #include #include #include )// BCCU Channels for PDM outputs to Ports#define R_LED1_CH BCCU0_CH0#define G_LED1_CH BCCU0_CH7#define B_LED1_CH BCCU0_CH84// Port Pins for PDM outputs to LED drivers (BCR421)#define R_LED1_PIN P0_4#define G_LED1_PIN P0_11#define B_LED1_PIN P0_1// Port Pins for unused LEDs#define R_LED2_PIN P0_5#define G_LED2_PIN P0_6#define B_LED2_PIN P0_7#define R_LED3_PIN P0_8#define G_LED3_PIN P0_9#define B_LED3_PIN P0_10v/********************************************************************************************************************* * CONFIGURATIONw *********************************************************************************************************************//* Clock configuration */%XMC_SCU_CLOCK_CONFIG_t clock_config ={0 .pclk_src = XMC_SCU_CLOCK_PCLKSRC_DOUBLE_MCLK, .fdiv = 0, .idiv = 1};/* BCCU configuration */-XMC_BCCU_GLOBAL_CONFIG_t bccu_global_config ={' .fclk_ps = 0x50, //800kHz @PCLK=64MHz+ .dclk_ps = 0xdb, //292.237KHz @PCLK=64MHz< .bclk_sel = XMC_BCCU_BCLK_MODE_NORMAL //200KHz @PCLK=64MHz};#XMC_BCCU_CH_CONFIG_t r_pdm_config ={2 .dim_sel = XMC_BCCU_CH_DIMMING_SOURCE_DE0 // DE0};#XMC_BCCU_CH_CONFIG_t g_pdm_config ={2 .dim_sel = XMC_BCCU_CH_DIMMING_SOURCE_DE0 // DE0};#XMC_BCCU_CH_CONFIG_t b_pdm_config ={2 .dim_sel = XMC_BCCU_CH_DIMMING_SOURCE_DE0 // DE0};'XMC_BCCU_DIM_CONFIG_t bccu_dim_config ={% .dim_div = 0x0 // immediate dimming};v/********************************************************************************************************************* * MAINw *********************************************************************************************************************/int main(void){f //----CLOCK-SETUP-----------------------------------------------------------------------------------$ XMC_SCU_CLOCK_Init(&clock_config);f //--------------------------------------------------------------------------------------------------B /* init unused LED output pins so that they will not light up */? XMC_GPIO_SetMode(R_LED2_PIN, XMC_GPIO_MODE_OUTPUT_PUSH_PULL);? XMC_GPIO_SetMode(G_LED2_PIN, XMC_GPIO_MODE_OUTPUT_PUSH_PULL);? XMC_GPIO_SetMode(B_LED2_PIN, XMC_GPIO_MODE_OUTPUT_PUSH_PULL);? XMC_GPIO_SetMode(R_LED3_PIN, XMC_GPIO_MODE_OUTPUT_PUSH_PULL);? XMC_GPIO_SetMode(G_LED3_PIN, XMC_GPIO_MODE_OUTPUT_PUSH_PULL);? XMC_GPIO_SetMode(B_LED3_PIN, XMC_GPIO_MODE_OUTPUT_PUSH_PULL); /* init PDM output pins */D XMC_GPIO_SetMode(R_LED1_PIN, XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1);D XMC_GPIO_SetMode(G_LED1_PIN, XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1);D XMC_GPIO_SetMode(B_LED1_PIN, XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT6);" /* BCCU Global Initialization */2 XMC_BCCU_GlobalInit(BCCU0, &bccu_global_config);n //----DIMMING&COLOR----------------------------------------------------------------------------------------- /* init dimming engine */1 XMC_BCCU_DIM_Init(BCCU0_DE0, &bccu_dim_config); /* enable dimming engine */F XMC_BCCU_EnableDimmingEngine(BCCU0, XMC_BCCU_CH_DIMMING_SOURCE_DE0);' /* set target dimming level to max */6 XMC_BCCU_DIM_SetTargetDimmingLevel(BCCU0_DE0, 1024);* /* effect the change in dimming level */? XMC_BCCU_StartDimming(BCCU0, XMC_BCCU_CH_DIMMING_SOURCE_DE0); /* init channels */- XMC_BCCU_CH_Init(R_LED1_CH, &r_pdm_config);- XMC_BCCU_CH_Init(G_LED1_CH, &g_pdm_config);- XMC_BCCU_CH_Init(B_LED1_CH, &b_pdm_config); /* Enable PDM channels*/2 XMC_BCCU_ConcurrentEnableChannels(BCCU0, 0x181);# /* set initial color to yellow */3 XMC_BCCU_CH_SetTargetIntensity(R_LED1_CH, 0x800);3 XMC_BCCU_CH_SetTargetIntensity(G_LED1_CH, 0x800);3 XMC_BCCU_CH_SetTargetIntensity(B_LED1_CH, 0x000);$ /* Set linear walk time for PDMs*/O XMC_BCCU_CH_SetLinearWalkPrescaler(R_LED1_CH, 0x0); // immediate color change5 XMC_BCCU_CH_SetLinearWalkPrescaler(G_LED1_CH, 0x0);5 XMC_BCCU_CH_SetLinearWalkPrescaler(B_LED1_CH, 0x0); /* Start linear walk */3 XMC_BCCU_ConcurrentStartLinearWalk(BCCU0, 0x181);n //----------------------------------------------------------------------------------------------------------2 /* check if previous color change is complete */3 while(XMC_BCCU_IsLinearWalkComplete (BCCU0, 0U)); /* set color to blue */3 XMC_BCCU_CH_SetTargetIntensity(R_LED1_CH, 0x000);3 XMC_BCCU_CH_SetTargetIntensity(G_LED1_CH, 0x000);3 XMC_BCCU_CH_SetTargetIntensity(B_LED1_CH, 0xFFF);$ /* Set linear walk time for PDMs*/Q XMC_BCCU_CH_SetLinearWalkPrescaler(R_LED1_CH, 0x1); // Linear walk time = 10 ms5 XMC_BCCU_CH_SetLinearWalkPrescaler(G_LED1_CH, 0x1);5 XMC_BCCU_CH_SetLinearWalkPrescaler(B_LED1_CH, 0x1); /* Start linear walk */3 XMC_BCCU_ConcurrentStartLinearWalk(BCCU0, 0x181);@ /* Set up system timer for a periodic 750us timer interrupt */ SysTick_Config(24000U); while(1) { } return 0;}/* 750us interrupt */void SysTick_Handler(void){ static uint8_t step = 0; /* Change to white */ if (++step == 16) {5 XMC_BCCU_CH_SetTargetIntensity(R_LED1_CH, 0x555);5 XMC_BCCU_CH_SetTargetIntensity(G_LED1_CH, 0x555);5 XMC_BCCU_CH_SetTargetIntensity(B_LED1_CH, 0x555);5 XMC_BCCU_ConcurrentStartLinearWalk(BCCU0, 0x181); } /* Change to magenta */ else if (step == 32) {5 XMC_BCCU_CH_SetTargetIntensity(R_LED1_CH, 0x800);5 XMC_BCCU_CH_SetTargetIntensity(G_LED1_CH, 0x000);5 XMC_BCCU_CH_SetTargetIntensity(B_LED1_CH, 0x800);5 XMC_BCCU_ConcurrentStartLinearWalk(BCCU0, 0x181); } /* Change to cyan */ else if (step == 48) {5 XMC_BCCU_CH_SetTargetIntensity(R_LED1_CH, 0x000);5 XMC_BCCU_CH_SetTargetIntensity(G_LED1_CH, 0x800);5 XMC_BCCU_CH_SetTargetIntensity(B_LED1_CH, 0x800);5 XMC_BCCU_ConcurrentStartLinearWalk(BCCU0, 0x181); step = 0; }} core_cm0.hÇO/**************************************************************************//** * @file core_cm0.hE * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File * @version V4.00 * @date 22. August 2014 * * @note *P ******************************************************************************/(/* Copyright (c) 2009 - 2014 ARM LIMITED All rights reserved.E Redistribution and use in source and binary forms, with or withoutN modification, are permitted provided that the following conditions are met:C - Redistributions of source code must retain the above copyrightB notice, this list of conditions and the following disclaimer.F - Redistributions in binary form must reproduce the above copyrightH notice, this list of conditions and the following disclaimer in theI documentation and/or other materials provided with the distribution.J - Neither the name of ARM nor the names of its contributors may be usedF to endorse or promote products derived from this software without' specific prior written permission. *N THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"L AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THEM IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSEJ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BEF LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, ORG CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OFK SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESSJ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER INJ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)M ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.P ---------------------------------------------------------------------------*/#if defined ( __ICCARM__ )P #pragma system_include /* treat file as system include file for MISRA check */#endif#ifndef __CORE_CM0_H_GENERIC#define __CORE_CM0_H_GENERIC#ifdef __cplusplus extern "C" {#endifD/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions2 CMSIS violates the following MISRA-C:2004 rules:H \li Required Rule 8.5, object/function definition in header file.
G Function definitions in header files are used to allow 'inlining'.Z \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
D Unions are used for effective representation of core registers.; \li Advisory Rule 19.7, Function-like macro defined.
@ Function-like macros are used to allow more efficient code. */P/*******************************************************************************$ * CMSIS definitionsP ******************************************************************************//** \ingroup Cortex_M0 @{ *//* CMSIS CM0 definitions */s#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */s#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */G#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \s __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */s#define __CORTEX_M (0x00) /*!< Cortex-M Core */#if defined ( __CC_ARM )s #define __ASM __asm /*!< asm keyword for ARM Compiler */s #define __INLINE __inline /*!< inline keyword for ARM Compiler */* #define __STATIC_INLINE static __inline#elif defined ( __GNUC__ )s #define __ASM __asm /*!< asm keyword for GNU Compiler */s #define __INLINE inline /*!< inline keyword for GNU Compiler */( #define __STATIC_INLINE static inline#elif defined ( __ICCARM__ )s #define __ASM __asm /*!< asm keyword for IAR Compiler */˜ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */( #define __STATIC_INLINE static inline#elif defined ( __TMS470__ )s #define __ASM __asm /*!< asm keyword for TI CCS Compiler */( #define __STATIC_INLINE static inline#elif defined ( __TASKING__ )s #define __ASM __asm /*!< asm keyword for TASKING Compiler */s #define __INLINE inline /*!< inline keyword for TASKING Compiler */( #define __STATIC_INLINE static inline#elif defined ( __CSMC__ ) #define __packedq #define __ASM _asm /*!< asm keyword for COSMIC Compiler */‹ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */( #define __STATIC_INLINE static inline#endif7/** __FPU_USED indicates whether an FPU is used or not., This core does not support an FPU at all*/#define __FPU_USED 0#if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFPd #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif#elif defined ( __GNUC__ )2 #if defined (__VFP_FP__) && !defined(__SOFTFP__)d #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif#elif defined ( __ICCARM__ ) #if defined __ARMVFP__d #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif#elif defined ( __TMS470__ )# #if defined __TI__VFP_SUPPORT____d #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif#elif defined ( __TASKING__ ) #if defined __FPU_VFP__b #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif(#elif defined ( __CSMC__ ) /* Cosmic */4 #if ( __CSMC__ & 0x400) // FPU present for parserb #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif#endif^#include /* standard types definitions */^#include /* Core Instruction Access */^#include /* Core Function Access */#ifdef __cplusplus}#endif!#endif /* __CORE_CM0_H_GENERIC */#ifndef __CMSIS_GENERIC#ifndef __CORE_CM0_H_DEPENDANT#define __CORE_CM0_H_DEPENDANT#ifdef __cplusplus extern "C" {#endif+/* check device defines and use defaults */"#if defined __CHECK_DEVICE_DEFINES #ifndef __CM0_REV* #define __CM0_REV 0x0000J #warning "__CM0_REV not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS' #define __NVIC_PRIO_BITS 2Q #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig' #define __Vendor_SysTickConfig 0W #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif#endifB/* IO definitions (access restrictions to peripheral registers) *//**2 \defgroup CMSIS_glob_defs CMSIS Global Defines0 IO Type Qualifiers are used6 \li to specify the access to peripheral variables.J \li for automatic generation of peripheral register debug information.*/#ifdef __cplusplus` #define __I volatile /*!< Defines 'read only' permissions */#else` #define __I volatile const /*!< Defines 'read only' permissions */#endif`#define __O volatile /*!< Defines 'write only' permissions */`#define __IO volatile /*!< Defines 'read / write' permissions *//*@} end of group Cortex_M0 */P/*******************************************************************************' * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick RegisterP ******************************************************************************/>/** \defgroup CMSIS_core_register Defines and Type DefinitionsM \brief Type definitions and defines for Cortex-M processor based devices.*/#/** \ingroup CMSIS_core_register8 \defgroup CMSIS_CORE Status and Control Registers+ \brief Core Register type definitions. @{ */P/** \brief Union type to access the Application Program Status Register (APSR). */ typedef union{ struct {#if (__CORTEX_M != 0x04)` uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */#else` uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */` uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */` uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */#endif` uint32_t Q:1; /*!< bit: 27 Saturation condition flag */` uint32_t V:1; /*!< bit: 28 Overflow condition code flag */` uint32_t C:1; /*!< bit: 29 Carry condition code flag */` uint32_t Z:1; /*!< bit: 30 Zero condition code flag */` uint32_t N:1; /*!< bit: 31 Negative condition code flag */` } b; /*!< Structure used for bit access */` uint32_t w; /*!< Type used for word access */ } APSR_Type;N/** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union{ struct {` uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */` uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */` } b; /*!< Structure used for bit access */` uint32_t w; /*!< Type used for word access */ } IPSR_Type;U/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union{ struct {` uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */#if (__CORTEX_M != 0x04)` uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */#else` uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */` uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */` uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */#endif` uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */` uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */` uint32_t Q:1; /*!< bit: 27 Saturation condition flag */` uint32_t V:1; /*!< bit: 28 Overflow condition code flag */` uint32_t C:1; /*!< bit: 29 Carry condition code flag */` uint32_t Z:1; /*!< bit: 30 Zero condition code flag */` uint32_t N:1; /*!< bit: 31 Negative condition code flag */` } b; /*!< Structure used for bit access */` uint32_t w; /*!< Type used for word access */ } xPSR_Type;A/** \brief Union type to access the Control Registers (CONTROL). */ typedef union{ struct {` uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */` uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */` uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */` uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */` } b; /*!< Structure used for bit access */` uint32_t w; /*!< Type used for word access */} CONTROL_Type;/*@} end of group CMSIS_CORE */#/** \ingroup CMSIS_core_registerG \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)7 \brief Type definitions for the NVIC Registers @{ */U/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */typedef struct{m __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31];n __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31];n __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31];n __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31]; uint32_t RESERVED4[64];n __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type;/*@} end of group CMSIS_NVIC */!/** \ingroup CMSIS_core_register6 \defgroup CMSIS_SCB System Control Block (SCB)G \brief Type definitions for the System Control Block Registers @{ */D/** \brief Structure type to access the System Control Block (SCB). */typedef struct{{ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */{ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ uint32_t RESERVED0;{ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */{ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */{ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1;{ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */{ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type;$/* SCB CPUID Register Definitions */#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */}#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */}#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */y#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */‚#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */~#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */|#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */x#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */~#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */z#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */6/* SCB Interrupt Control State Register Definitions */#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */{#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */~#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */z#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */~#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */z#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */~#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */z#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */~#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */z#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */{#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */{#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */€#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */|#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */{#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */F/* SCB Application Interrupt and Reset Control Register Definitions */}#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */y#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */}#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */{#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */}#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ƒ#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */-/* SCB System Control Register Definitions */}#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */y#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */}#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */y#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */{#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */4/* SCB Configuration Control Register Definitions */|#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */x#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */{#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */?/* SCB System Handler Control and State Register Definitions */‚#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */~#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask *//*@} end of group CMSIS_SCB */!/** \ingroup CMSIS_core_register; \defgroup CMSIS_SysTick System Tick Timer (SysTick)@ \brief Type definitions for the System Timer Registers. @{ */@/** \brief Structure type to access the System Timer (SysTick). */typedef struct{i __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */i __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */i __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */i __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */} SysTick_Type;3/* SysTick Control / Status Register Definitions */‚#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */~#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */‚#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */~#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */€#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */|#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */{#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */)/* SysTick Reload Register Definitions */#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */{#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */*/* SysTick Current Register Definitions */#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */{#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */./* SysTick Calibration Register Definitions */#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */{#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */~#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */z#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */{#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */"/*@} end of group CMSIS_SysTick */!/** \ingroup CMSIS_core_registerD \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)O \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)M are only accessible over DAP and not via processor. ThereforeB they are not covered by the Cortex-M0 header file. @{ */$/*@} end of group CMSIS_CoreDebug */#/** \ingroup CMSIS_core_register4 \defgroup CMSIS_core_base Core DefinitionsG \brief Definitions for base addresses, unions, and structures. @{ */*/* Memory mapping of Cortex-M0 Hardware */o#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */o#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */o#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */o#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */p#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */p#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */p#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct *//*@} */P/*******************************************************************************, * Hardware Abstraction Layer# Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions" - Core Register Access FunctionsP ******************************************************************************/O/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference*/W/* ########################## NVIC functions #################################### */*/** \ingroup CMSIS_Core_FunctionInterface5 \defgroup CMSIS_Core_NVICFunctions NVIC FunctionsM \brief Functions that manage interrupts and exceptions via the NVIC. @{ */R/* Interrupt Priorities are WORD accessible only under ARMv6M */R/* The following MACROS handle generation of the register offset and byte masks */P#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )P#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )P#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )%/** \brief Enable External InterruptV The function enables a device-specific interrupt in the NVIC interrupt controller.O \param [in] IRQn External interrupt number. Value cannot be negative. */3__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn){3 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));}&/** \brief Disable External InterruptW The function disables a device-specific interrupt in the NVIC interrupt controller.O \param [in] IRQn External interrupt number. Value cannot be negative. */4__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn){3 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));}!/** \brief Get Pending InterruptS The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt., \param [in] IRQn Interrupt number.; \return 0 Interrupt status is not pending.7 \return 1 Interrupt status is pending. */;__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn){N return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));}!/** \brief Set Pending Interrupt? The function sets the pending bit of an external interrupt.F \param [in] IRQn Interrupt number. Value cannot be negative. */7__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn){3 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));}#/** \brief Clear Pending InterruptA The function clears the pending bit of an external interrupt.O \param [in] IRQn External interrupt number. Value cannot be negative. */9__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn){Q NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */}"/** \brief Set Interrupt Priority3 The function sets the priority of an interrupt.> \note The priority cannot be set for every core interrupt., \param [in] IRQn Interrupt number.+ \param [in] priority Priority to set. */H__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority){ if(IRQn < 0) {Y SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |N (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } else {W NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |N (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }}"/** \brief Get Interrupt PriorityB The function reads the priority of an interrupt. The interruptC number can be positive to specify an external (device specific)C interrupt, or negative to specify an internal (core) interrupt.) \param [in] IRQn Interrupt number.] \return Interrupt Priority. Value is aligned automatically to the implemented= priority bits of the microcontroller. */9__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn){ if(IRQn < 0) {¡ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ else {¡ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */}/** \brief System ResetC The function initiates a system reset request to reset the MCU. */+__STATIC_INLINE void NVIC_SystemReset(void){q __DSB(); /* Ensure all outstanding memory accesses includedn buffered write are completed before reset */8 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |, SCB_AIRCR_SYSRESETREQ_Msk);g __DSB(); /* Ensure completion of memory access */U while(1); /* wait until reset */}'/*@} end of CMSIS_Core_NVICFunctions */j/* ################################## SysTick function ############################################ */*/** \ingroup CMSIS_Core_FunctionInterface; \defgroup CMSIS_Core_SysTickFunctions SysTick Functions4 \brief Functions that configure the System. @{ */!#if (__Vendor_SysTickConfig == 0)%/** \brief System Tick Configurationb The function initializes the System Timer and its interrupt, and starts the System Tick Timer.D Counter is in free running mode to generate periodic interrupts.? \param [in] ticks Number of ticks between two interrupts.+ \return 0 Function succeeded.( \return 1 Function failed.S \note When the variable __Vendor_SysTickConfig is set to 1, then thea function SysTick_Config is not included. In this case, the file device.hC must contain a vendor-specific implementation of this function. */7__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks){\ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */X SysTick->LOAD = ticks - 1; /* set reload register */g NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */c SysTick->VAL = 0; /* Load the SysTick Counter Value *// SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |/ SysTick_CTRL_TICKINT_Msk |i SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */X return (0); /* Function successful */}#endif*/*@} end of CMSIS_Core_SysTickFunctions */#ifdef __cplusplus}#endif##endif /* __CORE_CM0_H_DEPENDANT */#endif /* __CMSIS_GENERIC */system_xmc1200.hTO/****************************************************************************** * @file system_XMC1200.hM * @brief Device specific initialization for the XMC1300-Series according * to CMSIS * @version V1.2 * @date 19 Jul 2013 * * @noteI * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved. * * @parO * Infineon Technologies AG (Infineon) is supplying this software for use with  * Infineon’s microcontrollers. * I * This file can be freely distributed within development tools that are $ * supporting such microcontrollers. *  * * @parN * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIEDE * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OFO * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.O * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,7 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. *P ******************************************************************************//*O * *************************** Change history *********************************F * V1.1, 13 Dec 2012, PKB, Created this table, added extern and stdintJ * V1.2, 19 Jul 2013, PKB, Added header guard, BootROM header, C++ support */#ifndef SYSTEM_XMC1200_H#define SYSTEM_XMC1200_HP/******************************************************************************* * HEADER FILESQ *******************************************************************************/#include P/******************************************************************************* * GLOBAL VARIABLESQ *******************************************************************************/ extern uint32_t SystemCoreClock;P/******************************************************************************* * API PROTOTYPESQ *******************************************************************************/#ifdef __cplusplus extern "C" {#endif/** * @brief Initialize the system * */void SystemInit(void);/**! * @brief Initialize CPU settings * */void SystemCoreSetup(void);/** * @brief Initialize clock * */ void SystemCoreClockSetup(void);/**) * @brief Update SystemCoreClock variable * */!void SystemCoreClockUpdate(void);#ifdef __cplusplus}#endif#endif xmc1200.hN/****************************************************************************//**FCopyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.* ** @parN* Infineon Technologies AG (Infineon) is supplying this software for use with J* Infineon's microcontrollers. This file can be freely distributed within>* development tools that are supporting such microcontrollers.** @parJ* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIEDD* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OFN* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.N* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,6* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.*O******************************************************************************/i/****************************************************************************************************//** * @file XMC1200.h *D * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for# * XMC1200 from Infineon. *+ * @version V1.2.2 (Reference Manual v1.2) * @date 23. January 2015 *+ * @note Generated with SVDConv V2.86c c * from CMSIS SVD File 'XMC1200_Processed_SVD.xml' Version 1.2.2 (Reference Manual v1.2),i *******************************************************************************************************//** @addtogroup Infineon * @{ *//** @addtogroup XMC1200 * @{ */#ifndef XMC1200_H#define XMC1200_H#ifdef __cplusplus extern "C" {#endifV/* ------------------------- Interrupt Number Definition ------------------------ */typedef enum {V/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ SysTick_IRQn = -1, /*!< 15 System Tick Timer */V/* --------------------- XMC1200 Specific Interrupt Numbers --------------------- */O SCU_0_IRQn = 0, /*!< SCU SR0 Interrupt */O SCU_1_IRQn = 1, /*!< SCU SR1 Interrupt */O SCU_2_IRQn = 2, /*!< SCU SR2 Interrupt */O ERU0_0_IRQn = 3, /*!< ERU0 SR0 Interrupt */O ERU0_1_IRQn = 4, /*!< ERU0 SR1 Interrupt */O ERU0_2_IRQn = 5, /*!< ERU0 SR2 Interrupt */O ERU0_3_IRQn = 6, /*!< ERU0 SR3 Interrupt */ O USIC0_0_IRQn = 9, /*!< USIC SR0 Interrupt */O USIC0_1_IRQn = 10, /*!< USIC SR1 Interrupt */O USIC0_2_IRQn = 11, /*!< USIC SR2 Interrupt */O USIC0_3_IRQn = 12, /*!< USIC SR3 Interrupt */O USIC0_4_IRQn = 13, /*!< USIC SR4 Interrupt */O USIC0_5_IRQn = 14, /*!< USIC SR5 Interrupt */ O VADC0_C0_0_IRQn = 15, /*!< VADC SR0 Interrupt */O VADC0_C0_1_IRQn = 16, /*!< VADC SR1 Interrupt */O VADC0_G0_0_IRQn = 17, /*!< VADC SR2 Interrupt */O VADC0_G0_1_IRQn = 18, /*!< VADC SR3 Interrupt */O VADC0_G1_0_IRQn = 19, /*!< VADC SR4 Interrupt */O VADC0_G1_1_IRQn = 20, /*!< VADC SR5 Interrupt */ O CCU40_0_IRQn = 21, /*!< CCU40 SR0 Interrupt */O CCU40_1_IRQn = 22, /*!< CCU40 SR1 Interrupt */O CCU40_2_IRQn = 23, /*!< CCU40 SR2 Interrupt */O CCU40_3_IRQn = 24, /*!< CCU40 SR3 Interrupt */ O LEDTS0_0_IRQn = 29, /*!< LEDTS0 SR0 Interrupt */O LEDTS1_0_IRQn = 30, /*!< LEDTS1 SR0 Interrupt */ O BCCU0_0_IRQn = 31, /*!< BCCU0 SR0 Interrupt */ } IRQn_Type;&/** @addtogroup Configuration_of_CMSIS * @{ */V/* ================================================================================ */V/* ================ Processor and Core Peripheral Section ================ */V/* ================================================================================ */c/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */#define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */#define __MPU_PRESENT 0 /*!< MPU present or not */#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */3/** @} */ /* End of group Configuration_of_CMSIS */#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */#include "system_XMC1200.h" /*!< XMC1200 System */V/* ================================================================================ */V/* ================ Device Specific Peripheral Section ================ */V/* ================================================================================ */5/* Macro to modify desired bitfields of a register */E#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \@ ((uint32_t)mask)) | \O (reg & ((uint32_t)~((uint32_t)mask)))5/* Macro to modify desired bitfields of a register */3#define WR_REG_SIZE(reg, mask, pos, val, size) { \Euint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \Guint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \@uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \Fuint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \&reg = (uint##size##_t) (VAL2 | VAL4);\}./** Macro to read bitfields from a register */H#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos)./** Macro to read bitfields from a register */M#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \O (uint32_t)mask) >> pos) )%/** Macro to set a bit in register */9#define SET_BIT(reg, pos) (reg |= ((uint32_t)1<* development tools that are supporting such microcontrollers.** @parK* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIEDD* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OFN* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.L* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR3* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.*O******************************************************************************/O/* ============================ REVISION HISTORY ==============================> 1. Prakash Kalanjeri Balasubramanian , V0.1 , Initial draft> 2. Prakash Kalanjeri Balasubramanian , V0.2 , Label updatesK 3. Prakash Kalanjeri Balasubramanian , V1.0 , Made _Sbrk device agnostic< 3. Prakash Kalanjeri Balasubramanian , V1.1 , C++ supportO 3. Prakash Kalanjeri Balasubramanian , V1.2 , Restored compatibilty with old> project filesL 4. Prakash Kalanjeri Balasubramanian, V1.3 , Encapsulating everything inL this file for use only with4 GCCO ========================================================================= *//*J * This file contains stubs for standard C library functionality that must5 * typically be provided for the underlying platform. *O * All routines are WEAKLY defined. This creates an opportunity for applicationH * developers to override the provided implementation and define a final& * implementation for their platforms. */#if defined ( __GNUC__ )#include #include #include #ifdef __cplusplus extern "C" {#endifO/* ========================================================================= */O/* =========================== File I/O related ============================ */O/* ========================================================================= *//* * File open */F__attribute__((weak)) int _open(const char *name, int flags, int mode){ (void)flags; (void)mode; return -1;}/* * File position seek */B__attribute__((weak)) int _lseek(int file, int offset, int whence){ (void)file; (void)offset; (void)whence; return -1;}/* * File read */=__attribute__((weak)) int _read(int file, char *ptr, int len){ (void)file; (void)len; return 0;}/* * File write */A__attribute__((weak)) int _write(int file, char *buf, int nbytes){ return -1;}/* * File close */&__attribute__((weak)) int _close(void){ return -1;}/* * File status */;__attribute__((weak)) int _fstat(int file, struct stat *st){ (void)file; if(st) return -1; else return -2;}/* * File linking */=__attribute__((weak)) int _link(char *oldname, char *newname){ if (oldname == newname) return -1; else return -2;}/* * Unlinking directory entry */-__attribute__((weak)) int _unlink(char *name){ return -1;}O/* ========================================================================= */O/* =================== Dynamic memory management related =================== */O/* ========================================================================= *//* * Heap break (position) */4__attribute__((weak)) void *_sbrk(int RequestedSize){* /* Heap limits from linker script file */& extern unsigned int Heap_Bank1_Start;% extern unsigned int Heap_Bank1_Size;& unsigned char *CurrBreak, *NextBreak; unsigned int HeapSize;! static unsigned char *HeapBound;4 static unsigned char * heap= (unsigned char *)NULL;/ HeapSize = (unsigned int)(&Heap_Bank1_Size); /*E * If this is the first time malloc() was invoked, we start with the * begining of the heap. */" if(heap == (unsigned char *)NULL) {- heap = (unsigned char *)&Heap_Bank1_Start;4 HeapBound = (unsigned char *) (heap + HeapSize); }L /* Super duper algo to find out if we have memory for the latest request */ /* Given conditions are: */ /* 1. Latest break */ CurrBreak = heap;5 /* And 2. Potential break based on requested size */L NextBreak = (unsigned char *)( (((unsigned int)(heap)) + RequestedSize + 7)8 & 0xFFFFFFF8);G /* Return no memory condition if we sense we are crossing the limit */ if (NextBreak >= HeapBound )! return ((unsigned char *)NULL); else { heap = NextBreak; return CurrBreak; }}O/* ========================================================================= */O/* ====================== Process related ================================== */O/* ========================================================================= *//* * Process timing information */1__attribute__((weak)) int _times(struct tms *buf){ return -1;}/** * Waiting for a child process to complete */,__attribute__((weak)) int _wait(int *status){ return -1;}/* * Kill a process */0__attribute__((weak)) int _kill(int pid,int sig){ (void)pid; (void)sig; return -1;}/* * Forking a child process */%__attribute__((weak)) int _fork(void){ return -1;}/* * Process ID */'__attribute__((weak)) int _getpid(void){ return -1;}/* * Program/process exit */(__attribute__((weak)) void _exit(int rc){ (void)rc; while(1){}} /* Init */&__attribute__((weak)) void _init(void){}O/* ========================================================================= */O/* ======================= TERMIO related ================================== */O/* ========================================================================= *//* * Terminal type evaluation */+__attribute__((weak)) int _isatty(int file){ (void)file; return -1;}O/* ========================================================================= */O/* ================================= C++ =================================== */O/* ========================================================================= */void *__dso_handle = (void *)0;#ifdef __cplusplus}#endif#endif /* __GNUC__ */ xmc1_gpio.h¼/*D * Copyright (C) 2015 Infineon Technologies AG. All rights reserved. *N * Infineon Technologies AG (Infineon) is supplying this software for use with * Infineon's microcontrollers.H * This file can be freely distributed within development tools that are$ * supporting such microcontrollers. *M * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIEDE * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OFO * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.O * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,7 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * *//** * @file xmc1_gpio.h * @date 20 Feb, 2015 * @version 1.0.2 * * History
 * * Version 1.0.0 Initial
 */#ifndef XMC1_GPIO_H#define XMC1_GPIO_HP/******************************************************************************* * HEADER FILESQ *******************************************************************************/#include "xmc_common.h"#if UC_FAMILY == XMC1#include "xmc1_gpio_map.h"/**, * @addtogroup XMClib XMC Peripheral Library * @{ *//** * @addtogroup GPIO * @{ */P/******************************************************************************* * MACROSQ *******************************************************************************/\#define XMC_GPIO_PORT0 ((XMC_GPIO_PORT_t *) PORT0_BASE) /**< Port0 module base address */\#define XMC_GPIO_PORT1 ((XMC_GPIO_PORT_t *) PORT1_BASE) /**< Port1 module base address */\#define XMC_GPIO_PORT2 ((XMC_GPIO_PORT_t *) PORT2_BASE) /**< Port2 module base address */@#define XMC_GPIO_CHECK_PORT(port) ((port == XMC_GPIO_PORT0) || \@ (port == XMC_GPIO_PORT1) || \< (port == XMC_GPIO_PORT2))B#define XMC_GPIO_CHECK_OUTPUT_PORT(port) XMC_GPIO_CHECK_PORT(port)# A#define XMC_GPIO_CHECK_ANALOG_PORT(port) (port == XMC_GPIO_PORT2)M#define XMC_GPIO_CHECK_MODE(mode) ((mode == XMC_GPIO_MODE_INPUT_TRISTATE) ||\N (mode == XMC_GPIO_MODE_INPUT_PULL_DOWN) ||\L (mode == XMC_GPIO_MODE_INPUT_PULL_UP) ||\M (mode == XMC_GPIO_MODE_INPUT_SAMPLING) ||\V (mode == XMC_GPIO_MODE_INPUT_INVERTED_TRISTATE) ||\W (mode == XMC_GPIO_MODE_INPUT_INVERTED_PULL_DOWN) ||\U (mode == XMC_GPIO_MODE_INPUT_INVERTED_PULL_UP) ||\V (mode == XMC_GPIO_MODE_INPUT_INVERTED_SAMPLING) ||\O (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL) ||\T (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1) ||\T (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2) ||\T (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT3) ||\T (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4) ||\T (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT5) ||\T (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT6) ||\T (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7) ||\P (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN) ||\U (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT1) ||\U (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2) ||\U (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT3) ||\U (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT4) ||\U (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT5) ||\U (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6) ||\R (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7))# l#define XMC_GPIO_CHECK_INPUT_HYSTERESIS(hysteresis) ((hysteresis == XMC_GPIO_INPUT_HYSTERESIS_STANDARD) || \e (hysteresis == XMC_GPIO_INPUT_HYSTERESIS_LARGE))P/******************************************************************************* * ENUMSQ *******************************************************************************//**b * Configures input hysteresis mode of pin. Use type \a XMC_GPIO_INPUT_HYSTERESIS_t for this enum.U * Selecting the appropriate pad hysteresis allows optimized pad oscillation behavior" * for touch-sensing applications. */&typedef enum XMC_GPIO_INPUT_HYSTERESIS{H XMC_GPIO_INPUT_HYSTERESIS_STANDARD = 0x0U, /**< Standard hysteresis */E XMC_GPIO_INPUT_HYSTERESIS_LARGE = 0x4U /**< Large hysteresis */} XMC_GPIO_INPUT_HYSTERESIS_t;P/******************************************************************************* * DATA STRUCTURESQ *******************************************************************************//**[ * Structure points port hardware registers. Use type XMC_GPIO_PORT_t for this structure. */typedef struct XMC_GPIO_PORT {d __IO uint32_t OUT; /**< The port output register determines the value of a GPIO pin when it is@ selected by Pn_IOCRx as output */f __O uint32_t OMR; /**< The port output modification register contains control bits that make itn possible to individually set, reset, or toggle the logic state of a single port& line*/ __I uint32_t RESERVED0[2];l __IO uint32_t IOCR[4]; /**< The port input/output control registers select the digital output and input] driver functionality and characteristics of a GPIO port pin */ __I uint32_t RESERVED1;l __I uint32_t IN; /**< The logic level of a GPIO pin can be read via the read-only port input register1 Pn_IN */ __I uint32_t RESERVED2[6];C __IO uint32_t PHCR[2]; /**< Pad hysteresis control register */ __I uint32_t RESERVED3[6];k __IO uint32_t PDISC; /**< Pin Function Decision Control Register is to disable/enable the digital padM structure in shared analog and digital ports*/ __I uint32_t RESERVED4[3];8 __IO uint32_t PPS; /**< Pin Power Save Register */? __IO uint32_t HWSEL; /**< Pin Hardware Select Register */} XMC_GPIO_PORT_t;/**R * Structure initializes port pin. Use type XMC_GPIO_CONFIG_t for this structure. */typedef struct XMC_GPIO_CONFIG{Y XMC_GPIO_MODE_t mode; /**< Defines the direction and characteristics of a pin */^ XMC_GPIO_INPUT_HYSTERESIS_t input_hysteresis; /**< Defines input pad hysteresis of a pin */P XMC_GPIO_OUTPUT_LEVEL_t output_level; /**< Defines output level of a pin */} XMC_GPIO_CONFIG_t;P/******************************************************************************* * API PROTOTYPESQ *******************************************************************************//** * @brief Sets pad hysteresis._ * @param port Constant pointer pointing to GPIO port, to access hardware register Pn_PHCR." * @param pin Port pin number.g * @param hysteresis input hysteresis selection. Refer data structure @ref XMC_GPIO_INPUT_HYSTERESIS_t * for details. * * @return None * * \parDescription:
x * Sets port pin input hysteresis. It configures hardware registers Pn_PHCR.\a hysteresis is initially configured duringk * initialization in XMC_GPIO_Init(). Call this API to alter pad hysteresis as needed later in the program. * * \parRelated APIs:
 * None * * \parNote:
\ * Prior to this api, user has to configure port pin to input mode using XMC_GPIO_SetMode(). * */>void XMC_GPIO_SetInputHysteresis(XMC_GPIO_PORT_t *const port, 4 const uint8_t pin, O const XMC_GPIO_INPUT_HYSTERESIS_t hysteresis);/** * @} (end addtogroup GPIO) *//** * @} (end addtogroup XMClib) */#endif /* UC_FAMILY == XMC1 */#endif /* XMC1_GPIO_H */ xmc1_scu.h3/*D * Copyright (C) 2015 Infineon Technologies AG. All rights reserved. *N * Infineon Technologies AG (Infineon) is supplying this software for use with * Infineon's microcontrollers.H * This file can be freely distributed within development tools that are$ * supporting such microcontrollers. *v * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITEDi * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * w * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,OR CONSEQUENTIAL DAMAGES, FOR ANY REASON * WHATSOEVER. *//** * @file xmc1_scu.h * @date 20 Feb, 2015 * @version 1.0.2 * * History * * Version 1.0.0 Initial
, * Version 1.0.2 Documentation improved
 */#ifndef XMC1_SCU_H#define XMC1_SCU_Hv/********************************************************************************************************************* * HEADER FILESv ********************************************************************************************************************/#include "xmc_common.h"#if UC_FAMILY == XMC1/**, * @addtogroup XMClib XMC Peripheral Library * @{ */ /** * @addtogroup SCU * @{ */ v/********************************************************************************************************************* * ENUMSv ********************************************************************************************************************//**Y * Defines the cause of last reset. The cause of last reset gets automatically stored inv * the \a SCU_RSTSTAT register and can be checked by user software to determine the state of the system and for debug] * purpose. All the enum items are tabulated as per bits present in \a SCU_RSTSTAT register.K * Use type \a XMC_SCU_RESET_REASON_t for accessing these enum parameters. */!typedef enum XMC_SCU_RESET_REASON{s XMC_SCU_RESET_REASON_PORST = (1UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Power On reset. */q XMC_SCU_RESET_REASON_MASTER = (2UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Master reset. */} XMC_SCU_RESET_REASON_SW = (4UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Software initiated reset. */o XMC_SCU_RESET_REASON_LOCKUP = (8UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to CPU lockup. */p XMC_SCU_RESET_REASON_FLASH = (16UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to flash error. */m XMC_SCU_RESET_REASON_WATCHDOG = (32UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to watchdog. */o XMC_SCU_RESET_REASON_CLOCK_LOSS = (64UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to clock loss. */u XMC_SCU_RESET_REASON_PARITY_ERROR = (128UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos) /**< Reset due to RAM parity error. */} XMC_SCU_RESET_REASON_t;/**u * Defines the reset sources that can cause device reset. These enums can be used to configure reset source in resett * control \a RSTCON register which enables different reset sources to identify the reset cause. The \a SCU_RSTSTAT_ * register can be checked by user software to determine the state of the system and for debug\ * purpose. Use type \a XMC_SCU_SYSTEM_RESET_REQUEST_t for accessing these enum parameters. */)typedef enum XMC_SCU_SYSTEM_RESET_REQUEST{~ XMC_SCU_RESET_REQUEST_FLASH_ECC_ERROR = SCU_RESET_RSTCON_ECCRSTEN_Msk, /**< Reset when ECC double bit error occurs.*/w XMC_SCU_RESET_REQUEST_CLOCK_LOSS = SCU_RESET_RSTCON_LOCRSTEN_Msk, /**< Reset when loss of clock occurs.*/{ XMC_SCU_RESET_REQUEST_SRAM_PARITY_ERROR = SCU_RESET_RSTCON_SPERSTEN_Msk, /**< Reset when SRAM parity error occurs.*/ƒ XMC_SCU_RESET_REQUEST_USIC_SRAM_PARITY_ERROR = SCU_RESET_RSTCON_U0PERSTEN_Msk /**< Reset when USIC0 memory parity error occurs.*/!} XMC_SCU_SYSTEM_RESET_REQUEST_t; /**h * Defines list of events that can generate SCU interrupt. These enums can be used to configure events i * in \a SRMSK register for assertion of interrupt. All the enum items are tabulated as per bits presentj * in \a SRMSK register. Use type \a XMC_SCU_INTERRUPT_EVENT_t for accessing these enum parameters. TheseY * enums can also be used for checking the status of events from the \a SRSTAT register. */$typedef enum XMC_SCU_INTERRUPT_EVENT{k XMC_SCU_INTERRUPT_EVENT_WDT_WARN = SCU_INTERRUPT_SRMSK_PRWARN_Msk, /**< WDT pre-warning event. */h XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC = SCU_INTERRUPT_SRCLR_PI_Msk, /**< RTC periodic event. */e XMC_SCU_INTERRUPT_EVENT_RTC_ALARM = SCU_INTERRUPT_SRCLR_AI_Msk, /**< RTC alarm event. */l XMC_SCU_INTERRUPT_EVENT_VDDPI = SCU_INTERRUPT_SRMSK_VDDPI_Msk, /**< VDDP pre-warning event. */#if UC_SERIES != XMC11v XMC_SCU_INTERRUPT_EVENT_ACMP0 = SCU_INTERRUPT_SRMSK_ACMP0I_Msk, /**< Analog comparator-0 output event. */v XMC_SCU_INTERRUPT_EVENT_ACMP1 = SCU_INTERRUPT_SRMSK_ACMP1I_Msk, /**< Analog comparator-1 output event. */v XMC_SCU_INTERRUPT_EVENT_ACMP2 = SCU_INTERRUPT_SRMSK_ACMP2I_Msk, /**< Analog comparator-2 output event. */#endifb XMC_SCU_INTERRUPT_EVENT_VDROP = SCU_INTERRUPT_SRMSK_VDROPI_Msk, /**< VDROP event. */#if UC_SERIES != XMC11v XMC_SCU_INTERRUPT_EVENT_ORC0 = SCU_INTERRUPT_SRMSK_ORC0I_Msk, /**< Out of range comparator-0 event. */v XMC_SCU_INTERRUPT_EVENT_ORC1 = SCU_INTERRUPT_SRMSK_ORC1I_Msk, /**< Out of range comparator-1 event. */v XMC_SCU_INTERRUPT_EVENT_ORC2 = SCU_INTERRUPT_SRMSK_ORC2I_Msk, /**< Out of range comparator-2 event. */v XMC_SCU_INTERRUPT_EVENT_ORC3 = SCU_INTERRUPT_SRMSK_ORC3I_Msk, /**< Out of range comparator-3 event. */v XMC_SCU_INTERRUPT_EVENT_ORC4 = SCU_INTERRUPT_SRMSK_ORC4I_Msk, /**< Out of range comparator-4 event. */v XMC_SCU_INTERRUPT_EVENT_ORC5 = SCU_INTERRUPT_SRMSK_ORC5I_Msk, /**< Out of range comparator-5 event. */v XMC_SCU_INTERRUPT_EVENT_ORC6 = SCU_INTERRUPT_SRMSK_ORC6I_Msk, /**< Out of range comparator-6 event. */v XMC_SCU_INTERRUPT_EVENT_ORC7 = SCU_INTERRUPT_SRMSK_ORC7I_Msk, /**< Out of range comparator-7 event. */#endifj XMC_SCU_INTERRUPT_EVENT_LOCI = SCU_INTERRUPT_SRMSK_LOCI_Msk, /**< Loss of clock event. */p XMC_SCU_INTERRUPT_EVENT_PESRAM = SCU_INTERRUPT_SRMSK_PESRAMI_Msk, /**< PSRAM Parity error event. */ n XMC_SCU_INTERRUPT_EVENT_PUSIC = SCU_INTERRUPT_SRMSK_PEU0I_Msk, /**< USIC Parity error event. */w XMC_SCU_INTERRUPT_EVENT_FLASH_ERROR = SCU_INTERRUPT_SRMSK_FLECC2I_Msk, /**< Flash ECC double bit error event. */x XMC_SCU_INTERRUPT_EVENT_FLASH_COMPLETED = SCU_INTERRUPT_SRCLR_FLCMPLTI_Msk, /**< Flash operation completion event. */b XMC_SCU_INTERRUPT_EVENT_VCLIP = SCU_INTERRUPT_SRMSK_VCLIPI_Msk, /**< VCLIP event. */t XMC_SCU_INTERRUPT_EVENT_STDBYCLKFAIL = SCU_INTERRUPT_SRMSK_SBYCLKFI_Msk, /**< Standby clock failure event. */t XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED = SCU_INTERRUPT_SRMSK_RTC_CTR_Msk, /**< RTCCTR register update event. */x XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED = SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk, /**< RTCATIM0 register update event. */x XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED = SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk, /**< RTCATIM1 register update event. */v XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED = SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk, /**< RTCTIM0 register update event. */v XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED = SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk, /**< RTCTIM1 register update event. */x XMC_SCU_INTERRUPT_EVENT_TSE_DONE = SCU_INTERRUPT_SRMSK_TSE_DONE_Msk, /**< Temperature measurement Completion _ event. */ s XMC_SCU_INTERRUPT_EVENT_TSE_HIGH = SCU_INTERRUPT_SRMSK_TSE_HIGH_Msk, /**< Temperature too high event. */y XMC_SCU_INTERRUPT_EVENT_TSE_LOW = (int32_t)SCU_INTERRUPT_SRMSK_TSE_LOW_Msk, /**< Temperature too low event. */} XMC_SCU_INTERRUPT_EVENT_t;/**{ * Defines possible sources of RTC clock. These enums can be used to configure \a RTCCLKSEL bits of \a CLKCR Clock ControlX * Register. Use type \a XMC_SCU_CLOCK_RTCCLKSRC_t for accessing these enum parameters. */ $typedef enum XMC_SCU_CLOCK_RTCCLKSRC{s XMC_SCU_CLOCK_RTCCLKSRC_DCO2 = (0x0UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos), /**< RTC clock source is standby clock. */{ XMC_SCU_CLOCK_RTCCLKSRC_ERU_IOUT0 = (0x1UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos), /**< RTC clock source is external clock from a ERU0.IOUT0. */{ XMC_SCU_CLOCK_RTCCLKSRC_ACMP0_OUT = (0x2UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos), /**< RTC clock source is external clock from ` ACMP0.OUT. */{ XMC_SCU_CLOCK_RTCCLKSRC_ACMP1_OUT = (0x3UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos), /**< RTC clock source is external clock from _ ACMP1.OUT. */z XMC_SCU_CLOCK_RTCCLKSRC_ACMP2_OUT = (0x4UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos) /**< RTC clock source is external clock from _ ACMP2.OUT. */} XMC_SCU_CLOCK_RTCCLKSRC_t;/**y * Defines possible sources of peripheral clock (PCLK). These enums can be used to configure \a PCLKSEL bits of \a CLKCRd * Clock Control Register. Use type \a XMC_SCU_CLOCK_PCLKSRC_t for accessing these enum parameters. */ "typedef enum XMC_SCU_CLOCK_PCLKSRC{g XMC_SCU_CLOCK_PCLKSRC_MCLK = (0UL << SCU_CLK_CLKCR_PCLKSEL_Pos), /**< MCLK as the source for PCLK. */r XMC_SCU_CLOCK_PCLKSRC_DOUBLE_MCLK = (1UL << SCU_CLK_CLKCR_PCLKSEL_Pos) /**< Source of PCLK is twice the MCLK. */} XMC_SCU_CLOCK_PCLKSRC_t;/**ƒ * Defines th list of various sources that support gating of clock to peripherals. After a master reset, only core, memories, SCU a * and PORT peripheral are not clock gated. The rest of the peripherals are default clock gated.R * All the enum items are tabulated as per bits present in \a CGATSTAT0 register.O * Use type \a XMC_SCU_PERIPHERAL_CLOCK_t for accessing these enum parameters. */%typedef enum XMC_SCU_PERIPHERAL_CLOCK{c XMC_SCU_PERIPHERAL_CLOCK_VADC = SCU_CLK_CGATSTAT0_VADC_Msk, /**< VADC peripheral clock gate. */#if defined(CCU80)e XMC_SCU_PERIPHERAL_CLOCK_CCU80 = SCU_CLK_CGATSTAT0_CCU80_Msk, /**< CCU80 peripheral clock gate. */#endife XMC_SCU_PERIPHERAL_CLOCK_CCU40 = SCU_CLK_CGATSTAT0_CCU40_Msk, /**< CCU40 peripheral clock gate. */e XMC_SCU_PERIPHERAL_CLOCK_USIC0 = SCU_CLK_CGATSTAT0_USIC0_Msk, /**< USIC0 peripheral clock gate. */#if defined(BCCU0)e XMC_SCU_PERIPHERAL_CLOCK_BCCU0 = SCU_CLK_CGATSTAT0_BCCU0_Msk, /**< BCCU0 peripheral clock gate. */#endif#if defined(LEDTS0)g XMC_SCU_PERIPHERAL_CLOCK_LEDTS0 = SCU_CLK_CGATSTAT0_LEDTS0_Msk, /**< LEDTS0 peripheral clock gate. */#endif#if defined(LEDTS1)g XMC_SCU_PERIPHERAL_CLOCK_LEDTS1 = SCU_CLK_CGATSTAT0_LEDTS1_Msk, /**< LEDTS1 peripheral clock gate. */#endif#if defined(POSIF0)g XMC_SCU_PERIPHERAL_CLOCK_POSIF0 = SCU_CLK_CGATSTAT0_POSIF0_Msk, /**< POSIF0 peripheral clock gate. */#endif#if defined(MATH)c XMC_SCU_PERIPHERAL_CLOCK_MATH = SCU_CLK_CGATSTAT0_MATH_Msk, /**< MATH peripheral clock gate. */#endifa XMC_SCU_PERIPHERAL_CLOCK_WDT = SCU_CLK_CGATSTAT0_WDT_Msk, /**< WDT peripheral clock gate. */` XMC_SCU_PERIPHERAL_CLOCK_RTC = SCU_CLK_CGATSTAT0_RTC_Msk /**< RTC peripheral clock gate. */} XMC_SCU_PERIPHERAL_CLOCK_t;/**I * Defines different states used while changing the device sleep modes. N * Use type \a XMC_SCU_SLEEP_CLK_INSTR_t for accessing these enum parameters. */%typedef enum XMC_SCU_SLEEP_CLK_INSTR {k XMC_SCU_SLEEP_CLK_INSTR_ENTER = 0UL, /**< Enter sleep mode : In this state, a snapshot of clocks that arex active is taken. All peripheral clocks are disabled before sleep mode instruction (WFI) is executed. */d XMC_SCU_SLEEP_CLK_INSTR_EXIT , /**< Exit sleep mode : In this state, all the peripheral clocksP that were active before entering the sleep mode are enabled. */} XMC_SCU_SLEEP_CLK_INSTR_t;/** * Defines options for Capture/Compare unit timer slice trigger that enables synchronous start function available on the \a SCU,^ * \a CCUCON register. Use type \a XMC_SCU_CCU_TRIGGER_t for accessing these enum parameters. */ typedef enum XMC_SCU_CCU_TRIGGER{ ] XMC_SCU_CCU_TRIGGER_CCU40 = SCU_GENERAL_CCUCON_GSC40_Msk, /**< Trigger CCU40 peripheral. */#if defined(CCU80)] XMC_SCU_CCU_TRIGGER_CCU80 = SCU_GENERAL_CCUCON_GSC80_Msk, /**< Trigger CCU80 peripheral. */#endif} XMC_SCU_CCU_TRIGGER_t;v/********************************************************************************************************************* * DATA STRUCTURESv ********************************************************************************************************************//**^ * Defines a data structure for initializing the data of the supply voltage monitoring block.y * Supply voltage monitoring block consists of 2 detectors namely External voltage detector (VDEL) and External brownoutw * detector (BDE) in the EVR that are used to monitor the VDDP. \a VDEL detector compares the supply voltage against a# * pre-warning threshold voltage. Q * Use type \a XMC_SCU_SUPPLYMONITOR_t for accessing these structure parameters. */$typedef struct XMC_SCU_SUPPLYMONITOR{U uint32_t ext_supply_threshold; /**< External supply range (VDEL Range Select).\n4 \b Range:\np 00B sets threshold value to 2.25V, 01B sets threshold value to 3.0V andL 10B sets threshold value to 4.4V */_ uint32_t ext_supply_monitor_speed; /**< Speed of the voltage monitor(VDEL Timing Setting).\n7 \b Range: \ns 00B sets monitor speed typ 1µs - slowest response time, 01B sets monitors speed typ 500n, 10B sets monitor speed typ 250n, 11B sets monitor speedT with no delay - fastest response time. */W bool enable_prewarning_int; /**< Configure pre-warning interrupt generation.\nV \b Range: \a true to enable the interrupt.*/R bool enable_vdrop_int; /**< Configure VDROP interrupt generation. \nV \b Range: \a true to enable the interrupt.*/F bool enable_vclip_int; /**< Configure VCLIP interrupt . V \b Range: \a true to enable the interrupt.*/b bool enable_at_init; /**< Whether the monitor has to be enabled (VDEL unit Enable)B after initialization. \n] \b Range: \a true to enable after initialization.*/} XMC_SCU_SUPPLYMONITOR_t; /**U * Defines a data structure for initializing the data of the clock functional block.s * Clock functional block configures clock dividers, peripheral and RTC clock source by configuring corresponding , * bits in \a CLKCR clock control register.P * Use type \a XMC_SCU_CLOCK_CONFIG_t for accessing these structure parameters. */#typedef struct XMC_SCU_CLOCK_CONFIG{A XMC_SCU_CLOCK_PCLKSRC_t pclk_src; /**< Source of PCLK Clock.\n2 \b Range: \n T XMC_SCU_CLOCK_PCLKSRC_MCLK- PCLK as a MCLK, \n b XMC_SCU_CLOCK_PCLKSRC_DOUBLE_MCLK- PCLK as twice the MCLK. */A XMC_SCU_CLOCK_RTCCLKSRC_t rtc_src; /**< Source of RTC Clock.\n0 \b Range: \na XMC_SCU_CLOCK_RTCCLKSRC_DCO2- standby clock as RTC clock, \n i XMC_SCU_CLOCK_RTCCLKSRC_ERU_IOUT0- external clock from ERU0.IOUT0, \ni XMC_SCU_CLOCK_RTCCLKSRC_ACMP0_OUT- external clock from ACMP0.OUT, \n i XMC_SCU_CLOCK_RTCCLKSRC_ACMP1_OUT- external clock from ACMP1.OUT, \n d XMC_SCU_CLOCK_RTCCLKSRC_ACMP2_OUT- external clock from ACMP2.OUT& */P uint8_t fdiv; /**< Fractional divider selection(FDIV). \b Range: 0 to 255. */< uint8_t idiv; /**< Clock divider value(IDIV). \b Range:\n2 00H- Divider is bypassed,\n , 01H- MCLK = 32 MHz,\n + 02H- MCLK = 16 MHz,\n/ 03H- MCLK = 10.67 MHz,\n * 04H- MCLK = 8 MHz,\n- FEH- MCLK = 126 kHz,\n . FFH- MCLK = 125.5 kHz */} XMC_SCU_CLOCK_CONFIG_t;/**D * Defines the data structure for initializing the deep sleep mode.R * During deep sleep mode peripheral clock is disabled and flash is powered down.T * Use type \a XMC_SCU_CLOCK_DEEP_SLEEP_t for accessing these structure parameters. */'typedef struct XMC_SCU_CLOCK_DEEP_SLEEP{Z bool flash_power_down; /**< Whether the device flash memory has to be powered down> during deep sleep mode.\n ] \b Range: Set true to disable flash in deep sleep mode.*/c uint32_t clock_gating_mask; /**< Configures mask value of clocks to be gated during deep sleep.\ni \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t to get the bitmaske of the peripheral clocks. Multiple peripherals can be combined by@ using the \a OR operation.*/} XMC_SCU_CLOCK_DEEP_SLEEP_t; v/********************************************************************************************************************* * API Prototypesv ********************************************************************************************************************/#ifdef __cplusplus extern "C" {#endif/** * * @return None * * \parDescription
7 * Locks access to protected bit fields of the SCU.\n\n\ * The bit protection scheme prevents changing selected register bits by unauthorized code. [ * Bit protection scheme is enabled by writing 000000C3H to \a PASSWD register. By writing Z * this value, the API is setting the \a MODE bit field to bit protection enabled state.\n@ * List of Protected Register Bit Fields are mentioned below. \n * P * P * P * P * P * P * P * *
\a Register \a Bit fields
SCU_CLKCR FDIV, IDIV, PCLKSEL, RTCLKSEL
SCU_CGATSET0 All bits
SCU_CGATCLR0 All bits
SCU_ANAOFFSET ADJL_OFFSET
VADC0_ACCPROT0 All bits
VADC0_ACCPROT1 All bits
 *  * \parRelated APIs:
' * XMC_SCU_UnlockProtectedBits() \n\n\n */%void XMC_SCU_LockProtectedBits(void); /** * * @return None * * \parDescription
9 * Unlocks access to protected bit fields of the SCU.\n\n\ * The bit protection scheme prevents changing selected register bits by unauthorized code. u * Bit protection scheme can be temporarily(for 32 MCLK cycles) disabled by writing 000000C0H to \a PASSWD register. l * By writing this value, the API is setting the \a MODE bit field to bit protection disabled state. The APIH * waits for the protection to be disabled after changing the \a MODE.\ns * User can change the values of the protected bit fields within 32 MCLK cycles. After 32 MCLK cycles the lock will * be enabled automatically. @ * List of Protected Register Bit Fields are mentioned below. \n * P * P * P * P * P * P * P * *
\a Register \a Bit fields
SCU_CLKCR FDIV, IDIV, PCLKSEL, RTCLKSEL
SCU_CGATSET0 All bits
SCU_CGATCLR0 All bits
SCU_ANAOFFSET ADJL_OFFSET
VADC0_ACCPROT0 All bits
VADC0_ACCPROT1 All bits
 *  * \parRelated APIs:
% * XMC_SCU_LockProtectedBits() \n\n\n */'void XMC_SCU_UnlockProtectedBits(void);/** *^ * @param obj Pointer to data structure consisting voltage monitoring block configuration.\no * \b Range: Use type @ref XMC_SCU_SUPPLYMONITOR_t for detailed description of structure members. * * @return None * * \parDescription
0 * Initializes power supply monitoring unit.\n\nw * Supply voltage monitoring block consist of 2 detectors namely External voltage detector (VDEL) and External brownoutv * detector (BDE) in the EVR that are used to monitor the VDDP. \a VDEL detector compares the supply voltage against a * pre-warning threshold voltage \a ext_supply_threshold. The threshold level is programmable via register \a ANAVDEL.VDEL_SELECT. An interrupt~ * if enabled via \a enable_prewarning_int, will be triggered if a level below this threshold is detected and the flag, VDDPI,‰ * in SRRAW register bit is set. Similarly interrupts can be enabled for the events of VCLIP and prewarning, using the structure members,{ * \a enable_vclip_int and \a enable_prewarning_int. The handlers for these interrupts have to be explicitly defined using/ * the API XMC_SCU_INTERRUPT_SetEventHandler(). * \parRelated APIs:
, * XMC_SCU_INTERRUPT_SetEventHandler()\n\n\n */Cvoid XMC_SCU_SupplyMonitorInit(const XMC_SCU_SUPPLYMONITOR_t *obj);/** *F * @param lower_temp Lower threshold value for the die temperature.\n8 * \b Range: 0 to 65535(16 bit unsigned value).F * @param upper_temp Upper threshold value for the die temperature.\n8 * \b Range: 0 to 65535(16 bit unsigned value). * * @return None * * \parDescription
n * Configures upper and lower thresholds of die temperature as raw digital values into temperature sensor.\n\np * The API configures \a ANATSEIH and \a ANATSEIL registers for upper and lower die temperature threshold limits * respectively.\n. * It is recommended to use following steps:\nh * - Call \a XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.\nh * - Call \a XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values.\nU * - Finally call \a XMC_SCU_StartTempMeasurement to start temperature measurement.\n * * \parRelated APIs:
G * XMC_SCU_StopTempMeasurement(), XMC_SCU_StartTempMeasurement() \n\n\n */#if (UC_SERIES != XMC11)Tvoid XMC_SCU_SetRawTempLimits(const uint32_t lower_temp, const uint32_t upper_temp);t// /* API to program temperature limits in centigrade into temperature sensor unit */ // need to implement in futureT// void XMC_SCU_SetTempLimits(const uint32_t lower_temp, const uint32_t upper_temp);/** *O * @return XMC_SCU_STATUS_t Status of starting the temperature measurement.\nV * \b Range: Use type @ref XMC_SCU_STATUS_t to identify the result.\nV * XMC_SCU_STATUS_OK- Temperature measurement started successfully.\n4 * Always returns the above status. * * \parDescription
L * Starts die temperature measurement using internal temperature sensor.\n\nW * The API, enables die temperature measurement and waits for about 10000 cycles until X * temperature measurement result is available on \a SCU_ANALOG->ANATSEMON bit fields.\n. * It is recommended to use following steps:\nh * - Call \a XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.\nx * - Call \a XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values if it is needed.\nM * - Call \a XMC_SCU_StartTempMeasurement to start temperature measurement.\nF * - Read die temperature value using \a XMC_SCU_GetTemperature API.\n * \parRelated APIs:
] * XMC_SCU_StopTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_GetTemperature() \n\n\n */4XMC_SCU_STATUS_t XMC_SCU_StartTempMeasurement(void);/** * @return None  * * \parDescription
- * Stops the die temperature measurement.\n\nY * Die temperature measurement is stopped by disabling the sensor using \a TSE_EN bit of  * \a ANATSECTRL register. * \parRelated APIs:
^ * XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_GetTemperature() \n\n\n */'void XMC_SCU_StopTempMeasurement(void);/** *c * @return bool Result of checking whether the die temperature is more than the upper threshold.\ne * \b Range: \a false if temperature is below the upper threshold. \a true if temperature R * has exceeded the upper threshold configured in \a ANATSEIH register. * * \parDescription
G * Check if the temperature has exceeded the upper threshold value.\n\nk * The API checks for \a TSE_HIGH bit (TSE Compare High Temperature Event Status bit) of \a SRRAW register._ * The bit will be set when the \a TSE_MON value in \a ANATSEMON register exceeds the value of + * \a TSE_IH value in \a ANATSEIH register. * \parRelated APIs:
x * XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_GetTemperature(), XMC_SCU_LowTemperature() \n\n\n */#bool XMC_SCU_HighTemperature(void);/** *c * @return bool Result of checking whether the die temperature is less than the lower threshold.\nk * \b Range: \a false if temperature is higher than the lower threshold. \a true if temperature W * has dropped below the lower threshold configured in \a ANATSEIL register. * * \parDescription
L * Check if the temperature has dropped below the lower threshold value.\n\ni * The API checks for \a TSE_LOW bit (TSE Compare Low Temperature Event Status bit) of \a SRRAW register.c * The bit will be set when the \a TSE_MON value in \a ANATSEMON register drops below the value of + * \a TSE_IL value in \a ANATSEIL register. * \parRelated APIs:
y * XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_GetTemperature(), XMC_SCU_HighTemperature() \n\n\n */"bool XMC_SCU_LowTemperature(void);/**C * @return uint32_t Die temperature value. \b Range: 16 bit value. * * \parDescription
* * Provides the die temperature value.\n\nY * The API reads temperature measurement result from \a SCU_ANALOG->ANATSEMON bit fields. * \parRelated APIs:
_ * XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_HighTemperature() \n\n\n */&uint32_t XMC_SCU_GetTemperature(void);#endif /** * @return None * * \parDescription
# * Trigger device master reset.\n\nT * The API triggers master reset by setting the \a MRSTEN bit of \a RSTCON register.l * It also internally triggers system reset. Almost all the logics of the device are affected by this reset. * \parRelated APIs:
, * XMC_SCU_RESET_EnableResetRequest() \n\n\n */:__STATIC_INLINE void XMC_SCU_RESET_AssertMasterReset(void){3 SCU_RESET->RSTCON |= SCU_RESET_RSTCON_MRSTEN_Msk;}/** *> * @param request Reset source to trigger the device reset.\nb * \b Range: Use type @ref XMC_SCU_SYSTEM_RESET_REQUEST_t to identify the reset source.\nj * XMC_SCU_RESET_REQUEST_FLASH_ECC_ERROR- Reset when flash memory double bit error is detected.\nU * XMC_SCU_RESET_REQUEST_CLOCK_LOSS- Reset when loss of clock is detected.\n` * XMC_SCU_RESET_REQUEST_SRAM_PARITY_ERROR- Reset when SRAM parity error is detected.\nk * XMC_SCU_RESET_REQUEST_USIC_SRAM_PARITY_ERROR- Reset when USIC0 SRAM parity error is detected.\n * * @return None * * \parDescription
D * Configures trigger for system reset from the selected source.\n\nN * The API configures the reset source specific bit in the \a RSTCON register.L * Multiple reset sources can be combined using \a OR operation. By enablingS * the reset using this API will not trigger the reset. The reset will happen when + * the configured source event is detected. * \parRelated APIs:
+ * XMC_SCU_RESET_AssertMasterReset() \n\n\n */G__STATIC_INLINE void XMC_SCU_RESET_EnableResetRequest(uint32_t request){ SCU_RESET->RSTCON |= request;}/** *> * @return uint32_t Fast peripheral clock frequency in Hertz. * * \parDescription
r * Provides the clock frequency of peripherals on the peripheral bus that are using a shared functional clock.\n\n^ * The value is derived using the bitfield \a PCLKSEL from \a CLKCR register. Peripheral clockL * can have 2 times the frequency of system clock if the \a PCLKSEL is set.  * \parRelated APIs:
6 * XMC_SCU_CLOCK_SetFastPeripheralClockSource() \n\n\n */=uint32_t XMC_SCU_CLOCK_GetFastPeripheralClockFrequency(void);/** *1 * @param source Fast peripheral clock source.\n[ * \b Range: Use type @ref XMC_SCU_CLOCK_PCLKSRC_t to identify the clock source.\nK * XMC_SCU_CLOCK_PCLKSRC_MCLK- Use MCLK as the peripheral clock.\nc * XMC_SCU_CLOCK_PCLKSRC_DOUBLE_MCLK- peripheral clock will be 2 times the MCLK frequency. * * @return None * * \parDescription
2 * Configures the source of peripheral clock. \n\nR * The peripheral clock can be either same as MCLK or twice the frequency of MCLK. * \parRelated APIs:
9 * XMC_SCU_CLOCK_GetFastPeripheralClockFrequency() \n\n\n */Vvoid XMC_SCU_CLOCK_SetFastPeripheralClockSource(const XMC_SCU_CLOCK_PCLKSRC_t source);#ifdef __cplusplus}#endif/** * @} */ /** * @} */#endif /* UC_FAMILY == XMC1 */ #endif /* XMC1_SCU_H */ xmc_bccu.hŒ/*D * Copyright (C) 2015 Infineon Technologies AG. All rights reserved. *N * Infineon Technologies AG (Infineon) is supplying this software for use with * Infineon's microcontrollers.H * This file can be freely distributed within development tools that are$ * supporting such microcontrollers. *M * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIEDE * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OFO * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.O * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,7 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * *//** * @file xmc_bccu.h * @date 20 Feb, 2015 * @version 1.0.2 *+ * Detailed description of file:
@ * APIs for the functional blocks of BCCU have been defined:
 * -- GLOBAL configuration
U * -- Clock configuration, Function/Event configuration, Interrupt configuration
 * * History *" * Version 1.0.0 Initial draft
, * Version 1.0.2 Documentation improved
 */#ifndef XMC_BCCU_H#define XMC_BCCU_Hv/********************************************************************************************************************* * HEADER FILESv ********************************************************************************************************************/#include /**, * @addtogroup XMClib XMC Peripheral Library * @{ *//** * @addtogroup BCCU^ * @brief Brightness and Color Control Unit (BCCU) driver for the XMC1 microcontroller family. *y * The Brightness and Color Control Unit (BCCU) is a dimming control peripheral for LED lighting applications. The BCCUv * module can be used to control multiple LED channels. Every channel generates one-bit sigma-delta bit stream with a z * user adjustable 12-bit average value. The dimming engine changes the brightness gradually (exponential curve) to appearw * natural to the human eye. It supports color control by adjusting the relative intensity of selected channels using ay * linear walk scheme for smooth color changes. It also supports high-power multi-channel LED lamps by optionally packingz * the bitstream. The optional packer which decreases the average rate of output switching by enforcing a defined on-time.v * The BCCU module generates two trigger signals to the ADC (BCCU_TRIGOUT0 and BCCU_TRIGOU1) to start conversions in a} * synchronized manner. The module can also be used as a multi-channel digital-analog converter with low-pass filters on the t * outputs. The BCCU module supports 3 independent dimming engines, 9 independent channels, Trap functions and 2 ADC * triggering modes. *n * The driver is divided into global control (BCCU), channel control (BCCU_CH) and dimming control (BCCU_DIM). *  * BCCU features:h * -# Configuration structure XMC_BCCU_GLOBAL_CONFIG_t and initialization function XMC_BCCU_GlobalInit()x * -# Allows configuring of clock settings (Fast clock, Bit clock and Dimming clock). XMC_BCCU_SetFastClockPrescaler(), A * -# XMC_BCCU_SelectBitClock(), XMC_BCCU_SetDimClockPrescaler().P * -# Allows configuring global trigger settings. XMC_BCCU_ConfigGlobalTrigger()U * -# Allows enabling multiple channels together. XMC_BCCU_ConcurrentEnableChannels()> * -# Allows enabling single channel. XMC_BCCU_EnableChannel()O * -# Allows configuring global dimming level. XMC_BCCU_SetGlobalDimmingLevel()^ * -# Starts linear walk for multiple channels together. XMC_BCCU_ConcurrentStartLinearWalk().H * -# Starts linear walk for single channel. XMC_BCCU_StartLinearWalk().^ * -# Starts dimming for multiple dimming engines together. XMC_BCCU_ConcurrentStartDimming().H * -# Starts dimming for single dimming engine. XMC_BCCU_StartDimming(). * * BCCU_CH features:[ * -# Configuration structure (XMC_BCCU_CH_t and initialization function XMC_BCCU_CH_Init()E * -# Allows selecting dimming engine. XMC_BCCU_CH_SelectDimEngine().P * -# Allows setting target channel intensity. XMC_BCCU_CH_SetTargetIntensity().Z * -# Allows knowing the status of linear walk completion. XMC_BCCU_IsLinearWalkComplete()K * -# Allows setting flicker watchdog. XMC_BCCU_CH_EnableFlickerWatchdog().g * -# Allows configuring packer settings. XMC_BCCU_CH_EnablePacker(), XMC_BCCU_CH_SetPackerThreshold(),i * XMC_BCCU_CH_SetPackerOffCompare(), XMC_BCCU_CH_SetPackerOffCounte(), XMC_BCCU_CH_SetPackerOnCounter() I * -# Allows selecting dimming bypass. XMC_BCCU_CH_DisableDimmingBypass() * * BCCU_DIM features:] * -# Configuration structure (XMC_BCCU_DIM_t and initialization function XMC_BCCU_DIM_Init()[ * -# Allows setting target dimming engine intensity. XMC_BCCU_DIM_SetTargetDimmingLevel().% * XMC_BCCU_DIM_SetTargetDimmingLevelS * -# Allows knowing the status of dimming completion. XMC_BCCU_IsDimmingFinished()F * -# Allows configuring dimming divider. XMC_BCCU_DIM_SetDimDivider()E * -# Allows configuring dimming curve. XMC_BCCU_DIM_ConfigDimCurve() * - * Recommended programming sequence:  *
    a *
  1. Set output passive and active levels using XMC_BCCU_ConcurrentSetOutputPassiveLevel() or ) * XMC_BCCU_SetOutputPassiveLevel()
  2. E *
  3. Initializes global features using XMC_BCCU_GlobalInit()
  4. C *
  5. Initializes channel features using XMC_BCCU_CH_Init()
  6. B *
  7. Initializes dimming engine using XMC_BCCU_DIM_Init()
  8. c *
  9. Enable channels using XMC_BCCU_ConcurrentEnableChannels() or XMC_BCCU_EnableChannel()
  10. u *
  11. Enable dimming engines using XMC_BCCU_ConcurrentEnableDimmingEngine() or XMC_BCCU_EnableDimmingEngine()
  12. _ *
  13. Configure channel linear walk prescaler using XMC_BCCU_CH_SetLinearWalkPrescaler()
  14. J *
  15. Configure dimming divider using XMC_BCCU_DIM_SetDimDivider()
  16. W *
  17. Set target intensities of channels using XMC_BCCU_CH_SetTargetIntensity()
  18. a *
  19. Set target dim levels of dimming engines using XMC_BCCU_DIM_SetTargetDimmingLevel()
  20. x *
  21. Start linear walk of the channels using XMC_BCCU_ConcurrentStartLinearWalk() or XMC_BCCU_StartLinearWalk()
  22. u *
  23. Start dimming of the dimming engines using XMC_BCCU_ConcurrentStartDimming() or XMC_BCCU_StartDimming()
  24. ] *
  25. Know the status of linear walk completion using XMC_BCCU_IsLinearWalkComplete()
  26. P *
  27. Know the status of dimming completion XMC_BCCU_IsDimmingFinished()
  28.  * @{ */v/********************************************************************************************************************* * DEVICE SPECIFIC MACROSv ********************************************************************************************************************/#if defined (BCCU0)v/********************************************************************************************************************* * MACROSv ********************************************************************************************************************/V#define XMC_BCCU_MAJOR_VERSION (1U) /**< Major number of the driver version, which is,S \.\.\ e.g. 1.5.3.*/V#define XMC_BCCU_MINOR_VERSION (0U) /**< Minor number of the driver version, which is,S \.\.\ e.g. 1.5.3.*/V#define XMC_BCCU_PATCH_VERSION (2U) /**< Patch number of the driver version, which is,S \.\.\ e.g. 1.5.3.*/`#define XMC_BCCU_NO_OF_CHANNELS (9U) /**< Total number of channels available @ BCCU module */~#define XMC_BCCU_CHANNEL_MASK ((0x1 << XMC_BCCU_NO_OF_CHANNELS)-1) /* Maximum possible value for multiple channels; used only for \n xmc_assert() */g#define XMC_BCCU_NO_OF_DIM_ENGINE (3U) /**< Total number of dimming engines available @ BCCU module */z#define XMC_BCCU_DIM_ENGINE_MASK (((0x1 << XMC_BCCU_NO_OF_DIM_ENGINE)-1)) /* Maximum possible value for dimming engine; used \n only for xmc_assert() */v/********************************************************************************************************************* * ENUMSv ********************************************************************************************************************//**s * Defines the status of BCCU driver, to verify the related API calls. Use type \a XMC_BCCU_STATUS_t for this enum. */ typedef enum {G XMC_BCCU_STATUS_SUCCESS = 0U, /**< Operation completed successfully */> XMC_BCCU_STATUS_ERROR = 1U, /**< Operation has some errors */} XMC_BCCU_STATUS_t; /**1 * Provides the options to select bit clock mode. */typedef enum {Y XMC_BCCU_BCLK_MODE_NORMAL = 0U, /**< Normal Mode: Bit clock runs at 1/4 of fast clock */V XMC_BCCU_BCLK_MODE_FAST = 1U, /**< Fast Mode: Bit clock runs at same as fast clock */} XMC_BCCU_BCLK_MODE_t;/**/ * Provides the options to select trigger mode. */typedef enum {N XMC_BCCU_TRIGMODE0 = 0U, /**< Mode0: Trigger on Any Channel using OR logic */S XMC_BCCU_TRIGMODE1 = 1U, /**< Mode1: Trigger on Active channel using round-robin*/} XMC_BCCU_TRIGMODE_t;/**] * Provides the options to select trigger delay, and only be used if Bit clock in Normal mode */typedef enum {` XMC_BCCU_TRIGDELAY_NO_DELAY = 0U, /**< BCCU trigger occurs on channel trigger(without delay) */o XMC_BCCU_TRIGDELAY_QUARTER_BIT = 1U, /**< BCCU trigger occurs on 1/4 bit time delayed after channel trigger */l XMC_BCCU_TRIGDELAY_HALF_BIT = 2U, /**< BCCU trigger occurs on 1/2 bit time delayed after channel trigger */} XMC_BCCU_TRIGDELAY_t;/**. * Provides the options to select suspend mode */typedef enum {\ XMC_BCCU_SUSPEND_MODE_IGNORE = 0U, /**< Request ignored, and module cannot get suspended */} XMC_BCCU_SUSPEND_MODE_FREEZE = 1U, /**< All running channels gets stopped, and freeze into a last state (without safe stop)  */y XMC_BCCU_SUSPEND_MODE_SAFE_FREEZE = 2U, /**< All running channels gets stopped, and freeze into a last state (with safe stop) */} XMC_BCCU_SUSPEND_MODE_t;/**+ * Provides the options to select trap edge */typedef enum {T XMC_BCCU_TRAPEDGE_RISING = 0U, /**< Trap on rising edge of the BCCU.TRAPL signal */V XMC_BCCU_TRAPEDGE_FALLING = 1U, /**< Trap on falling edge of the BCCU.TRAPL signal */} XMC_BCCU_TRAPEDGE_t;/**5 * Provides the options to enable/disable the events.N * The members can be combined using 'OR' operator for multiple selection.
     */typedef enum {6 XMC_BCCU_EVENT_TIMER0 = 0x1U, /**< Trigger 0 event */6 XMC_BCCU_EVENT_TIMER1 = 0x2U, /**< Trigger 1 event */8 XMC_BCCU_EVENT_FIFOFULL = 0x4U, /**< FIFO Full event */: XMC_BCCU_EVENT_FIFOEMPTY = 0x8U, /**< FIFO Empty event */0 XMC_BCCU_EVENT_TRAP = 0x10U, /**< Trap event */} XMC_BCCU_EVENT_t;/**> * Provides the options to know the status of the event flags.N * The members can be combined using 'OR' operator for multiple selection.
     */typedef enum {I XMC_BCCU_EVENT_STATUS_TIMER0 = 0x1U, /**< Trigger 0 Event flag status */I XMC_BCCU_EVENT_STATUS_TIMER1 = 0x2U, /**< Trigger 1 Event flag status */K XMC_BCCU_EVENT_STATUS_FIFOFULL = 0x4U, /**< FIFO Full Event flag status */M XMC_BCCU_EVENT_STATUS_FIFOEMPTY = 0x8U, /**< FIFO Empty Event flag status */V XMC_BCCU_EVENT_STATUS_TRAP = 0x10U, /**< Trap Event flag status (Without Trap Set) */I XMC_BCCU_EVENT_STATUS_TRAP_STATE = 0x40U, /**< Trap state flag status */} XMC_BCCU_EVENT_STATUS_t;/**= * Provides the options to know the status of trap occurrence */typedef enum {Q XMC_BCCU_TRAP_STATUS_DEACTIVE = 0x0U, /**< BCCU module is not in a Trap State */K XMC_BCCU_TRAP_STATUS_ACTIVE = 0x1U, /**< BCCU module is in a Trap State */} XMC_BCCU_TRAP_STATUS_t;/**9 * Provides the options to know the current level of trap */typedef enum {: XMC_BCCU_TRAP_LEVEL_LOW = 0x0U, /**< BCCU.TRAPL is Low */< XMC_BCCU_TRAP_LEVEL_HIGH = 0x1U, /**< BCCU.TRAPL is High */} XMC_BCCU_TRAP_LEVEL_t;/**A * Provides the options to select flicker watchdog enable/disable */typedef enum {a XMC_BCCU_CH_FLICKER_WD_DS = 0U, /**< Disable: No control over a sigma-delta modulator output */i XMC_BCCU_CH_FLICKER_WD_EN = 1U, /**< Enable: Limit consecutive zeros at sigma-delta modulator output */} XMC_BCCU_CH_FLICKER_WD_t;/**k * Provides the options to select gating functionality enable/disable, and be used for peak-current control */typedef enum {^ XMC_BCCU_CH_GATING_FUNC_DISABLE = 0U, /**< Disable: No control over a BCCU module output */p XMC_BCCU_CH_GATING_FUNC_ENABLE = 1U, /**< Enable: External gating signal which controls BCCU module output */} XMC_BCCU_CH_GATING_FUNC_t;/**0 * Provides the options to bypass dimming engine */typedef enum {i XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_DISABLE = 0U, /**< Disable: Brightness = Dimming Level * Intensity */Y XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_ENABLE = 1U, /**< Enable: Brightness = Intensity */&} XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_t;/**E * Provides the options to select passive level of the channel output */ typedef enum{Y XMC_BCCU_CH_ACTIVE_LEVEL_HIGH = 0U, /**< Default passive level of the channel is low */Y XMC_BCCU_CH_ACTIVE_LEVEL_LOW = 1U, /**< Default passive level of the channel is high */} XMC_BCCU_CH_ACTIVE_LEVEL_t;/**. * Provides the options to select trigger edge */ typedef enum{f XMC_BCCU_CH_TRIG_EDGE_PASS_TO_ACT = 0U, /**< Trigger on output transition from passive to active */f XMC_BCCU_CH_TRIG_EDGE_ACT_TO_PASS = 1U, /**< Trigger on output transition from active to passive */} XMC_BCCU_CH_TRIG_EDGE_t;/**6 * Provides the options to select source of trap input */ typedef enum{0 XMC_BCCU_CH_TRAP_INA = 0x0U, /**< Trap INA */0 XMC_BCCU_CH_TRAP_INB = 0x1U, /**< Trap INB */0 XMC_BCCU_CH_TRAP_INC = 0x2U, /**< Trap INC */0 XMC_BCCU_CH_TRAP_IND = 0x3U, /**< Trap IND */0 XMC_BCCU_CH_TRAP_INE = 0x4U, /**< Trap INE */0 XMC_BCCU_CH_TRAP_INF = 0x5U, /**< Trap INF */0 XMC_BCCU_CH_TRAP_ING = 0x6U, /**< Trap ING */0 XMC_BCCU_CH_TRAP_INH = 0x7U, /**< Trap INH */0 XMC_BCCU_CH_TRAP_INI = 0x8U, /**< Trap INI */0 XMC_BCCU_CH_TRAP_INJ = 0x9U, /**< Trap INJ *// XMC_BCCU_CH_TRAP_INK = 0xAU, /**< Trap INK *// XMC_BCCU_CH_TRAP_INL = 0xBU, /**< Trap INL *// XMC_BCCU_CH_TRAP_INM = 0xCU, /**< Trap INM *// XMC_BCCU_CH_TRAP_INN = 0xDU, /**< Trap INN *// XMC_BCCU_CH_TRAP_INO = 0xEU, /**< Trap INO *// XMC_BCCU_CH_TRAP_INP = 0xFU, /**< Trap INP */} XMC_BCCU_CH_TRAP_IN_t;/**: * Provides the options to select edge for trap occurrence */ typedef enum{Y XMC_BCCU_CH_TRAP_EDGE_RISING = 0U, /**< Trap on rising edge of the BCCU.TRAPL signal */[ XMC_BCCU_CH_TRAP_EDGE_FALLING = 1U /**< Trap on falling edge of the BCCU.TRAPL signal */} XMC_BCCU_CH_TRAP_EDGE_t;/**X * Provides the options to select trigger output, and only be used in XMC_BCCU_TRIGMODE1 */typedef enum {O XMC_BCCU_CH_TRIGOUT0 = 0U, /**< Trigger occurrence on BCCU_TRIGOUT0 signal */O XMC_BCCU_CH_TRIGOUT1 = 1U, /**< Trigger occurrence on BCCU_TRIGOUT1 signal */} XMC_BCCU_CH_TRIGOUT_t;/**? * Provides the options to select dimming source of the channel */typedef enum {G XMC_BCCU_CH_DIMMING_SOURCE_GLOBAL = 7U, /**< Global Dimming Engine */? XMC_BCCU_CH_DIMMING_SOURCE_DE0 = 0U, /**< Dimming Engine 0 */? XMC_BCCU_CH_DIMMING_SOURCE_DE1 = 1U, /**< Dimming Engine 1 */? XMC_BCCU_CH_DIMMING_SOURCE_DE2 = 2U, /**< Dimming Engine 2 */} XMC_BCCU_CH_DIMMING_SOURCE_t;/**; * Provides the options to select exponential dimming curve */typedef enum {{ XMC_BCCU_DIM_CURVE_COARSE = 0U, /**< Coarse curve: Slope of the linear pieces doubles every time, when it passes specific 8 thresholds of 16, 32, 64, 128, 256, 512, 1024, 2048 */X XMC_BCCU_DIM_CURVE_FINE = 1U, /**< Fine Curve: More pieces and different line slopes */} XMC_BCCU_DIM_CURVE_t;v/********************************************************************************************************************* * DATA STRUCTURESv ********************************************************************************************************************//**M * Redefinition of BCCU module structure; pointer to bccu module base address */typedef BCCU_Type XMC_BCCU_t;/**] * Redefinition of BCCU module channel structure; pointer to bccu module channel Base address */#typedef BCCU_CH_Type XMC_BCCU_CH_t;/**k * Redefinition of BCCU module dimming engine structure; pointer to bccu module dimming engine base address */$typedef BCCU_DE_Type XMC_BCCU_DIM_t;)/*Anonymous structure/union guard start*/#if defined(__CC_ARM) #pragma push #pragma anon_unions#elif defined(__TASKING__) #pragma warning 586#endif/**2 * Configures a global setting of the BCCU module. */%typedef struct XMC_BCCU_GLOBAL_CONFIG{ union{ struct{[ uint32_t trig_mode:1; /**< Selects trigger Mode. Use type @ref XMC_BCCU_TRIGMODE_t */ uint32_t : 1;k uint32_t trig_delay:2; /**< Selects trigger delay between channel & module trigger. \n Use type @ref  XMC_BCCU_TRIGDELAY_t */ uint32_t : 12;_ uint32_t maxzero_at_output:12; /**< Configures maximum 0's allowed at modulator output */ };& uint32_t globcon; /* Not to use */ }; union{ struct{[ uint32_t fclk_ps:12; /**< Configures the ratio between fast clock and module clock */ uint32_t : 3;\ uint32_t bclk_sel:1; /**< Selects the bit clock. Use type @ref XMC_BCCU_BCLK_MODE_t */] uint32_t dclk_ps:12; /**< Configures the ratio between dimmer clock and module clock */ };& uint32_t globclk; /* Not to use */ };R uint32_t global_dimlevel; /**< Configures global dimming engine dimming level */} XMC_BCCU_GLOBAL_CONFIG_t;/**9 * Configures global trigger settings of the BCCU module. */#typedef struct XMC_BCCU_TRIG_CONFIG{i XMC_BCCU_TRIGMODE_t mode; /**< Selects global trigger mode which decides when to occur BCCU trigger */i XMC_BCCU_TRIGDELAY_t delay; /**< Selects global trigger delay between channel trigger & BCCU trigger */} uint16_t mask_chans; /**< Channel mask to configure trigger settings for multiple channels For example: } If channel 0 and 7, wants to configure then the channel mask is 01000 0001 = 0x81\n*/A uint16_t mask_trig_lines; /**< Trigger line mask */} XMC_BCCU_TRIG_CONFIG_t;/**2 * Configures channel settings of the BCCU module. */#ifdef DOXYGEN !typedef struct XMC_BCCU_CH_CONFIG{K uint32_t pack_thresh:3; /**< Configures packer threshold value of FIFO */? uint32_t pack_en:1; /**< Enables a packed output bitstream */| uint32_t dim_sel:3; /**< Selects a dimming engine source of the channel. \n Use type @ref XMC_BCCU_CH_DIMMING_SOURCE_t */{ uint32_t dim_bypass:1; /**< Selects dimming engine bypass enable. \n Use type @ref XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_t */\ uint32_t gate_en:1; /**< Selects gating enable. Use type @ref XMC_BCCU_CH_GATING_FUNC_t */i uint32_t flick_wd_en:1; /**< Selects flicker watchdog enable. Use type @ref XMC_BCCU_CH_FLICKER_WD_t */[ uint32_t trig_edge:1; /**< Selects trigger edge. Use type @ref XMC_BCCU_CH_TRIG_EDGE_t */{ uint32_t force_trig_en:1; /**< Selects force trigger enable; generates a trigger if modulator output do not change\n for  256 bclk cycles */{ uint32_t pack_offcmp_lev:8; /**< Configures a packer off-time compare level. When the off-time counter reaches this, the 9 measured on & off time counters are stored into FIFO */u uint32_t pack_oncmp_lev:8; /**< Configures a packer on-time compare level. When the on-time counter reaches this,\nc the measured on & off time counters are stored into FIFO */y uint32_t pack_offcnt_val:8; /**< Configures an initial packer off-time counter level, only if channel is disabled.
    W Controls phase shift of the modulator output */w uint32_t pack_oncnt_val:8; /**< Configures an initial packer on-time counter level, only if channel is disabled.
    W Controls phase shift of the modulator output */}XMC_BCCU_CH_CONFIG_t;#endif !typedef struct XMC_BCCU_CH_CONFIG{ union{ struct{O uint32_t pack_thresh:3; /**< Configures packer threshold value of FIFO */C uint32_t pack_en:1; /**< Enables a packed output bitstream */~ uint32_t dim_sel:3; /**< Selects a dimming engine source of the channel. \n Use type @ref XMC_BCCU_CH_DIMMING_SOURCE_t  */ uint32_t dim_bypass:1; /**< Selects dimming engine bypass enable. \n Use type @ref XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_t */` uint32_t gate_en:1; /**< Selects gating enable. Use type @ref XMC_BCCU_CH_GATING_FUNC_t */m uint32_t flick_wd_en:1; /**< Selects flicker watchdog enable. Use type @ref XMC_BCCU_CH_FLICKER_WD_t */_ uint32_t trig_edge:1; /**< Selects trigger edge. Use type @ref XMC_BCCU_CH_TRIG_EDGE_t */{ uint32_t force_trig_en:1; /**< Selects force trigger enable; generates a trigger if modulator output do not change\n  for 256 bclk cycles */ };$ uint32_t chconfig; /* Not to use */ }; union{ struct{w uint32_t pack_offcmp_lev:8; /**< Configures a packer off-time compare level. When the off-time counter reaches \nh this, the measured on & off time counters are stored into FIFO */ uint32_t : 8;y uint32_t pack_oncmp_lev:8; /**< Configures a packer on-time compare level. When the on-time counter reaches this,\nc the measured on & off time counters are stored into FIFO */ };$ uint32_t pkcmp; /* Not to use */ }; union{ struct{} uint32_t pack_offcnt_val:8; /**< Configures an initial packer off-time counter level, only if channel is disabled.
    W Controls phase shift of the modulator output */ uint32_t : 8;{ uint32_t pack_oncnt_val:8; /**< Configures an initial packer on-time counter level, only if channel is disabled.
    W Controls phase shift of the modulator output */ };% uint32_t pkcntr; /* Not to use */ };}XMC_BCCU_CH_CONFIG_t;/**9 * Configures dimming engine settings of the BCCU module. */#ifdef DOXYGEN"typedef struct XMC_BCCU_DIM_CONFIG{z uint32_t dim_div:10; /**< Configures a dimming clock divider, used to adjust the fade rate. If 0, the dimming level
    V as same as target dimming level on shadow transfer */w uint32_t dither_en:1; /**< Selects a dither enable. Dithering added for every dimming step if dimming level < 128. */r uint32_t cur_sel:1; /**< Selects a type of exponential curve. Use type @ref XMC_BCCU_DIM_CURVE_t. If dither
    N enabled, the configuration is being ignored */}XMC_BCCU_DIM_CONFIG_t;#endif"typedef struct XMC_BCCU_DIM_CONFIG{ union{ struct{~ uint32_t dim_div:10; /**< Configures a dimming clock divider, used to adjust the fade rate. If 0, the dimming level
    V as same as target dimming level on shadow transfer */ uint32_t : 6;{ uint32_t dither_en:1; /**< Selects a dither enable. Dithering added for every dimming step if dimming level < 128. */v uint32_t cur_sel:1; /**< Selects a type of exponential curve. Use type @ref XMC_BCCU_DIM_CURVE_t. If dither
    N enabled, the configuration is being ignored */ };" uint32_t dtt; /* Not to use */ };}XMC_BCCU_DIM_CONFIG_t;'/*Anonymous structure/union guard end*/#if defined(__CC_ARM) #pragma pop#elif defined(__TASKING__) #pragma warning restore#endifv/********************************************************************************************************************* * API Prototypesv ********************************************************************************************************************/#ifdef __cplusplus extern "C" {#endif/**I * @return Data structure (::XMC_DRIVER_VERSION_t) storing driver version * * \parDescription:
    2 * Return the version of the low level driver
     * * \parW * The function can be used to check application software compatibility with a specific# * version of the low level driver. */5XMC_DRIVER_VERSION_t XMC_BCCU_GetDriverVersion(void);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0v * @param config Pointer to constant bccu global configuration data structure. Use type @ref XMC_BCCU_GLOBAL_CONFIG_t. * * @return None * * \parDescription:
    } * Initializes three main clocks (fast clock, bit clock, dimmer clock) by using \a fclk_ps \a bclk_sel \a dclk_ps parameters ) * and writing into a GLOBCLK register.\nx * And also configures a trigger mode, trigger delay, maximum 0's allowed at modulator output by writing into a GLOBCON  * register.\n\n * * \parRelated APIs:
    0 * XMC_BCCU_CH_Init(), XMC_BCCU_DIM_Init()\n\n\n*/`void XMC_BCCU_GlobalInit (XMC_BCCU_t *const bccu, const XMC_BCCU_GLOBAL_CONFIG_t *const config);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0Z * @param mode Trigger mode selection. \b Range: XMC_BCCU_TRIGMODE0, XMC_BCCU_TRIGMODE1.\nM * 1. XMC_BCCU_TRIGMODE0 - Trigger on Any ChannelP * 2. XMC_BCCU_TRIGMODE1 - Trigger on Active channelf * @param delay Delay to avoid sampling during switching noise. Use type @ref XMC_BCCU_TRIGDELAY_t. \na * \b Range: XMC_BCCU_NO_DELAY, XMC_BCCU_QUARTER_BIT_DELAY, XMC_BCCU_HALF_BIT_DELAY. * * @return None * * \parDescription:
    v * Configures trigger mode and trigger delay by writing register bits GLOBCON.TM, GLOBCON.TRDEL. \a mode and \a delay e * parameters which decides when to trigger a conversion of vadc module for voltage measurement. \n\n * * \parRelated APIs:
    } * XMC_BCCU_EnableChannelTrigger(), XMC_BCCU_ReadGlobalTrigger(), XMC_BCCU_ConcurrentConfigTrigger(), XMC_BCCU_GlobalInit(), p * XMC_BCCU_ReadLastTrigChanNr(), XMC_BCCU_GetChannelOutputLvlAtLastTrigger(), XMC_BCCU_CH_ConfigTrigger()\n\n\n */pvoid XMC_BCCU_ConfigGlobalTrigger(XMC_BCCU_t *const bccu, XMC_BCCU_TRIGMODE_t mode, XMC_BCCU_TRIGDELAY_t delay);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0 *6 * @return Source of Trigger mode. \b Range: 0 or 1 \n9 * 0 - Trigger mode 0 (Trigger on Any Channel) \n= * 1 - Trigger mode 1 (Trigger on Active Channel)\n\n * \parDescription:
    | * Retrieves global trigger mode of the BCCU module by reading the register bit GLOBCON_TM. Use XMC_BCCU_TRIGMODE_t type to ! * validate a returned value.\n\n * * \parRelated APIs:
    b * XMC_BCCU_ConfigGlobalTrigger(), XMC_BCCU_ConcurrentConfigTrigger(), XMC_BCCU_GlobalInit()\n\n\n */L__STATIC_INLINE uint32_t XMC_BCCU_ReadGlobalTrigger (XMC_BCCU_t *const bccu){8 return (uint32_t)(bccu->GLOBCON & BCCU_GLOBCON_TM_Msk);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0J * @param input Trap input selection. Use type @ref XMC_BCCU_TRIGDELAY_t. s * \b Range: XMC_BCCU_TRIGDELAY_NO_DELAY, XMC_BCCU_TRIGDELAY_QUARTER_BIT, XMC_BCCU_TRIGDELAY_HALF_BIT. * * @return None * * \parDescription:
    x * Selects input of trap functionality by writing register bit GLOBCON_TRAPIS. The trap functionality is used to switch F * off the connected power devices when trap input becomes active.\n\n * * \parRelated APIs:
    q * XMC_BCCU_SetTrapEdge(), XMC_BCCU_ReadTrapInput(), XMC_BCCU_EnableTrap(), XMC_BCCU_ConcurrentEnableTrap()\n\n\n */Tvoid XMC_BCCU_SelectTrapInput (XMC_BCCU_t *const bccu, XMC_BCCU_CH_TRAP_IN_t input);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0 *5 * @return Source of trap input. \b Range: 0 to 15 \n+ * 0 - TRAPINA \n6 * 1 - TRAPINB and so on. \n * \parDescription:
    u * Retrieves trap input of the channel by reading the register bit GLOBCON_TRAPIS. Use XMC_BCCU_CH_TRAP_IN_t type to ! * validate a returned value.\n\n * * \parRelated APIs:
    # * XMC_BCCU_SelectTrapInput()\n\n\n */H__STATIC_INLINE uint32_t XMC_BCCU_ReadTrapInput (XMC_BCCU_t *const bccu){\ return (uint32_t)(( (bccu->GLOBCON) & BCCU_GLOBCON_TRAPIS_Msk) >> BCCU_GLOBCON_TRAPIS_Pos);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0N * @param edge Trap edge selection. Use type @ref XMC_BCCU_CH_TRAP_EDGE_t. \nV * \b Range: XMC_BCCU_CH_TRAP_EDGE_RISING, XMC_BCCU_CH_TRAP_EDGE_FALLING. * * @return None * * \parDescription:
    e * Selects active edge which detects trap on TRAPL signal by writing register bit GLOBCON_TRAPED.\n\n * * \parRelated APIs:
    t * XMC_BCCU_SelectTrapInput(), XMC_BCCU_ReadTrapEdge(), XMC_BCCU_EnableTrap(), XMC_BCCU_ConcurrentEnableTrap()\n\n\n */Qvoid XMC_BCCU_SetTrapEdge (XMC_BCCU_t *const bccu, XMC_BCCU_CH_TRAP_EDGE_t edge);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0 *3 * @return Trap edge selection. \b Range: 0 or 1 \n@ * 0 - XMC_BCCU_CH_TRAP_EDGE_RISING \nB * 1 - XMC_BCCU_CH_TRAP_EDGE_FALLING. \n * \parDescription:
    g * Retrieves trap edge by reading the register bit GLOBCON_TRAPED. Use XMC_BCCU_CH_TRAP_EDGE_t type to ! * validate a returned value.\n\n * * \parRelated APIs:
     * XMC_BCCU_SetTrapEdge()\n\n\n */G__STATIC_INLINE uint32_t XMC_BCCU_ReadTrapEdge (XMC_BCCU_t *const bccu){\ return (uint32_t)(( (bccu->GLOBCON) & BCCU_GLOBCON_TRAPED_Msk) >> BCCU_GLOBCON_TRAPED_Pos);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0P * @param mode Suspend mode selection. Use type @ref XMC_BCCU_SUSPEND_MODE_t. \ny * \b Range: XMC_BCCU_SUSPEND_MODE_IGNORE, XMC_BCCU_SUSPEND_MODE_FREEZE, XMC_BCCU_USPEND_MODE_SAFE_FREEZE. \n * * @return None * * \parDescription:
    F * Configures suspend mode by writing register bit GLOBCON_SUSCFG.\n\n * * \parRelated APIs:
    # * XMC_BCCU_ReadSuspendMode()\n\n\n */Wvoid XMC_BCCU_ConfigSuspendMode (XMC_BCCU_t *const bccu, XMC_BCCU_SUSPEND_MODE_t mode);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0 *4 * @return Trap edge selection. \b Range: 0, 1, 2 \n3 * 0 - XMC_BCCU_SUSPEND_MODE_IGNORE \n4 * 1 - XMC_BCCU_SUSPEND_MODE_FREEZE. \n8 * 2 - XMC_BCCU_USPEND_MODE_SAFE_FREEZE. \n * \parDescription:
    w * Retrieves the state of suspend mode by reading the register bit GLOBCON_TRAPIS. Use XMC_BCCU_SUSPEND_MODE_t type to ! * validate a returned value.\n\n * * \parRelated APIs:
    % * XMC_BCCU_ConfigSuspendMode()\n\n\n */J__STATIC_INLINE uint32_t XMC_BCCU_ReadSuspendMode (XMC_BCCU_t *const bccu){\ return (uint32_t)( ((bccu->GLOBCON) & BCCU_GLOBCON_SUSCFG_Msk) >> BCCU_GLOBCON_SUSCFG_Pos);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0 *< * @return Last triggered channel number. \b Range: 0 to 8\n$ * 0 - BCCU Channel 0\n/ * 1 - BCCU Channel 1 and so on.\n * \parDescription:
    i * Retrieves last triggered channel number of a BCCU module by reading the register bit GLOBCON_LTRS.\n\n * * \parRelated APIs:
    s * XMC_BCCU_GetChannelOutputLvlAtLastTrigger(), XMC_BCCU_ConfigGlobalTrigger(), XMC_BCCU_ConcurrentConfigTrigger(),< * XMC_BCCU_ReadGlobalTrigger(), XMC_BCCU_GlobalInit()\n\n\n */M__STATIC_INLINE uint32_t XMC_BCCU_ReadLastTrigChanNr (XMC_BCCU_t *const bccu){Y return (uint32_t)(( (bccu->GLOBCON) & BCCU_GLOBCON_LTRS_Msk) >> BCCU_GLOBCON_LTRS_Pos);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0] * @param threshold_no Number of consecutive zeroes at modulator output. \b Range: 0 to 4095. * * @return None * * \parDescription:
    v * Configures number of consecutive zeroes allowed at modulator output (flicker watch-dog number) by writing register  * bit GLOBCON_WDMBN.\n\n * * \parRelated APIs:
    ‰ * XMC_BCCU_CH_EnableFlickerWatchdog(), XMC_BCCU_ReadFlickerWDThreshold(), XMC_BCCU_CH_Init(), XMC_BCCU_CH_DisableFlickerWatchdog()\n\n\n */Tvoid XMC_BCCU_SetFlickerWDThreshold (XMC_BCCU_t *const bccu, uint32_t threshold_no);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0 *S * @return Number of consecutive zeroes at modulator output. \b Range: 0 to 4095 \n * \parDescription:
    t * Retrieves number of consecutive zeroes at modulator output (flicker watchdog number) by reading the register bit  * GLOBCON_WDMBN.\n\n * * \parRelated APIs:
    ˆ * XMC_BCCU_SetFlickerWDThreshold(), XMC_BCCU_CH_EnableFlickerWatchdog(), XMC_BCCU_CH_Init(), XMC_BCCU_CH_DisableFlickerWatchdog()\n\n\n */Q__STATIC_INLINE uint32_t XMC_BCCU_ReadFlickerWDThreshold (XMC_BCCU_t *const bccu){[ return (uint32_t)(( (bccu->GLOBCON) & BCCU_GLOBCON_WDMBN_Msk) >> BCCU_GLOBCON_WDMBN_Pos);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU04 * @param div Prescaler factor. \b Range: 0 to 4095. * * @return None * * \parDescription:
    x * Configures trigger functionality clock prescaler factor of a BCCU module by writing register bit GLOBCLK_FCLK_PS.\n\n * * \parRelated APIs:
    ] * XMC_BCCU_SetDimClockPrescaler(), XMC_BCCU_SelectBitClock(), XMC_BCCU_ReadFastClock()\n\n\n*/Kvoid XMC_BCCU_SetFastClockPrescaler (XMC_BCCU_t *const bccu, uint32_t div);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0 *0 * @return Prescaler factor. \b Range: 0 to 4095 * \parDescription:
    x * Retrieves fast clock prescaler factor of a BCCU module by reading the register bit GLOBCLK_FCLK_PS. The fast clock isa * derived from the bccu clock by prescaler factor i.e. fdclk = fbccu_clk / prescaler factor.\n\n * * \parRelated APIs:
    [ * XMC_BCCU_SetFastClockPrescaler(), XMC_BCCU_ReadBitClock(), XMC_BCCU_ReadDimClock()\n\n\n */H__STATIC_INLINE uint32_t XMC_BCCU_ReadFastClock (XMC_BCCU_t *const bccu){^ return (uint32_t)(((bccu->GLOBCLK) & BCCU_GLOBCLK_FCLK_PS_Msk) >> BCCU_GLOBCLK_FCLK_PS_Pos);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU04 * @param div Prescaler factor. \b Range: 0 to 4095. * * @return None * * \parDescription:
    i * Configures dimmer clock prescaler factor of a BCCU module by writing register bit GLOBCLK_DCLK_PS.\n\n * * \parRelated APIs:
    { * XMC_BCCU_DIM_SetDimDivider(), XMC_BCCU_SetFastClockPrescaler(), XMC_BCCU_SelectBitClock(), XMC_BCCU_ReadDimClock()\n\n\n */Jvoid XMC_BCCU_SetDimClockPrescaler (XMC_BCCU_t *const bccu, uint32_t div);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0 *0 * @return Prescaler factor. \b Range: 0 to 4095 * \parDescription:
    y * Retrieves dimmer clock prescaler factor of a BCCU module by reading the register bit GLOBCLK_DCLK_PS. The dim clock ism * derived from the bccu clock by prescaler factor. \n i.e. fdclk = fbccu_clk / prescaler factor.\n\n * * \parRelated APIs:
    [ * XMC_BCCU_SetDimClockPrescaler(), XMC_BCCU_ReadBitClock(), XMC_BCCU_ReadFastClock()\n\n\n */G__STATIC_INLINE uint32_t XMC_BCCU_ReadDimClock (XMC_BCCU_t *const bccu){^ return (uint32_t)(((bccu->GLOBCLK) & BCCU_GLOBCLK_DCLK_PS_Msk) >> BCCU_GLOBCLK_DCLK_PS_Pos);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0G * @param div Prescaler factor. Use type @ref XMC_BCCU_BCLK_MODE_t. \nP * \b Range: XMC_BCCU_BCLK_MODE_NORMAL or XMC_BCCU_BCLK_MODE_FAST. \n * @return None * * \parDescription:
    z * Configures modulator output (bit-time) clock prescaler factor of a BCCU module by writing register bit GLOBCLK_BCS.\n\n * * \parRelated APIs:
    c * XMC_BCCU_SetFastClockPrescaler(), XMC_BCCU_SetDimClockPrescaler(), XMC_BCCU_ReadBitClock()\n\n\n */Pvoid XMC_BCCU_SelectBitClock (XMC_BCCU_t *const bccu, XMC_BCCU_BCLK_MODE_t div);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0 *0 * @return Prescaler factor. \b Range: 0 or 1 \n= * 0 - XMC_BCCU_BCLK_MODE_NORMAL \n; * 1 - XMC_BCCU_BCLK_MODE_FAST \n * \parDescription:
    y * Retrieves modulator output (bit-time) clock prescaler factor of a BCCU module by reading the register bit GLOBCLK_BCS.B * Use XMC_BCCU_BCLK_MODE_t type to validate a returned value.\n\n * * \parRelated APIs:
    U * XMC_BCCU_SelectBitClock(), XMC_BCCU_ReadDimClock(), XMC_BCCU_ReadFastClock()\n\n\n */G__STATIC_INLINE uint32_t XMC_BCCU_ReadBitClock (XMC_BCCU_t *const bccu){V return (uint32_t)(((bccu->GLOBCLK) & BCCU_GLOBCLK_BCS_Msk) >> BCCU_GLOBCLK_BCS_Pos);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0: * @param mask Channel mask to enable multiple channels.\nc * For example: If channel 0, channel 7, channel 1 wants to enable at a same time, \n2 * then channel mask is 01000 0011 = 0x83\nr * ------------------------------------------------------------------------------------------------------\nU * | Chan8 | Chan7 | Chan6 | Chan5 | Chan4 | Chan3 | Chan2 | Chan1 | Chan0 |\nr * ------------------------------------------------------------------------------------------------------\n * * @return None * * \parDescription:
    Y * Enables multiple channels at a same time using \a mask by writing a register CHEN.\n\n * * \parRelated APIs:
    G * XMC_BCCU_EnableChannel(), XMC_BCCU_ConcurrentDisableChannels()\n\n\n */Ovoid XMC_BCCU_ConcurrentEnableChannels (XMC_BCCU_t *const bccu, uint32_t mask);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0; * @param mask Channel mask to disable multiple channels.\nd * For example: If channel 0, channel 7, channel 1 wants to disable at a same time, \n2 * then channel mask is 01000 0011 = 0x83\nr * ------------------------------------------------------------------------------------------------------\nU * | Chan8 | Chan7 | Chan6 | Chan5 | Chan4 | Chan3 | Chan2 | Chan1 | Chan0 |\nr * ------------------------------------------------------------------------------------------------------\n * * @return None * * \parDescription:
    Z * Disables multiple channels at a same time using \a mask by writing a register CHEN.\n\n * * \parRelated APIs:
    G * XMC_BCCU_ConcurrentEnableChannels(), XMC_BCCU_DisableChannel()\n\n\n */Pvoid XMC_BCCU_ConcurrentDisableChannels (XMC_BCCU_t *const bccu, uint32_t mask);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0? * @param chan_mask Channel mask to enable multiple channels.\nc * For example: If channel 0, channel 7, channel 1 wants to enable at a same time, \n2 * then channel mask is 01000 0011 = 0x83\nr * ------------------------------------------------------------------------------------------------------\nU * | Chan8 | Chan7 | Chan6 | Chan5 | Chan4 | Chan3 | Chan2 | Chan1 | Chan0 |\nr * ------------------------------------------------------------------------------------------------------\nT * @param level Passive level selection. Use type @ref XMC_BCCU_CH_ACTIVE_LEVEL_t.\nW * \b Range: XMC_BCCU_CH_ACTIVE_LEVEL_HIGH or XMC_BCCU_CH_ACTIVE_LEVEL_LOW * * @return None * * \parDescription:
    z * Configures passive levels of multiple channels at a same time using \a mask by writing a register bit CHOCON_CHyOP.\n\n * * \parRelated APIs:
    ) * XMC_BCCU_SetOutputPassiveLevel()\n\n\n */|void XMC_BCCU_ConcurrentSetOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_mask, XMC_BCCU_CH_ACTIVE_LEVEL_t level);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0M * @param mask Channel mask to enable multiple channels trap functionality.\nx * For example: If channel 0, channel 7, channel 1 wants to enable a trap functionality at a same time, \n2 * then channel mask is 01000 0011 = 0x83\nr * ------------------------------------------------------------------------------------------------------\nU * | Chan8 | Chan7 | Chan6 | Chan5 | Chan4 | Chan3 | Chan2 | Chan1 | Chan0 |\nr * ------------------------------------------------------------------------------------------------------\n * * @return None * * \parDescription:
    { * Enables multiple channels trap functionality at the same time using \a mask by writing a register bit CHOCON_CHyTPE.\n\n * * \parRelated APIs:
    t * XMC_BCCU_EnableTrap(), XMC_BCCU_ConcurrentDisableTrap(), XMC_BCCU_SelectTrapInput(), XMC_BCCU_SetTrapEdge()\n\n\n */Kvoid XMC_BCCU_ConcurrentEnableTrap (XMC_BCCU_t *const bccu, uint32_t mask);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0L * @param mask Channel mask to disable multiple channels trap functionality.y * For example: If channel 0, channel 7, channel 1 wants to disable a trap functionality at a same time, \n2 * then channel mask is 01000 0011 = 0x83\nr * ------------------------------------------------------------------------------------------------------\nU * | Chan8 | Chan7 | Chan6 | Chan5 | Chan4 | Chan3 | Chan2 | Chan1 | Chan0 |\nr * ------------------------------------------------------------------------------------------------------\n * * @return None * * \parDescription:
    | * Disables multiple channels trap functionality at the same time using \a mask by writing a register bit CHOCON_CHyTPE.\n\n * * \parRelated APIs:
    @ * XMC_BCCU_DisableTrap(), XMC_BCCU_ConcurrentEnableTrap()\n\n\n */Lvoid XMC_BCCU_ConcurrentDisableTrap (XMC_BCCU_t *const bccu, uint32_t mask);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0h * @param trig Pointer to a trigger configuration data structure. Use type @ref XMC_BCCU_TRIG_CONFIG_t.  * * @return None * * \parDescription:
    } * Configures global trigger settings: trigger mode, trigger delay, individual trigger lines and channel mask by writing a \n} * registers GLOBCON and CHTRIG. Trigger mode decides when to generate a BCCU trigger, trigger delay postpones the channel \n) * trigger by 1/4, or 1/2 bclk cycles\n\n * * \parRelated APIs:
    { * XMC_BCCU_ConfigGlobalTrigger(), XMC_BCCU_ReadLastTrigChanNr(), XMC_BCCU_ReadGlobalTrigger(), XMC_BCCU_GlobalInit()\n\n\n */]void XMC_BCCU_ConcurrentConfigTrigger (XMC_BCCU_t *const bccu, XMC_BCCU_TRIG_CONFIG_t *trig);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0Z * @param mask Channel mask to start a linear walk for multiple channels at a same time.\np * For example: If channel 0, channel 7, channel 1 wants to start a linear walk at a same time, \n2 * then channel mask is 01000 0011 = 0x83\nr * ------------------------------------------------------------------------------------------------------\nU * | Chan8 | Chan7 | Chan6 | Chan5 | Chan4 | Chan3 | Chan2 | Chan1 | Chan0 |\nr * ------------------------------------------------------------------------------------------------------\n * * @return None * * \parDescription:
    y * After channel initialization, the outcome of executing the API starts changing the color smoothly towards to target \nY * for multiple channels at a same time using \a mask by writing a register CHSTRCON.\n\n * * \parRelated APIs:
    I * XMC_BCCU_StartLinearWalk(), XMC_BCCU_ConcurrentAbortLinearWalk()\n\n\n */Pvoid XMC_BCCU_ConcurrentStartLinearWalk (XMC_BCCU_t *const bccu, uint32_t mask);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0Y * @param mask Channel mask to stop a linear walk for multiple channels at a same time.\np * For example: If channel 0, channel 7, channel 1 wants to abort a linear walk at a same time, \n2 * then channel mask is 01000 0011 = 0x83\nr * ------------------------------------------------------------------------------------------------------\nU * | Chan8 | Chan7 | Chan6 | Chan5 | Chan4 | Chan3 | Chan2 | Chan1 | Chan0 |\nr * ------------------------------------------------------------------------------------------------------\n * * @return None * * \parDescription:
    v * When the linear walk in progress, the outcome of executing the API is stopping the linear walk (i.e. color change) e * immediately for multiple channels at a same time using \a mask by writing a register CHSTRCON.\n\n * * \parRelated APIs:
    I * XMC_BCCU_AbortLinearWalk(), XMC_BCCU_ConcurrentStartLinearWalk()\n\n\n */Pvoid XMC_BCCU_ConcurrentAbortLinearWalk (XMC_BCCU_t *const bccu, uint32_t mask);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0V * @param mask Dimming engine mask to enable multiple dimming engine at a same time.\ng * For example: If dimming engine 0, channel 2 wants to enable a dimming at a same time, 3 * then dimming engine mask is 0101 = 0x03\n& * --------------------------\n * | DE2 | DE1 | DE0 |\n& * --------------------------\n * * @return None * * \parDescription:
    ` * Enables multiple dimming engines at a same time using \a mask by writing a register DEEN.\n\n * * \parRelated APIs:
    R * XMC_BCCU_EnableDimmingEngine(), XMC_BCCU_ConcurrentDisableDimmingEngine()\n\n\n */Tvoid XMC_BCCU_ConcurrentEnableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t mask);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0W * @param mask Dimming engine mask to disable multiple dimming engine at a same time.\nh * For example: If dimming engine 0, channel 2 wants to disable a dimming at a same time, 3 * then dimming engine mask is 0101 = 0x03\n& * --------------------------\n * | DE2 | DE1 | DE0 |\n& * --------------------------\n * * @return None * * \parDescription:
    a * Disables multiple dimming engines at a same time using \a mask by writing a register DEEN.\n\n * * \parRelated APIs:
    R * XMC_BCCU_DisableDimmingEngine(), XMC_BCCU_ConcurrentEnableDimmingEngine()\n\n\n */Uvoid XMC_BCCU_ConcurrentDisableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t mask);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0d * @param mask Dimming engine mask to start a dimming for multiple dimming engines at a same time.\nf * For example: If dimming engine 0, channel 2 wants to start a dimming at a same time, 3 * then dimming engine mask is 0101 = 0x03\n& * --------------------------\n * | DE2 | DE1 | DE0 |\n& * --------------------------\n * * @return None * * \parDescription:
    z * After dimming engine initialization, the outcome of executing the API starts changing the brightness towards to target ` * for multiple dimming engines at a same time using \a mask by writing a register DESTRCON.\n\n * * \parRelated APIs:
    C * XMC_BCCU_StartDimming(), XMC_BCCU_ConcurrentAbortDimming()\n\n\n */Mvoid XMC_BCCU_ConcurrentStartDimming (XMC_BCCU_t *const bccu, uint32_t mask);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0d * @param mask Dimming engine mask to abort a dimming for multiple dimming engines at a same time.\nf * For example: If dimming engine 0, channel 2 wants to abort a dimming at a same time, 3 * then dimming engine mask is 0101 = 0x03\n& * --------------------------\n * | DE2 | DE1 | DE0 |\n& * --------------------------\n * * @return None * * \parDescription:
    h * When the dimming in progress, the outcome of executing the API is stopping the dimming (i.e. fading) _ * immediately for specific dimming engine number \a dim_no by writing a register DESTRCON.\n\n * * \parRelated APIs:
    C * XMC_BCCU_AbortDimming(), XMC_BCCU_ConcurrentStartDimming()\n\n\n */Mvoid XMC_BCCU_ConcurrentAbortDimming (XMC_BCCU_t *const bccu, uint32_t mask);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0M * @param level Dimming level of global dimming engine. \b Range: 0 to 4095\n * * @return None * * \parDescription:
    { * Configures a global dimming level by writing a register GLOBDIM. This is useful only if global dimming engine selected. / * Otherwise the configuration is ignored. \n\n * * \parRelated APIs:
    - * XMC_BCCU_DIM_SetTargetDimmingLevel()\n\n\n */Nvoid XMC_BCCU_SetGlobalDimmingLevel (XMC_BCCU_t *const bccu, uint32_t level);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0l * @param event Event mask to enable multiple events at a time using ORed values of @ref XMC_BCCU_EVENT_t.\nx * For example: If XMC_BCCU_EVENT_TIMER0, XMC_BCCU_EVENT_TIMER1, XMC_BCCU_EVENT_FIFOEMPTY wants to enable e * at a same time,\n then event mask is = (XMC_BCCU_EVENT_TIMER0 | XMC_BCCU_EVENT_TIMER1 | + * XMC_BCCU_EVENT_FIFOEMPTY) \n * * @return None * * \parDescription:
     * Enables multiple interrupt events at a same time using ORed values of @ref XMC_BCCU_EVENT_t by writing a register EVIER.\n\n * * \parRelated APIs:
    $ * XMC_BCCU_DisableInterrupt()\n\n\n */V__STATIC_INLINE void XMC_BCCU_EnableInterrupt (XMC_BCCU_t *const bccu, uint32_t event){ bccu->EVIER |= event;}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0m * @param event Event mask to disable multiple events at a time using ORed values of @ref XMC_BCCU_EVENT_t.\nz * For example: If XMC_BCCU_EVENT_TIMER0, XMC_BCCU_EVENT_TIMER1, XMC_BCCU_EVENT_FIFOEMPTY wants to disable\nd * at a same time, then event mask is = (XMC_BCCU_EVENT_TIMER0 | XMC_BCCU_EVENT_TIMER1 | + * XMC_BCCU_EVENT_FIFOEMPTY) \n * * @return None * * \parDescription:
    € * Disables multiple interrupt events at a same time using ORed values of @ref XMC_BCCU_EVENT_t by writing a register EVIER.\n\n * * \parRelated APIs:
    # * XMC_BCCU_EnableInterrupt()\n\n\n */W__STATIC_INLINE void XMC_BCCU_DisableInterrupt (XMC_BCCU_t *const bccu, uint32_t event){$ bccu->EVIER &= (uint32_t)~(event);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0 *\ * @return Interrupt events flags at a same time using ORed values of @ref XMC_BCCU_EVENT_t. * \parDescription:
    y * Retrieves interrupt event flags at the same time using ORed values of @ref XMC_BCCU_EVENT_t by reading the register \n * EVFR. \n\n * * \parRelated APIs:
    * XMC_BCCU_SetEventFlag()\n\n\n */H__STATIC_INLINE uint32_t XMC_BCCU_ReadEventFlag (XMC_BCCU_t *const bccu){ return (bccu->EVFR);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0k * @param flag_type Event flag mask to configure multiple events flags at a time using ORed values of @ref  * XMC_BCCU_EVENT_STATUS_t.\n} * For example: If XMC_BCCU_EVENT_STATUS_TIMER0, XMC_BCCU_EVENT_STATUS_TIMER1, XMC_BCCU_EVENT_STATUS_FIFOEMPTY } * wants to configure at a same time, then event mask is = (XMC_BCCU_EVENT_STATUS_TIMER0 | XMC_BCCU_EVENT_STATUS_TIMER1 | * * XMC_BCCU_EVENT_STATUS_FIFOEMPTY) \n * * @return None * * \parDescription:
    Ž * Configures multiple interrupt event flags at a same time using ORed values of @ref XMC_BCCU_EVENT_STATUS_t by writing a register EVFSR.\n\n * * \parRelated APIs:
    < * XMC_BCCU_ClearEventFlag(), XMC_BCCU_ReadEventFlag()\n\n\n */W__STATIC_INLINE void XMC_BCCU_SetEventFlag (XMC_BCCU_t *const bccu, uint32_t flag_type){ bccu->EVFSR |= flag_type;}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0g * @param flag_type event Flag mask to clear multiple events flags at a time using ORed values of @ref  * XMC_BCCU_EVENT_STATUS_t.\n} * For example: If XMC_BCCU_EVENT_STATUS_TIMER0, XMC_BCCU_EVENT_STATUS_TIMER1, XMC_BCCU_EVENT_STATUS_FIFOEMPTY y * wants to clear at a same time, then event mask is = (XMC_BCCU_EVENT_STATUS_TIMER0 | XMC_BCCU_EVENT_STATUS_TIMER1 | * * XMC_BCCU_EVENT_STATUS_FIFOEMPTY) \n * * @return None * * \parDescription:
    w * Clears multiple interrupt event flags at a same time using ORed values of @ref XMC_BCCU_EVENT_STATUS_t by writing a  * register EVFSR.\n\n * * \parRelated APIs:
    * XMC_BCCU_SetEventFlag()\n\n\n */Y__STATIC_INLINE void XMC_BCCU_ClearEventFlag (XMC_BCCU_t *const bccu, uint32_t flag_type){ bccu->EVFCR |= flag_type;}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0G * @param chan_no Specific channel number to enable. \b Range: 0 to 8\n * * @return None * * \parDescription:
    U * Enables a specific channel number using \a chan_no by writing a register CHEN.\n\n * * \parRelated APIs:
    G * XMC_BCCU_ConcurrentEnableChannels(), XMC_BCCU_DisableChannel()\n\n\n */Gvoid XMC_BCCU_EnableChannel (XMC_BCCU_t *const bccu, uint32_t chan_no);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0H * @param chan_no Specific channel number to disable. \b Range: 0 to 8\n * * @return None * * \parDescription:
    V * Disables a specific channel number using \a chan_no by writing a register CHEN.\n\n * * \parRelated APIs:
    G * XMC_BCCU_ConcurrentDisableChannels(), XMC_BCCU_EnableChannel()\n\n\n */Hvoid XMC_BCCU_DisableChannel (XMC_BCCU_t *const bccu, uint32_t chan_no);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0X * @param chan_no Specific channel number to enable specific channel. \b Range: 0 to 8\nT * @param level Passive level selection. Use type @ref XMC_BCCU_CH_ACTIVE_LEVEL_t.\nW * \b Range: XMC_BCCU_CH_ACTIVE_LEVEL_HIGH or XMC_BCCU_CH_ACTIVE_LEVEL_LOW * * @return None * * \parDescription:
    l * Configures passive level of specific channel using \a chan_no by writing a register bit CHOCON_CHyOP.\n\n * * \parRelated APIs:
    3 * XMC_BCCU_ConcurrentSetOutputPassiveLevel()\n\n\n */pvoid XMC_BCCU_SetOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_no, XMC_BCCU_CH_ACTIVE_LEVEL_t level);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0` * @param chan_no Channel number to enable specific channel trap functionality. \b Range: 0 to 8 * * @return None * * \parDescription:
    l * Enables specific channel trap functionality using \a chan_no by writing a register bit CHOCON_CHyTPE.\n\n * * \parRelated APIs:
    t * XMC_BCCU_DisableTrap(), XMC_BCCU_ConcurrentEnableTrap(), XMC_BCCU_SelectTrapInput(), XMC_BCCU_SetTrapEdge()\n\n\n */Dvoid XMC_BCCU_EnableTrap (XMC_BCCU_t *const bccu, uint32_t chan_no);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0a * @param chan_no Channel number to disable specific channel trap functionality. \b Range: 0 to 8 * * @return None * * \parDescription:
    m * Disables specific channel trap functionality using \a chan_no by writing a register bit CHOCON_CHyTPE.\n\n * * \parRelated APIs:
    @ * XMC_BCCU_EnableTrap(), XMC_BCCU_ConcurrentDisableTrap()\n\n\n */Evoid XMC_BCCU_DisableTrap (XMC_BCCU_t *const bccu, uint32_t chan_no);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0P * @param chan_no Channel number to trigger a specific channel. \b Range: 0 to 8a * @param trig_line Trigger line number to trigger a vadc. Use type @ref XMC_BCCU_CH_TRIGOUT_t.\nJ * \b Range: XMC_BCCU_CH_TRIGOUT0 or XMC_BCCU_CH_TRIGOUT1 * * @return None * * \parDescription:
    a * Enables specific channel trigger using \a chan_no by writing a register bit CHOCON_CHyTPE.\n\n * * \parRelated APIs:
    f * XMC_BCCU_ConfigGlobalTrigger(), XMC_BCCU_DisableChannelTrigger(), XMC_BCCU_CH_ConfigTrigger()\n\n\n */ovoid XMC_BCCU_EnableChannelTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no, XMC_BCCU_CH_TRIGOUT_t trig_line);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0P * @param chan_no Channel number to trigger a specific channel. \b Range: 0 to 8 * * @return None * * \parDescription:
    b * Disables specific channel trigger using \a chan_no by writing a register bit CHOCON_CHyTPE.\n\n * * \parRelated APIs:
    ( * XMC_BCCU_EnableChannelTrigger()\n\n\n */Ovoid XMC_BCCU_DisableChannelTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no);/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..s * @param config Pointer to constant bccu channel configuration data structure. Use type @ref XMC_BCCU_CH_CONFIG_t. * * @return None * * \parDescription:
    z * Configures dimming engine source, dimming bypass selection, channel trigger edge, flicker watchdog selection and force z * trigger selection by using \a dim_sel, \a dim_bypass, \a trig_edge, \a flick_wd_en, \a force_trig_en by writing into a | * CHCONFIG register. And also configures packer settings: threshold, off and on compare levels, initial values of off & on H * counters, by writing into a CHCONFIG, PKCMP and PKCNTR registers.\n\n * * \parRelated APIs:
    3 * XMC_BCCU_GlobalInit(), XMC_BCCU_DIM_Init()\n\n\n */_void XMC_BCCU_CH_Init (XMC_BCCU_CH_t *const channel, const XMC_BCCU_CH_CONFIG_t *const config);/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..U * @param edge Output transition selection. Use type @ref XMC_BCCU_CH_TRIG_EDGE_t. \na * \b Range: XMC_BCCU_CH_TRIG_EDGE_PASS_TO_ACT or XMC_BCCU_CH_TRIG_EDGE_ACT_TO_PASS\nG * @param force_trig_en Forcing a trigger at output. \b Range: 0 or 1\nd * Generates a trigger if modulator output do not change for 256 bclk cycles\n  * * @return None * * \parDescription:
    j * Configures global trigger settings: trigger edge, force trigger enable by writing a register CHCONFIG. v * And also configures force trigger enable, generates a trigger if modulator output do not change for 256 bclk cycles * * \parRelated APIs:
    H * XMC_BCCU_ConfigGlobalTrigger(), XMC_BCCU_EnableChannelTrigger()\n\n\n */tvoid XMC_BCCU_CH_ConfigTrigger (XMC_BCCU_CH_t *const channel, XMC_BCCU_CH_TRIG_EDGE_t edge, uint32_t force_trig_en);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0R * @param chan_no Specific channel number to start color change \b Range: 0 to 8\n * * @return None * * \parDescription:
    w * After channel initialization, the outcome of executing the API starts changing the color smoothly towards to target / * by writing a register bit CHSTRCON_CHyS.\n\n * * \parRelated APIs:
    a * XMC_BCCU_AbortLinearWalk(), XMC_BCCU_CH_SetTargetIntensity(), XMC_BCCU_IsLinearWalkComplete(),- * XMC_BCCU_ConcurrentStartLinearWalk()\n\n\n */X__STATIC_INLINE void XMC_BCCU_StartLinearWalk (XMC_BCCU_t *const bccu, uint32_t chan_no){B bccu->CHSTRCON |= (uint32_t)(BCCU_CHSTRCON_CH0S_Msk << chan_no);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0Q * @param chan_no Specific channel number to stop color change \b Range: 0 to 8\n * * @return None * * \parDescription:
    v * When the linear walk in progress, the outcome of executing the API is stopping the linear walk (i.e. color change) b * immediately for specific channels number using \a mask by writing a register CHSTRCON_CHyA.\n\n * * \parRelated APIs:
    I * XMC_BCCU_StartLinearWalk(), XMC_BCCU_ConcurrentAbortLinearWalk()\n\n\n */X__STATIC_INLINE void XMC_BCCU_AbortLinearWalk (XMC_BCCU_t *const bccu, uint32_t chan_no){B bccu->CHSTRCON |= (uint32_t)(BCCU_CHSTRCON_CH0A_Msk << chan_no);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0d * @param chan_no Specific channel number to get an output level on last trigger. \b Range: 0 to 8\n *6 * @return Trap channel output level. \b Range: 0 or 1 * \parDescription:
    ~ * Retrieves output level of specific channel number when last trigger occurred by reading the register bit LTCHOL_LTOLy. \n\n * * \parRelated APIs:
    e * XMC_BCCU_ReadLastTrigChanNr(), XMC_BCCU_ConfigGlobalTrigger(), XMC_BCCU_ConcurrentConfigTrigger(),< * XMC_BCCU_ReadGlobalTrigger(), XMC_BCCU_GlobalInit()\n\n\n */m__STATIC_INLINE uint32_t XMC_BCCU_GetChannelOutputLvlAtLastTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no){T return (uint32_t)((bccu->LTCHOL & (BCCU_LTCHOL_LTOL0_Msk << chan_no)) >> chan_no);}/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..7 * @param clk_div Prescaler factor. \b Range: 0 to 1023 * * @return None * * \parDescription:
    c * configure the linear walker clock prescaler factor by writing register bit CHCONFIG_LINPRES.\n\n * */Yvoid XMC_BCCU_CH_SetLinearWalkPrescaler (XMC_BCCU_CH_t *const channel, uint32_t clk_div);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0^ * @param chan_no Channel number to know the linear walk completion status. \b Range: 0 to 8\n *p * @return Linear walk completion status. \b Range: 0-Completed or 1-intensity start changing towards the target * \parDescription:
    € * Retrieves linear walk completion status for specific channel using \a chan_no by reading the register bit CHSTRCON_CHyS. \n\n * * \parRelated APIs:
    E * XMC_BCCU_CH_SetTargetIntensity(), XMC_BCCU_StartLinearWalk()\n\n\n */a__STATIC_INLINE uint32_t XMC_BCCU_IsLinearWalkComplete (XMC_BCCU_t *const bccu, uint32_t chan_no){W return (uint32_t)((bccu->CHSTRCON & (BCCU_CHSTRCON_CH0S_Msk << chan_no)) >> chan_no);}/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..> * @param ch_int Target channel intensity. \b Range: 0 to 4095 * * @return None * * \parDescription:
    w * Configures target channel intensity by writing register INTS, only be written if no shadow transfer of linear walk. L * Use XMC_BCCU_IsLinearWalkComplete() to know shadow transfer finished \n\n * * \parRelated APIs:
    a * XMC_BCCU_IsLinearWalkComplete(), XMC_BCCU_StartLinearWalk(), XMC_BCCU_CH_ReadIntensity()\n\n\n */Tvoid XMC_BCCU_CH_SetTargetIntensity (XMC_BCCU_CH_t *const channel, uint32_t ch_int);/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.. *9 * @return Current channel intensity. \b Range: 0 or 4095 * \parDescription:
    G * Retrieves current channel intensity by reading the register INT.\n\n * * \parRelated APIs:
    ) * XMC_BCCU_CH_SetTargetIntensity()\n\n\n */Buint32_t XMC_BCCU_CH_ReadIntensity (XMC_BCCU_CH_t *const channel);/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..{ * @param thresh Packer threshold value of FIFO. It defines number of queue stages must be filled before output generator g * starts generating the pulses. Until that, only off-bits are generated at the output.\ns * @param off_comp Packer off-time compare level. When the off-time counter reaches this, the measured on off time 0 * counters are stored into FIFOr * @param on_comp Packer on-time compare level. When the on-time counter reaches this, the measured on & off time / * counters are stored into FIFO * * @return None * * \parDescription:
    w * Enables packer by writing register bit CHCONFIG_PEN. And also configures packer threshold, off and on compare levelsw * by writing register PKCMP. The main purpose of the packer is to decrease the average rate of switching of the output[ * signal, to decrease the load on external switching circuits and improve EMC behavior\n\n * * \parRelated APIs:
    ‰ * XMC_BCCU_CH_DisablePacker(), XMC_BCCU_CH_SetPackerThreshold(), XMC_BCCU_CH_SetPackerOffCompare(), XMC_BCCU_CH_SetPackerOnCompare\n\n\n */svoid XMC_BCCU_CH_EnablePacker (XMC_BCCU_CH_t *const channel, uint32_t thresh, uint32_t off_comp, uint32_t on_comp);/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.., * @param val Packer threshold value of FIFO * * @return None * * \parDescription:
    H * Configures packer threshold by writing register bit CHCONFIG_PKTH\n\n * * \parRelated APIs:
    m * XMC_BCCU_CH_SetPackerOffCompare(), XMC_BCCU_CH_SetPackerOnCompare, XMC_BCCU_CH_ReadPackerThreshold()\n\n\n */Qvoid XMC_BCCU_CH_SetPackerThreshold (XMC_BCCU_CH_t *const channel, uint32_t val);/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..{ * @param level Packer off-time compare level. When the off-time counter reaches this, the measured on & off time counters $ * are stored into FIFO * * @return None * * \parDescription:
    O * Configures packer off compare level by writing register bit PKCMP_OFFCMP\n\n * * \parRelated APIs:
    k * XMC_BCCU_CH_SetPackerThreshold(), XMC_BCCU_CH_SetPackerOnCompare(), XMC_BCCU_CH_SetPackerOffCounter(), + * XMC_BCCU_CH_ReadPackerOffCompare()\n\n\n */Tvoid XMC_BCCU_CH_SetPackerOffCompare (XMC_BCCU_CH_t *const channel, uint32_t level);/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..y * @param level Packer on-time compare level. When the on-time counter reaches this, the measured on & off time counters $ * are stored into FIFO * * @return None * * \parDescription:
    M * Configures packer on compare level by writing register bit PKCMP_ONCMP\n\n * * \parRelated APIs:
    k * XMC_BCCU_CH_SetPackerThreshold(), XMC_BCCU_CH_SetPackerOffCompare(), XMC_BCCU_CH_SetPackerOnCounter(), * * XMC_BCCU_CH_ReadPackerOnCompare()\n\n\n */Svoid XMC_BCCU_CH_SetPackerOnCompare (XMC_BCCU_CH_t *const channel, uint32_t level);/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.. *) * @return Packer threshold value of FIFO * \parDescription:
    R * Retrieves packer threshold value by reading the register bit CHCONFIG_PKTH.\n\n * * \parRelated APIs:
    ) * XMC_BCCU_CH_SetPackerThreshold()\n\n\n */W__STATIC_INLINE uint32_t XMC_BCCU_CH_ReadPackerThreshold (XMC_BCCU_CH_t *const channel){E return (uint32_t)((channel->CHCONFIG) & BCCU_CH_CHCONFIG_PKTH_Msk);}/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.. *u * @return Packer off-time compare level. When the off-time counter reaches this, the measured on & off time counters * are stored into FIFO * \parDescription:
    S * Retrieves packer off compare level by reading the register bit PKCMP_OFFCMP.\n\n * * \parRelated APIs:
    * * XMC_BCCU_CH_SetPackerOffCompare()\n\n\n */X__STATIC_INLINE uint32_t XMC_BCCU_CH_ReadPackerOffCompare (XMC_BCCU_CH_t *const channel){A return (uint32_t)((channel->PKCMP) & BCCU_CH_PKCMP_OFFCMP_Msk);}/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.. *T * @return Packer on-time compare level. When the on-time counter reaches this,
    C * the measured on & off time counters are stored into FIFO * \parDescription:
    Q * Retrieves packer on compare level by reading the register bit PKCMP_ONCMP.\n\n * * \parRelated APIs:
    ) * XMC_BCCU_CH_SetPackerOnCompare()\n\n\n */W__STATIC_INLINE uint32_t XMC_BCCU_CH_ReadPackerOnCompare (XMC_BCCU_CH_t *const channel){] return (uint32_t)(((channel->PKCMP) & BCCU_CH_PKCMP_ONCMP_Msk) >> BCCU_CH_PKCMP_ONCMP_Pos);}/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.. * * @return None * * \parDescription:
    F * Disables packer by clearing writing register bit CHCONFIG_PEN. \n\n * * \parRelated APIs:
    # * XMC_BCCU_CH_EnablePacker()\n\n\n */>void XMC_BCCU_CH_DisablePacker (XMC_BCCU_CH_t *const channel);/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..s * @param cnt_val Configures an initial packer off-time counter level, only if channel is disabled. Controls phase / * shift of the modulator output * * @return None * * \parDescription:
    Y * Configures packer initial off counter value by writing register bit PKCNTR_OFFCNTVAL\n6 * Note: Shall only be called if channel disabled.\n\n * * \parRelated APIs:
    L * XMC_BCCU_CH_SetPackerOnCounter(), XMC_BCCU_CH_SetPackerOffCompare()\n\n\n */Vvoid XMC_BCCU_CH_SetPackerOffCounter (XMC_BCCU_CH_t *const channel, uint32_t cnt_val);/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..x * @param cnt_val Configures an initial packer on-time counter level, only if channel is disabled. Controls phase shift ) * of the modulator output * * @return None * * \parDescription:
    W * Configures packer initial on counter value by writing register bit PKCNTR_ONCNTVAL\n6 * Note: Shall only be called if channel disabled.\n\n * * \parRelated APIs:
    L * XMC_BCCU_CH_SetPackerOffCounter(), XMC_BCCU_CH_SetPackerOnCompare()\n\n\n */Uvoid XMC_BCCU_CH_SetPackerOnCounter (XMC_BCCU_CH_t *const channel, uint32_t cnt_val);/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1..h * @param sel Selects a dimming engine source of the channel. Use type @ref XMC_BCCU_CH_DIMMING_SOURCE_t * * @return None * * \parDescription:
    M * Configures dimming engine source by writing register bit CHCONFIG_DSEL\n\n * * \parRelated APIs:
    * * XMC_BCCU_CH_EnableDimmingBypass()\n\n\n */bvoid XMC_BCCU_CH_SelectDimEngine (XMC_BCCU_CH_t *const channel, XMC_BCCU_CH_DIMMING_SOURCE_t sel);/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.. * * @return None * * \parDescription:
    K * Enables dimming engine bypass by writing register bit CHCONFIG_DBP. \n\n * * \parRelated APIs:
    J * XMC_BCCU_CH_SelectDimEngine(), XMC_BCCU_CH_DisableDimmingBypass()\n\n\n */Dvoid XMC_BCCU_CH_EnableDimmingBypass (XMC_BCCU_CH_t *const channel);/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.. * * @return None * * \parDescription:
    M * Disables dimming engine bypass by clearing register bit CHCONFIG_DBP. \n\n * * \parRelated APIs:
    * * XMC_BCCU_CH_EnableDimmingBypass()\n\n\n */Evoid XMC_BCCU_CH_DisableDimmingBypass (XMC_BCCU_CH_t *const channel);/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.. * * @return None * * \parDescription:
    { * Enables gating feature by writing register bit CHCONFIG_GEN. The gating feature is used to enable fast control schemes, ] * such as peak-current control and this has been controlled by Analog Comparator module.\n\n * * \parRelated APIs:
    $ * XMC_BCCU_CH_DisableGating()\n\n\n */L__STATIC_INLINE void XMC_BCCU_CH_EnableGating (XMC_BCCU_CH_t *const channel){< channel->CHCONFIG |= (uint32_t)(BCCU_CH_CHCONFIG_GEN_Msk);}/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.. * * @return None * * \parDescription:
    { * Disables gating feature by writing register bit CHCONFIG_GEN. The gating feature is used to enable/disable fast control g * schemes, such as peak-current control and this has been controlled by Analog Comparator module. \n\n * * \parRelated APIs:
    # * XMC_BCCU_CH_EnableGating()\n\n\n */M__STATIC_INLINE void XMC_BCCU_CH_DisableGating (XMC_BCCU_CH_t *const channel){= channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_GEN_Msk);}/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.. * * @return None * * \parDescription:
    o * Enables flicker watchdog by writing register bit CHCONFIG_WEN. And limits the sigma-delta modulator output\n& * according to Watchdog threshold\n\n * * \parRelated APIs:
    \ * XMC_BCCU_SetFlickerWDThreshold(), XMC_BCCU_ReadFlickerWDThreshold(), XMC_BCCU_CH_Init(), - * XMC_BCCU_CH_DisableFlickerWatchdog()\n\n\n */U__STATIC_INLINE void XMC_BCCU_CH_EnableFlickerWatchdog (XMC_BCCU_CH_t *const channel){< channel->CHCONFIG |= (uint32_t)(BCCU_CH_CHCONFIG_WEN_Msk);}/** *T * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.. * * @return None * * \parDescription:
    m * Disables flicker watchdog by writing register bit CHCONFIG_WEN. No limits the sigma-delta modulator output& * according to Watchdog threshold\n\n * * \parRelated APIs:
    \ * XMC_BCCU_SetFlickerWDThreshold(), XMC_BCCU_ReadFlickerWDThreshold(), XMC_BCCU_CH_Init(), , * XMC_BCCU_CH_EnableFlickerWatchdog()\n\n\n */V__STATIC_INLINE void XMC_BCCU_CH_DisableFlickerWatchdog (XMC_BCCU_CH_t *const channel){= channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_WEN_Msk);}/** *g * @param dim_engine Base address of the bccu dimming engine. \b Range: BCCU0_DE0, BCCU0_DE1, BCCU0_DE2v * @param config Pointer to constant dimming engine configuration data structure. Use type @ref XMC_BCCU_DIM_CONFIG_t. * * @return None * * \parDescription:
    w * Configures dimming clock divider to adjust the fade rate, dither selection and exponential curve selection using \a W * dim_div, \a dither_en, \a cur_sel parameters and by writing into a DTT register.\n\n * * \parRelated APIs:
    2 * XMC_BCCU_GlobalInit(), XMC_BCCU_CH_Init()\n\n\n */evoid XMC_BCCU_DIM_Init (XMC_BCCU_DIM_t *const dim_engine, const XMC_BCCU_DIM_CONFIG_t *const config);/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0M * @param dim_no Specific dimming engine number to enable. \b Range: 0 to 2\n * * @return None * * \parDescription:
    d * Enables a specific dimming engine number using \a dim_no by writing a register bit DEEN_EDEy.\n\n * * \parRelated APIs:
    R * XMC_BCCU_DisableDimmingEngine(), XMC_BCCU_ConcurrentEnableDimmingEngine()\n\n\n */[__STATIC_INLINE void XMC_BCCU_EnableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t dim_no){: bccu->DEEN |= (uint32_t)(BCCU_DEEN_EDE0_Msk << dim_no);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0N * @param dim_no Specific dimming engine number to disable. \b Range: 0 to 2\n * * @return None * * \parDescription:
    f * Disables a specific dimming engine number using \a dim_no by clearing a register bit DEEN_EDEy.\n\n * * \parRelated APIs:
    R * XMC_BCCU_EnableDimmingEngine(), XMC_BCCU_ConcurrentDisableDimmingEngine()\n\n\n */\__STATIC_INLINE void XMC_BCCU_DisableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t dim_no){; bccu->DEEN &= ~(uint32_t)(BCCU_DEEN_EDE0_Msk << dim_no);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0[ * @param dim_no Specific dimming engine number to start dimming process \b Range: 0 to 2\n * * @return None * * \parDescription:
    z * After dimming engine initialization, the outcome of executing the API starts changing the brightness towards to target / * by writing a register bit DESTRCON_DEyS.\n\n * * \parRelated APIs:
    C * XMC_BCCU_AbortDimming(), XMC_BCCU_ConcurrentStartDimming()\n\n\n */T__STATIC_INLINE void XMC_BCCU_StartDimming (XMC_BCCU_t *const bccu, uint32_t dim_no){? bccu->DESTRCON = (uint32_t)(BCCU_DESTRCON_DE0S_Msk << dim_no);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0Z * @param dim_no Specific dimming engine number to stop dimming process \b Range: 0 to 2\n * * @return None * * \parDescription:
    h * When the dimming in progress, the outcome of executing the API is stopping the dimming (i.e. fading) h * immediately for specific dimming engine number \a dim_no by writing a register bit DESTRCON_DEyA.\n\n * * \parRelated APIs:
    C * XMC_BCCU_StartDimming(), XMC_BCCU_ConcurrentAbortDimming()\n\n\n */T__STATIC_INLINE void XMC_BCCU_AbortDimming (XMC_BCCU_t *const bccu, uint32_t dim_no){? bccu->DESTRCON = (uint32_t)(BCCU_DESTRCON_DE0A_Msk << dim_no);}/** *? * @param bccu Base address of the bccu module. \b Range: BCCU0^ * @param dim_no Specific dimming engine number to know the dimming status. \b Range: 0 to 2\n *` * @return Dimming completion status. \b Range: 0-Completed or 1-start change towards the target * \parDescription:
    v * Retrieves dimming completion status for specific dimming engine number using \a dim_no by reading the register bit  * DESTRCON_DEyS. \n\n * * \parRelated APIs:
    F * XMC_BCCU_DIM_SetTargetDimmingLevel(), XMC_BCCU_StartDimming()\n\n\n */]__STATIC_INLINE uint32_t XMC_BCCU_IsDimmingFinished (XMC_BCCU_t *const bccu, uint32_t dim_no){U return (uint32_t)((bccu->DESTRCON & (BCCU_DESTRCON_DE0S_Msk << dim_no)) >> dim_no);}/** *g * @param dim_engine Base address of the bccu dimming engine. \b Range: BCCU0_DE0, BCCU0_DE1, BCCU0_DE29 * @param level Target dimming level. \b Range: 0 to 4095 * * @return None * * \parDescription:
    m * Configures target dimming level by writing register DLS, only be written if no shadow transfer of dimming.I * Use XMC_BCCU_IsDimmingFinished() to know shadow transfer finished \n\n * * \parRelated APIs:
    ^ * XMC_BCCU_StartDimming(), XMC_BCCU_IsDimmingFinished(), XMC_BCCU_SetGlobalDimmingLevel(), \n( * XMC_BCCU_DIM_ReadDimmingLevel()\n\n\n */[void XMC_BCCU_DIM_SetTargetDimmingLevel (XMC_BCCU_DIM_t *const dim_engine, uint32_t level);/** *g * @param dim_engine Base address of the bccu dimming engine. \b Range: BCCU0_DE0, BCCU0_DE1, BCCU0_DE2 *5 * @return Current dimming level. \b Range: 0 or 4095 * \parDescription:
    J * Retrieves current dimming level by reading the register DE_DL_DLEV.\n\n * * \parRelated APIs:
    - * XMC_BCCU_DIM_SetTargetDimmingLevel()\n\n\n */Y__STATIC_INLINE uint32_t XMC_BCCU_DIM_ReadDimmingLevel (XMC_BCCU_DIM_t *const dim_engine){: return (uint32_t)(dim_engine->DL & BCCU_DE_DL_DLEV_Msk);}/** *g * @param dim_engine Base address of the bccu dimming engine. \b Range: BCCU0_DE0, BCCU0_DE1, BCCU0_DE2Z * @param div Dimming clock divider, used to adjust the fade rate. If 0, the dimming levelB as same as target dimming level on shadow transfer\n * * @return None * * \parDescription:
    N * Configures dimming clock divider by writing register bit DE_DTT_DIMDIV.\n\n * * \parRelated APIs:
    ( * XMC_BCCU_SetDimClockPrescaler()\n\n\n */Qvoid XMC_BCCU_DIM_SetDimDivider (XMC_BCCU_DIM_t *const dim_engine, uint32_t div);/** *g * @param dim_engine Base address of the bccu dimming engine. \b Range: BCCU0_DE0, BCCU0_DE1, BCCU0_DE2f * @param dither_en Dither enable. Dithering added for every dimming step if dimming level < 128.
    V * @param sel Type of exponential curve. Use type @ref XMC_BCCU_DIM_CURVE_t. If dither; enabled, the configuration is being ignored\n * * @return None * * \parDescription:
    J * Configures dimming clock curve by writing register bit DE_DTT_CSEL.\n\n * * \parRelated APIs:
     * XMC_BCCU_DIM_Init()\n\n\n */rvoid XMC_BCCU_DIM_ConfigDimCurve (XMC_BCCU_DIM_t *const dim_engine, uint32_t dither_en, XMC_BCCU_DIM_CURVE_t sel);/** * @} *//** * @} */#ifdef __cplusplus}#endif#endif /* BCCU0 */#endif /* XMC_BCCU_H */ xmc_common.h÷/*D * Copyright (C) 2015 Infineon Technologies AG. All rights reserved. *N * Infineon Technologies AG (Infineon) is supplying this software for use with * Infineon's microcontrollers.H * This file can be freely distributed within development tools that are$ * supporting such microcontrollers. *M * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIEDE * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OFO * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.O * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,7 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * *//** * @file xmc_common.h * @date 20 Feb, 2015 * @version 1.0.2 * * * History
     * * Version 1.0.0 Initial
    + * Version 1.0.2 Brief section updated
     */#ifndef XMC_COMMON_H#define XMC_COMMON_H#include #include #include #include #include "xmc_device.h"/**, * @addtogroup XMClib XMC Peripheral Library * @{ *//** * @addtogroup COMMONH * @brief Common APIs to all peripherals for XMC microcontroller family  * @{ */P/******************************************************************************* * MACROSQ *******************************************************************************//* Define WEAK attribute */#if !defined(__WEAK)#if defined ( __CC_ARM )%#define __WEAK __attribute__ ((weak))#elif defined ( __ICCARM__ )#define __WEAK __weak#elif defined ( __GNUC__ )%#define __WEAK __attribute__ ((weak))#elif defined ( __TASKING__ )%#define __WEAK __attribute__ ((weak))#endif#endif#ifdef XMC_ASSERT_ENABLEZ #define XMC_ASSERT(msg, exp) { if(!(exp)) {XMC_AssertHandler(msg, __FILE__, __LINE__);} }#else# #define XMC_ASSERT(msg, exp) { ; }#endif#ifdef XMC_DEBUG_ENABLE #include ( #define XMC_DEBUG(msg) { printf(msg); }#else #define XMC_DEBUG(msg) { ; }#endif!#define XMC_UNUSED_ARG(x) (void)x3#define XMC_STRUCT_INIT(m) memset(&m, 0, sizeof(m))'#define XMC_PRIOARRAY_DEF(name, size) \4XMC_PRIOARRAY_ITEM_t prioarray_m_##name[size + 2]; \FXMC_PRIOARRAY_t prioarray_def_##name = {(size), (prioarray_m_##name)};#define XMC_PRIOARRAY(name) \&prioarray_def_##nameP/******************************************************************************* * DATA STRUCTURESQ *******************************************************************************//* * */"typedef struct XMC_DRIVER_VERSION { uint8_t major; uint8_t minor; uint8_t patch;} XMC_DRIVER_VERSION_t;/* * */typedef void *XMC_LIST_t;/* * */!typedef struct XMC_PRIOARRAY_ITEM{ int32_t priority; int32_t previous; int32_t next;} XMC_PRIOARRAY_ITEM_t;/* * */typedef struct XMC_PRIOARRAY{ uint32_t size; XMC_PRIOARRAY_ITEM_t *items;} XMC_PRIOARRAY_t;P/******************************************************************************* * API PROTOTYPESQ *******************************************************************************/#ifdef __cplusplus extern "C" {#endif/* * */Uvoid XMC_AssertHandler(const char *const msg, const char *const file, uint32_t line);/* * */%void XMC_LIST_Init(XMC_LIST_t *list);/* * */6void XMC_LIST_Add(XMC_LIST_t *list, void *const item);/* * */9void XMC_LIST_Remove(XMC_LIST_t *list, void *const item);/* * */.uint32_t XMC_LIST_GetLength(XMC_LIST_t *list);/* * */)void *XMC_LIST_GetHead(XMC_LIST_t *list);/* * */)void *XMC_LIST_GetTail(XMC_LIST_t *list);/* * */Hvoid XMC_LIST_Insert(XMC_LIST_t *list, void *prev_item, void *new_item);/* * */4void XMC_PRIOARRAY_Init(XMC_PRIOARRAY_t *prioarray);/* * */Svoid XMC_PRIOARRAY_Add(XMC_PRIOARRAY_t *prioarray, int32_t item, int32_t priority);/* * */Dvoid XMC_PRIOARRAY_Remove(XMC_PRIOARRAY_t *prioarray, int32_t item);/* * */I__STATIC_INLINE int32_t XMC_PRIOARRAY_GetHead(XMC_PRIOARRAY_t *prioarray){D XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL);0 return prioarray->items[prioarray->size].next;}/* * */I__STATIC_INLINE int32_t XMC_PRIOARRAY_GetTail(XMC_PRIOARRAY_t *prioarray){D XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL);8 return prioarray->items[prioarray->size + 1].previous;}/* * */___STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemPriority(XMC_PRIOARRAY_t *prioarray, int32_t item){j XMC_ASSERT("XMC_PRIOARRAY_GetItemPriority: item out of range", (item >= 0) && (item < prioarray->size));) return prioarray->items[item].priority;}/* * */[__STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemNext(XMC_PRIOARRAY_t *prioarray, int32_t item){f XMC_ASSERT("XMC_PRIOARRAY_GetItemNext: item out of range", (item >= 0) && (item < prioarray->size));% return prioarray->items[item].next;}/* * */___STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemPrevious(XMC_PRIOARRAY_t *prioarray, int32_t item){j XMC_ASSERT("XMC_PRIOARRAY_GetItemPrevious: item out of range", (item >= 0) && (item < prioarray->size));) return prioarray->items[item].previous;}#ifdef __cplusplus}#endif/** * @} *//** * @} */#endif /* XMC_COMMON_H */ xmc_gpio.h/*D * Copyright (C) 2015 Infineon Technologies AG. All rights reserved. *N * Infineon Technologies AG (Infineon) is supplying this software for use with * Infineon's microcontrollers.H * This file can be freely distributed within development tools that are$ * supporting such microcontrollers. *M * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIEDE * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OFO * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.O * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,7 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * *//** * @file xmc_gpio.h * @date 20 Feb, 2015 * @version 1.0.2 * * History
     *& * Version 1.0.0 Initial version
    , * Version 1.0.2 Documentation improved
     */#ifndef XMC_GPIO_H#define XMC_GPIO_HP/******************************************************************************* * HEADER FILESQ *******************************************************************************/#include "xmc_common.h"/**, * @addtogroup XMClib XMC Peripheral Library * @{ *//** * @addtogroup GPIOX * @brief General Purpose Input Output (GPIO) driver for the XMC microcontroller family. *n * GPIO driver provide a generic and very flexible software interface for all standard digital I/O port pins. r * Each port slice has individual interfaces for the operation as General Purpose I/O and it further provides the V * connectivity to the on-chip periphery and the control for the pad characteristics.  *4 * The driver is divided into Input and Output mode. * * Input mode features:[ * -# Configuration structure XMC_GPIO_CONFIG_t and initialization function XMC_GPIO_Init()ˆ * -# Allows the selection of weak pull-up or pull-down device. Configuration structure XMC_GPIO_MODE_t and function XMC_GPIO_SetMode() * \if XMC1M * -# Allows the selection of input hysteresis. XMC_GPIO_SetInputHysteresis() * \endif * *  * Output mode features:‘ * -# Allows the selection of push pull/open drain and Alternate output. Configuration structure XMC_GPIO_MODE_t and function XMC_GPIO_SetMode() * \if XMC4 * -# Allows the selection of pad driver strength. Configuration structure XMC_GPIO_OUTPUT_STRENGTH_t and function XMC_GPIO_SetOutputStrength() * \endif *Š * -# Allows the selection of initial output level. Configuration structure XMC_GPIO_OUTPUT_LEVEL_t and function XMC_GPIO_SetOutputLevel() * *@{ */P/******************************************************************************* * MACROSQ *******************************************************************************/`#define XMC_GPIO_MAJOR_VERSION (1U) /**< Major number of the driver version, which is,6 \.\ e.g. 1.5.3.*/`#define XMC_GPIO_MINOR_VERSION (0U) /**< Minor number of the driver version, which is,D \.\ e.g. 1.5.3.*/`#define XMC_GPIO_PATCH_VERSION (2U) /**< Patch number of the driver version, which is,6 \.\ e.g. 1.5.3.*/_#define PORT_IOCR_PC_Msk PORT0_IOCR0_PC0_Msk /**< Port input output control register(Pn_IOCR),) PCx bit field-Mask :0xf8 */U#define PORT_IOCR_PC_Size (8U) /**< Port input output control register(Pn_IOCR),) PCx bit field-shift size */U#define XMC_GPIO_CHECK_OUTPUT_LEVEL(level) ((level == XMC_GPIO_OUTPUT_LEVEL_LOW) || \R (level == XMC_GPIO_OUTPUT_LEVEL_HIGH)), P#define XMC_GPIO_CHECK_HWCTRL(hwctrl) ((hwctrl == XMC_GPIO_HWCTRL_DISABLED) || \S (hwctrl == XMC_GPIO_HWCTRL_PERIPHERAL1) || \t (hwctrl == XMC_GPIO_HWCTRL_PERIPHERAL2)) , P/******************************************************************************* * ENUMSQ *******************************************************************************//**s * Defines the direction and characteristics of a pin. Use type \a XMC_GPIO_MODE_t for this enum. For the operationx * with alternate functions, the port pins are directly connected to input or output functions of the on-chip periphery. */typedef enum XMC_GPIO_MODE{Q XMC_GPIO_MODE_INPUT_TRISTATE = 0x00UL, /**< No internal pull device active */T XMC_GPIO_MODE_INPUT_PULL_DOWN = 0x08UL, /**< Internal pull-down device active */P XMC_GPIO_MODE_INPUT_PULL_UP = 0x10UL, /**< Internal pull-up device active */o XMC_GPIO_MODE_INPUT_SAMPLING = 0x18UL, /**< No internal pull device active;Pn_OUTx continuously samples the4 input value */c XMC_GPIO_MODE_INPUT_INVERTED_TRISTATE = 0x20UL, /**< Inverted no internal pull device active */f XMC_GPIO_MODE_INPUT_INVERTED_PULL_DOWN = 0x28UL, /**< Inverted internal pull-down device active */b XMC_GPIO_MODE_INPUT_INVERTED_PULL_UP = 0x30UL, /**< Inverted internal pull-up device active */u XMC_GPIO_MODE_INPUT_INVERTED_SAMPLING = 0x38UL, /**< Inverted no internal pull device active;Pn_OUTx continuouslyF samples the input value */V XMC_GPIO_MODE_OUTPUT_PUSH_PULL = 0x80UL, /**< Push-pull general-purpose output */_ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1 = 0x88UL, /**< Push-pull alternate output function 1 */_ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2 = 0x90UL, /**< Push-pull alternate output function 2 */_ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT3 = 0x98UL, /**< Push-pull alternate output function 3 */_ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4 = 0xA0UL, /**< Push-pull alternate output function 4 */_ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT5 = 0xA8UL, /**< Push-pull alternate output function 5 */_ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT6 = 0xB0UL, /**< Push-pull alternate output function 6 */_ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7 = 0xB8UL, /**< Push-pull alternate output function 7 */W XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN = 0xc0UL, /**< Open-drain general-purpose output */` XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT1 = 0xc8UL, /**< Push-pull alternate output function 1 */` XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2 = 0xD0UL, /**< Push-pull alternate output function 2 */` XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT3 = 0xD8UL, /**< Push-pull alternate output function 3 */` XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT4 = 0xE0UL, /**< Push-pull alternate output function 4 */` XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT5 = 0xE8UL, /**< Push-pull alternate output function 5 */` XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6 = 0xF0UL, /**< Push-pull alternate output function 6 */_ XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7 = 0xF8UL /**< Push-pull alternate output function 7 */} XMC_GPIO_MODE_t;/**T * Defines output level of a pin. Use type \a XMC_GPIO_OUTPUT_LEVEL_t for this enum. */"typedef enum XMC_GPIO_OUTPUT_LEVEL{; XMC_GPIO_OUTPUT_LEVEL_LOW = 0x10000U, /**< Reset bit */6 XMC_GPIO_OUTPUT_LEVEL_HIGH = 0x1U, /**< Set bit */} XMC_GPIO_OUTPUT_LEVEL_t;/**l * Defines direct hardware control characteristics of the pin . Use type \a XMC_GPIO_HWCTRL_t for this enum. */typedef enum XMC_GPIO_HWCTRL{E XMC_GPIO_HWCTRL_DISABLED = 0x0U, /**< Software control only */n XMC_GPIO_HWCTRL_PERIPHERAL1 = 0x1U, /**< HWI0/HWO0 control path can override the software configuration */n XMC_GPIO_HWCTRL_PERIPHERAL2 = 0x2U /**< HWI1/HWO1 control path can override the software configuration */} XMC_GPIO_HWCTRL_t;P/******************************************************************************* * DEVICE FAMILY EXTENSIONSQ *******************************************************************************/ #if UC_FAMILY == XMC1#include "xmc1_gpio.h"#elif UC_FAMILY == XMC4#include "xmc4_gpio.h"#else1#error "xmc_gpio.h: familiy device not supported"#endifP/******************************************************************************* * API PROTOTYPESQ *******************************************************************************/#ifdef __cplusplus extern "C" {#endif/** * * @param None *E * @return XMC_DRIVER_VERSION_t Data structure storing driver version * * \parDescription:
    z * The function is commonly used to check for user software compatibility with a specific version of the low level driver. * * \parRelated APIs:
     * None * */5XMC_DRIVER_VERSION_t XMC_GPIO_GetDriverVersion(void);/**r * @param port Constant pointer pointing to GPIO port, to access port registers like Pn_OUT,Pn_OMR,Pn_IOCR etc.! * @param pin Port pin number.m * @param config GPIO configuration data structure. Refer data structure @ref XMC_GPIO_CONFIG_t for details. * * @return None * * \parDescription:
    * \if XMC1p * Initializes input / output mode settings like, pull up / pull down devices,hysteresis, push pull /open drain.t * Also configures alternate function outputs and clears hardware port control for a selected \a port \a and \a pin.z * \a config provides selected I/O settings. It configures hardware registers Pn_IOCR,Pn_OUT, Pn_OMR,Pn_PDISC and Pn_PHCR. * \endif * \if XMC4y * Initializes input / output mode settings like, pull up / pull down devices,push pull /open drain, and pad driver mode.p * Also configures alternate function outputs and clears hardware port control for selected \a port and \a pin .P * It configures hardware registers Pn_IOCR,Pn_OUT,Pn_OMR,Pn_PDISC and Pn_PDR.\n * \endif * * \parRelated APIs:
     * None * * \parNote:
    q * This API is called in definition of DAVE_init by code generation and therefore should not be explicitly calledv * for the normal operation. Use other APIs only after DAVE_init is called successfully (returns DAVE_STATUS_SUCCESS). * * */ jvoid XMC_GPIO_Init(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_CONFIG_t *const config); /** *\ * @param port Constant pointer pointing to GPIO port, to access hardware register Pn_IOCR. * @param pin Port pin number.d * @param mode input / output functionality selection. Refer @ref XMC_GPIO_MODE_t for valid values. * * @return None * * \parDescription:
    t * Sets digital input and output driver functionality and characteristics of a GPIO port pin. It configures hardwarev * registers Pn_IOCR. \a mode is initially configured during initialization in XMC_GPIO_Init(). Call this API to alterC * the port direction functionality as needed later in the program. * * \parRelated APIs:
     * None * */bvoid XMC_GPIO_SetMode(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_MODE_t mode);/** *\ * @param port Constant pointer pointing to GPIO port, to access hardware register Pn_OMR. * @param pin Port pin number.] * @param level output level selection. Refer @ref XMC_GPIO_OUTPUT_LEVEL_t for valid values. * * @return None * * \parDescription:
    i * Set port pin output level to high or low.It configures hardware registers Pn_OMR.\a level is initially{ * configured during initialization in XMC_GPIO_Init(). Call this API to alter output level as needed later in the program. * * \parRelated APIs:
    6 * XMC_GPIO_SetOutputHigh(), XMC_GPIO_SetOutputLow(). * * \parNote:
    ] * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). * */__STATIC_INLINE void XMC_GPIO_SetOutputLevel(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_OUTPUT_LEVEL_t level){X XMC_ASSERT("XMC_GPIO_SetOutputLevel: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port));b XMC_ASSERT("XMC_GPIO_SetOutputLevel: Invalid output level", XMC_GPIO_CHECK_OUTPUT_LEVEL(level)); % port->OMR = (uint32_t)level << pin;}/**[ * @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR. * @param pin Port pin number. * * @return None * * \parDescription:
    J * Sets port pin output to high. It configures hardware registers Pn_OMR. * * \parRelated APIs:
     * XMC_GPIO_SetOutputLow() * * \parNote:
    _ * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode().\nh * Register Pn_OMR is virtual and does not contain any flip-flop. A read action delivers the value of 0. * */[__STATIC_INLINE void XMC_GPIO_SetOutputHigh(XMC_GPIO_PORT_t *const port, const uint8_t pin){W XMC_ASSERT("XMC_GPIO_SetOutputHigh: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port));$ port->OMR = (uint32_t)0x1U << pin;}/** *[ * @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR. * @param pin port pin number. * * @return None * *\parDescription:
    J * Sets port pin output to low. It configures hardware registers Pn_OMR.\n * * \parRelated APIs:
    > * XMC_GPIO_SetOutputHigh() * *\parNote:
    ] * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode().j * Register Pn_OMR is virtual and does not contain any flip-flop. A read action delivers the value of 0.\n * */Z__STATIC_INLINE void XMC_GPIO_SetOutputLow(XMC_GPIO_PORT_t *const port, const uint8_t pin){V XMC_ASSERT("XMC_GPIO_SetOutputLow: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); port->OMR = 0x10000U << pin;}/** *Z * @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR. * @param pin port pin number. * * @return None * * \parDescription:
    Q * Configures port pin output to Toggle. It configures hardware registers Pn_OMR. * * \parRelated APIs:
    5 * XMC_GPIO_SetOutputHigh(), XMC_GPIO_SetOutputLow(). * * \parNote:
    x * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). Register Pn_OMR is virtualM * and does not contain any flip-flop. A read action delivers the value of 0. * */Z__STATIC_INLINE void XMC_GPIO_ToggleOutput(XMC_GPIO_PORT_t *const port, const uint8_t pin){V XMC_ASSERT("XMC_GPIO_ToggleOutput: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); port->OMR = 0x10001U << pin;}/** *Y * @param port constant pointer pointing to GPIO port, to access hardware register Pn_IN. * @param pin Port pin number. *+ * @return uint32_t pin logic level status. * *\parDescription:
    R * Reads the Pn_IN register and returns the current logical value at the GPIO pin. * * \parRelated APIs:
     * None * * \parNote:
    \ * Prior to this api, user has to configure port pin to input mode using XMC_GPIO_SetMode(). * */Z__STATIC_INLINE uint32_t XMC_GPIO_GetInput(XMC_GPIO_PORT_t *const port, const uint8_t pin){K XMC_ASSERT("XMC_GPIO_GetInput: Invalid port", XMC_GPIO_CHECK_PORT(port));& return (((port->IN) >> pin) & 0x1U);}/**Z * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PPS. * @param pin port pin number. * * @return None * * \parDescription:
    u * Enables pin power save mode and configures Pn_PPS register.This configuration is useful when the controller entersx * Deep Sleep mode.Port pin enabled with power save mode option are set to a defined state and the input Schmitt-Triggerv * as well as the output driver stage are switched off. By default port pin does not react to power save mode request. * * \parRelated APIs:
    " * XMC_GPIO_DisablePowerSaveMode() * * Note:
    u * Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). Doing so^ * may result in an undefined behavior of the pin when the device enters the Deep Sleep state. * */a__STATIC_INLINE void XMC_GPIO_EnablePowerSaveMode(XMC_GPIO_PORT_t *const port, const uint8_t pin){V XMC_ASSERT("XMC_GPIO_EnablePowerSaveMode: Invalid port", XMC_GPIO_CHECK_PORT(port));% port->PPS |= (uint32_t)0x1U << pin;}/** *Z * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PPS. * @param pin port pin number. * * @return None * * \parDescription:
    v * Disables pin power save mode and configures Pn_PPS register.This configuration is useful when the controller enterst * Deep Sleep mode. This configuration enables input Schmitt-Trigger and output driver stage(if pin is enabled power[ * save mode previously). By default port \a pin does not react to power save mode request. * * \parRelated APIs:
    " * XMC_GPIO_EnablePowerSaveMode() * *\parNote:
    u * Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). Doing so^ * may result in an undefined behavior of the pin when the device enters the Deep Sleep state. * */b__STATIC_INLINE void XMC_GPIO_DisablePowerSaveMode(XMC_GPIO_PORT_t *const port, const uint8_t pin){W XMC_ASSERT("XMC_GPIO_DisablePowerSaveMode: Invalid port", XMC_GPIO_CHECK_PORT(port));2 port->PPS &= ~(uint32_t)((uint32_t)0x1U << pin);}/**] * @param port constant pointer pointing to GPIO port, to access hardware register Pn_HWSEL. * @param pin port pin number.b * @param hwctrl direct hardware control selection. Refer @ref XMC_GPIO_HWCTRL_t for valid values. * * @return None * * \parDescription:
    s * Selects direct hard ware control and configures Pn_HWSEL register.This configuration is useful for the port pins` * overlaid with peripheral functions for which the connected peripheral needs hardware control. * * \parRelated APIs:
     * None * *\parNote:
    l * Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B).g * Doing so may result in an undefined behavior of the pin when the device enters the Deep Sleep state. * */qvoid XMC_GPIO_SetHardwareControl(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_HWCTRL_t hwctrl);/**\ * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PDISC. * @param pin port pin number. * * @return None * * \parRelated APIs:
     * None * * \parDescription:
    w * Enable digital input path for analog pins and configures Pn_PDISC register.This configuration is applicable only for * analog port pins. * */`__STATIC_INLINE void XMC_GPIO_EnableDigitalInput(XMC_GPIO_PORT_t *const port, const uint8_t pin){c XMC_ASSERT("XMC_GPIO_EnableDigitalInput: Invalid analog port", XMC_GPIO_CHECK_ANALOG_PORT(port)); 4 port->PDISC &= ~(uint32_t)((uint32_t)0x1U << pin);}/**] * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PDISC. * @param pin port pin number. * * @return None * * \parRelated APIs:
     * None * * \parDescription:
    t * Disable digital input path for analog pins and configures Pn_PDISC register.This configuration is applicable only * for analog port pins. * */a__STATIC_INLINE void XMC_GPIO_DisableDigitalInput(XMC_GPIO_PORT_t *const port, const uint8_t pin){c XMC_ASSERT("XMC_GPIO_EnableDigitalInput: Invalid analog port", XMC_GPIO_CHECK_ANALOG_PORT(port)); ' port->PDISC |= (uint32_t)0x1U << pin;}#ifdef __cplusplus}#endif/** * @} (end addtogroup GPIO) *//** * @} (end addtogroup XMClib) */#endif /* XMC_GPIO_H */ xmc_scu.hS/*D * Copyright (C) 2015 Infineon Technologies AG. All rights reserved. *k * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon's microcontrollers.j * This file can be freely distributed within development tools that are supporting such microcontrollers. *v * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITEDi * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * w * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,OR CONSEQUENTIAL DAMAGES, FOR ANY REASON * WHATSOEVER. *//** * @file xmc_scu.h * @date 20 Feb, 2015 * @version 1.0.2 * *  * History
     * * Version 1.0.0 Initial
    , * Version 1.0.2 Documentation improved
     */#ifndef XMC_SCU_H#define XMC_SCU_H v/********************************************************************************************************************* * HEADER FILESv ********************************************************************************************************************/#include /**, * @addtogroup XMClib XMC Peripheral Library * @{ */ /** * @addtogroup SCUI * @brief System Control Unit(SCU) driver for XMC microcontroller family. *d * System control unit is the SoC power, reset and a clock manager with additional responsibility ofK * providing system stability protection and other auxiliary functions.
    ' * SCU provides the following features, * -# Power control \if XMC4  * -# Hibernate control  \endif * -# Reset control * -# Clock controlF * -# Miscellaneous control(boot mode, system interrupts etc.)

     *k * The SCU driver is divided in to clock control logic, reset control logic, system interrupt control logic \if XMC4G * , hibernate control logic, trap control logic, parity control logic  \endif' * and miscellaneous control logic.
     * * Clock driver features:h * -# Allows clock configuration using the structure XMC_SCU_CLOCK_CONFIG_t and API XMC_SCU_CLOCK_Init() \if XMC4U * -# Provides structure XMC_SCU_CLOCK_SYSPLL_CONFIG_t for configuring the system PLL^ * -# Allows selection of clock source for system PLL, XMC_SCU_CLOCK_GetSystemPllClockSource() * -# Provides APIs for configuring different module clock frequencies XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_SetUsbClockDivider()h * -# Allows selection of clock source for external output, XMC_SCU_CLOCK_SetExternalOutputClockSource()¹ * -# Provides APIs for enabling external high power oscillator and ultra low power oscillator, XMC_SCU_CLOCK_EnableHighPerformanceOscillator(), XMC_SCU_CLOCK_EnableLowPowerOscillator()g * -# Provides APIs for getting various clock frequencies XMC_SCU_CLOCK_GetPeripheralClockFrequency(), R XMC_SCU_CLOCK_GetCpuClockFrequency(), XMC_SCU_CLOCK_GetSystemClockFrequency()
     \endif \if XMC1b * -# Allows selection of peripheral clock frequency, XMC_SCU_CLOCK_SetFastPeripheralClockSource()i * -# Provides API to get the peripheral clock frequency, XMC_SCU_CLOCK_GetFastPeripheralClockFrequency() \endif * * Reset driver features: \if XMC4v * -# Allows to handle peripheral reset XMC_SCU_RESET_AssertPeripheralReset(), XMC_SCU_RESET_DeassertPeripheralReset()f * -# Allows configuration of NMI generation for selected events, XMC_SCU_INTERRUPT_EnableNmiRequest() \endif \if XMC1F * -# Allows to trigger device reset XMC_SCU_RESET_AssertMasterReset()X * -# Allows to configure multiple sources for reset, XMC_SCU_RESET_EnableResetRequest() \endif
     * * Interrupt driver features:h * -# Provides APIs for enabling/ disabling interrupt event generation XMC_SCU_INTERRUPT_EnableEvent(), ! XMC_SCU_INTERRUPT_DisableEvent()g * -# Provides API for registering callback function for events XMC_SCU_INTERRUPT_SetEventHandler()
     * \if XMC4 * Hibernate driver features:x * -# Allows configuration of hibernate domain XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_HIB_DisableHibernateDomain()S * -# Allows selection of standby clock source, XMC_SCU_HIB_SetStandbyClockSource()K * -# Allows selection of RTC clock source, XMC_SCU_HIB_SetRtcClockSource()t * -# Provides API for enabling slow internal clock used for backup clock, XMC_SCU_HIB_EnableInternalSlowClock()
     * * Trap driver features:i * -# Allows handling of trap XMC_SCU_TRAP_Enable(), XMC_SCU_TRAP_GetStatus(), XMC_SCU_TRAP_Trigger()
     * * Parity driver features:q * -# Parity error generated by on-chip RAM can be monitored, XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_GetStatus()q * -# Allows configuration of trap generation on detection of parity error, XMC_SCU_PARITY_EnableTrapGeneration() * * Power driver features:Z * -# Allows to power the USB module XMC_SCU_POWER_EnableUsb(), XMC_SCU_POWER_DisableUsb() \endif * * Miscellaneous features:v * -# Allows to trigger multiple capture compare unit(CCU) channels to be started together XMC_SCU_SetCcuTriggerHigh() \if XMC4a * -# Enables configuration of out of range comparator (ORC) XMC_SCU_EnableOutOfRangeComparator()} * -# Enables configuration of die temperature sensor XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor()I * -# Enables configuration of device boot mode XMC_SCU_SetBootMode()
     \endif \if XMC1p * -# Enables configuration of die temperature sensor XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits()| * -# Allows configuring supply monitor unit using the structure XMC_SCU_SUPPLYMONITOR_t and API XMC_SCU_SupplyMonitorInit()f * -# Allows handling of protected bits XMC_SCU_LockProtectedBits(), XMC_SCU_UnlockProtectedBits()
     \endif * @{ */ v/********************************************************************************************************************* * MACROSv ********************************************************************************************************************/X#define XMC_SCU_MAJOR_VERSION (1U) /**< Major number of the SCU driver version, which isS \.\.\ e.g. 1.5.3.*/X#define XMC_SCU_MINOR_VERSION (0U) /**< Minor number of the SCU driver version, which isS \.\.\ e.g. 1.5.3.*/X#define XMC_SCU_PATCH_VERSION (2U) /**< Patch number of the SCU driver version, which isS \.\.\ e.g. 1.5.3.*/v/********************************************************************************************************************* * ENUMSv ********************************************************************************************************************//**V * Defines the status of SCU API execution, used to verify the SCU related API calls. */typedef enum XMC_SCU_STATUS {Q XMC_SCU_STATUS_OK = 0UL, /**< SCU related operation successfully completed.*/Z XMC_SCU_STATUS_BUSY , /**< Cannot execute the SCU related operation request becausew another operation is in progress. \a XMC_SCU_STATUS_BUSY is returned when API is busy@ processing another request. */{ XMC_SCU_STATUS_ERROR /**< SCU related operation failed. When API cannot fulfill request, this value is returned. */} XMC_SCU_STATUS_t;v/********************************************************************************************************************* * DATA TYPESv ********************************************************************************************************************//**X * Function pointer type used for registering callback functions on SCU event occurence. */8typedef void (*XMC_SCU_INTERRUPT_EVENT_HANDLER_t)(void);v/********************************************************************************************************************* * DEVICE EXTENSIONSv ********************************************************************************************************************/#if (UC_FAMILY == XMC1)#include #elif (UC_FAMILY == XMC4)#include #else#error "Unspecified chipset"#endifv/********************************************************************************************************************* * API Prototypesv ********************************************************************************************************************/#ifdef __cplusplus extern "C" {#endif/**I * @return Data structure (::XMC_DRIVER_VERSION_t) storing driver version * * \parDescription:
    3 * Returns the version of the low level driver
     * * \parW * The function can be used to check application software compatibility with a specific# * version of the low level driver. */4XMC_DRIVER_VERSION_t XMC_SCU_GetDriverVersion(void); /** *t * @param trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits2 * in the register CCUCON.
     * \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be 5 * combined using \a OR operation. * * @return None * * \parDescription
    Z * Generates active edge(low to high) trigger for multiple CCU units at the same time.\n\nZ * Before executing this API, all the required CCU timers should configure external start.B * The edge of the start signal should be selected as active edge.F * The input signal for the CCU slice should be selected as SCU input.f * The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig(). Y * CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering * the timer using this API.
     * \parRelated APIs:
    \ * XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerLow()\n\n\n */F__STATIC_INLINE void XMC_SCU_SetCcuTriggerHigh(const uint32_t trigger){+ SCU_GENERAL->CCUCON |= (uint32_t)trigger;}/** *r * @param trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits2 * in the register CCUCON.
     * \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be 5 * combined using \a OR operation. * * @return None * * \parDescription
    [ * Generates passive edge(high to low) trigger for multiple CCU units at the same time.\n\nZ * Before executing this API, all the required CCU timers should configure external start.C * The edge of the start signal should be selected as passive edge.F * The input signal for the CCU slice should be selected as SCU input.f * The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig(). Y * CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering * the timer using this API.
     * \parRelated APIs:
    ] * XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerHigh()\n\n\n */E__STATIC_INLINE void XMC_SCU_SetCcuTriggerLow(const uint32_t trigger){, SCU_GENERAL->CCUCON &= (uint32_t)~trigger;}/** *` * @param config Pointer to structure holding the clock prescaler values and divider values for @ * configuring clock generators and clock tree.\nf * \b Range: Configure the members of structure @ref XMC_SCU_CLOCK_CONFIG_t for various, * parameters of clock setup. * * @return None * * \parDescription
    3 * Initializes clock generators and clock tree.\n\n * \if XMC1_ * Peripheral clock and system clock are configured based on the input configuration \a config.a * The system clock frequency is tuned by configuring the FDIV and IDIV values of CLKCR register.N * The values of FDIV and IDIV can be provided as part of input configuration.R * The PCLK divider determines the ratio of peripheral clock to the system clock. D * The source of RTC clock is set based on the input configuration. @ * \a SystemCoreClock variable will be updated with the value ofQ * system clock frequency. Access to protected bit fields are handled internally. * \endif * \if XMC4p * Enables the high precision oscillator(fOHP) input and configures the system and peripheral clock frequencies.n * Based on the system clock source selected in \a config, either fPLL or fOFI will be chosen as system clock.g * Based on PLL mode(normal or prescaler mode) used, PLL ramps up in steps to achieve target frequency.f * The clock dividers for CPU, CCU and peripheral clocks will be set based on the input configuration.S * The \a SystemCoreClock variable is set with the value of system clock frequency. * \endif * \parRelated APIs:
    [ * XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GetCpuClockFrequency() \n\n\n */Dvoid XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config);/** *c * @param event Bit mask of the event to enable. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_tk * for providing the input value. Multiple events can be combined using the \a OR operation. * * @return None * * \parDescription
    @ * Enables the generation of interrupt for the input events.\n\nX * The events are enabled by setting the respective bit fields in the SRMSK register. \n` * Note: User should separately enable the NVIC node responsible for handling the SCU interrupt.D * The interrupt will be generated when the respective event occurs. * \parRelated APIs:
    ; * NVIC_EnableIRQ(), XMC_SCU_INTERRUPT_DisableEvent()\n\n\n */H__STATIC_INLINE void XMC_SCU_INTERRUPT_EnableEvent(const uint32_t event){* SCU_INTERRUPT->SRMSK |= (uint32_t)event;}/** *d * @param event Bit mask of the event to disable. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_tk * for providing the input value. Multiple events can be combined using the \a OR operation. * * @return None * * \parDescription
    H * Disables generation of interrupt on occurence of the input event.\n\n[ * The events are disabled by resetting the respective bit fields in the SRMSK register. \n * \parRelated APIs:
    ; * NVIC_DisableIRQ(), XMC_SCU_INTERRUPT_EnableEvent()\n\n\n */I__STATIC_INLINE void XMC_SCU_INTERRUPT_DisableEvent(const uint32_t event){+ SCU_INTERRUPT->SRMSK &= (uint32_t)~event;}/** *h * @param event Bit mask of the event to be triggered. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_tk * for providing the input value. Multiple events can be combined using the \a OR operation. * * @return None * * \parDescription
    7 * Triggers the event as if the hardware raised it.\n\nV * Event will be triggered by setting the respective bitfield in the SRSET register.\ne * Note: User should enable the NVIC node that handles the respective event for interrupt generation. * \parRelated APIs:
    c * NVIC_EnableIRQ(), XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_ClearEventStatus() \n\n\n */I__STATIC_INLINE void XMC_SCU_INTERRUPT_TriggerEvent(const uint32_t event){* SCU_INTERRUPT->SRSET |= (uint32_t)event;}/**. * @return uint32_t Status of the SCU events. * * \parDescription
    - * Provides the status of all SCU events.\n\nS * The status is read from the SRRAW register. To check the status of a particular Y * event, the returned value should be masked with the bit mask of the event. The bitmask\ * of events can be obtained using the type @ref XMC_SCU_INTERRUPT_EVENT_t. Multiple events'K * status can be checked by combining the bit masks using \a OR operation. j * After detecting the event, the event status should be cleared using software to detect the event again. * \parRelated APIs:
    u * XMC_SCU_INTERRUPT_ClearEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n */>__STATIC_INLINE uint32_t XMC_SCU_INTERUPT_GetEventStatus(void){ return SCU_INTERRUPT->SRRAW;}/** *c * @param event Bit mask of the events to clear. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_tk * for providing the input value. Multiple events can be combined using the \a OR operation. * * @return None * * \parDescription
    5 * Clears the event status bit in SRRAW register.\n\nZ * The events are cleared by writing value 1 to their bit positions in the SRCLR register._ * The API can be used when polling method is used. After detecting the event, the event status> * should be cleared using software to detect the event again. * * \parRelated APIs:
    M * XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent() \n\n\n */M__STATIC_INLINE void XMC_SCU_INTERRUPT_ClearEventStatus(const uint32_t event){* SCU_INTERRUPT->SRCLR |= (uint32_t)event;}/** *E * @return uint32_t Status representing the reason for device reset. * * \parDescription
    C * Provides the value representing the reason for device reset.\n\nx * The return value is an encoded word, which can indicate multiple reasons for the last reset. Each bit position of thet * returned word is representative of a last reset cause. The returned value should be appropriately masked to check * the cause of reset. < * The cause of the last reset gets automatically stored in J * the \a SCU_RSTSTAT register. The reset status shall be reset after eachP * startup in order to ensure consistent source indication after the next reset.f * \b Range: The type @ref XMC_SCU_RESET_REASON_t can be used to get the bit masks of the reset cause. * * \parRelated APIs:
    0 * XMC_SCU_RESET_ClearDeviceResetReason() \n\n\n */A__STATIC_INLINE uint32_t XMC_SCU_RESET_GetDeviceResetReason(void){@ return ((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_RSTSTAT_Msk);}/** * @return None  * * \parDescription
    B * Clears the reset reason bits in the reset status register. \n\nw * Clearing of the reset status information in the \a SCU_RSTSTAT register via register bit \a RSTCLR.RSCLR is stronglyG * recommended to ensure a clear indication of the cause of next reset. * * \parRelated APIs:
    . * XMC_SCU_RESET_GetDeviceResetReason() \n\n\n */?__STATIC_INLINE void XMC_SCU_RESET_ClearDeviceResetReason(void){& /* Clear RSTSTAT.RSTSTAT bitfield */< SCU_RESET->RSTCLR |= (uint32_t)SCU_RESET_RSTCLR_RSCLR_Msk;} /**2 * @return uint32_t Value of CPU clock frequency. * * \parDescription
    1 * Provides the vlaue of CPU clock frequency.\n\nB * The value is stored in a global variable \a \b SystemCoreClock.M * It is updated when the clock configuration is done using the SCU LLD APIs.F * The value represents the frequency of clock used for CPU operation.R * \b Range: Value is of type uint32_t, and gives the value of frequency in Hertz. * * \parRelated APIs:
    Z * XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n */A__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetCpuClockFrequency(void){ return SystemCoreClock;}/**B * @return uint32_t Value of peripheral clock frequency in Hertz. * * \parDescription
    R * Provides the vlaue of clock frequency at which the peripherals are working.\n\np * The value is derived from the CPU frequency. \b Range: Value is of type uint32_t. It is represented in Hertz. * \parRelated APIs:
    R * XMC_SCU_CLOCK_GetCpuClockFrequency(),XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n */:uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void); #if(UC_SERIES != XMC45) /** *| * @param peripheral The peripheral for which the clock has to be gated. \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_tC * to identify the peripheral clock to be gated. * * @return None * * \parDescription
    = * Blocks the supply of clock to the selected peripheral.\n\nt * Clock gating helps in reducing the power consumption. User can selectively gate the clocks of unused peripherals. * \if XMC1o * fPCLK is the source of clock to various peripherals. Some peripherals support clock gate. Such a gate blocks0 * the clock supply for the selected peripheral.g * Software can request for individual gating of such peripheral clocks by enabling the \a SCU_CGATSET0{ * register bit field. Every bit in \a SCU_CGATSET0 register is protected by the bit protection scheme. Access to protected% * bit fields are handled internally. * \endif * \if XMC4o * fPERI is the source of clock to various peripherals. Some peripherals support clock gate. Such a gate blocks0 * the clock supply for the selected peripheral.a * Software can request for individual gating of such peripheral clocks by enabling one of the \aG * SCU_CGATSET0, \a SCU_CGATSET1 or \a SCU_CGATSET2 register bitfields. * * \endif[ * Note: Clock gating shall not be activated unless the module is in reset state. So use \a[ * XMC_SCU_CLOCK_IsPeripheralClockGated() API before enabling the gating of any peripheral. * \parRelated APIs:
    W * XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_UngatePeripheralClock() \n\n\n */Tvoid XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral); /** * * @param peripheral The peripheral for which the clock has to be ungated. \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t1 * to identify the peripheral. * * @return None * * \parDescription
    > * Enables the supply of clock to the selected peripheral.\n\nT * By default when the device powers on, the peripheral clock will be gated for the ) * peripherals that support clock gating.P * The peripheral clock should be enabled before using it for any functionality. * \if XMC1\ * fPCLK is the source of clock to various peripherals. Some peripherals support clock gate.d * Software can request for individual ungating of such peripheral clocks by setting respective bits# * in the \a SCU_CGATCLR0 register. * \endif * \if XMC4\ * fPERI is the source of clock to various peripherals. Some peripherals support clock gate.u * Software can request for individual ungating of such peripheral clocks by setting the respective bits in one of \a> * SCU_CGATCLR0, \a SCU_CGATCLR1 or \a SCU_CGATCLR2 registers. * \endif * * \parRelated APIs:
    U * XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n */Vvoid XMC_SCU_CLOCK_UngatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral);/** *[ * @param peripheral The peripheral for which the check for clock gating has to be done. d * \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t to identify the peripheral. *g * @return bool Status of the peripheral clock gating. \b Range: true if the peripheral clock is gated.H * false if the peripheral clock ungated(gate de-asserted). * * \parDescription
    3 * Gives the status of peripheral clock gating.\n\n * \if XMC1M * Checks the status of peripheral clock gating using the register CGATSTAT0. * \endif * \if XMC4i * Checks the status of peripheral clock gating using one of CGATSTAT0, CGATSTAT1 or CGATSTAT2 registers. * \endif+ * It is recommended to use this API before] * enabling the gating of any peripherals through \a XMC_SCU_CLOCK_GatePeripheralClock() API. * * \parRelated APIs:
    T * XMC_SCU_CLOCK_UngatePeripheralClock(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n */Wbool XMC_SCU_CLOCK_IsPeripheralClockGated(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral);#endif/**= * @return uint32_t Status of the register mirror update.\nt * \b Range: Use the bit mask of the SCU_GENERAL_MIRRSTS register for the mirror update event of n * interest. e.g.: SCU_GENERAL_MIRRSTS_RTC_CTR_Msk. Multiple update events can be combined , * using \a OR operation. * * \parDescription
    r * Provides the status of hibernate domain register update, when the respective mirror registers are changed. \n\ns * The hibernate domain is connected to the core domain via SPI serial communication. MIRRSTS is a status register m * representing the communication of changed value of a mirror register to its corresponding register in the < * hibernate domain. The bit fields of the register indicatew * that a corresponding register of the hibernate domain is ready to accept a write or that the communication interface3 * is busy with executing the previous operation.\ne * Note: There is no hibernate domain in XMC1x devices. This register is retained for legacy purpose. */6__STATIC_INLINE uint32_t XMC_SCU_GetMirrorStatus(void){ return(SCU_GENERAL->MIRRSTS);}/**Q * @param event The event for which the interrupt handler is to be configured. \nV * \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t for identifying the event.T * @param handler Name of the function to be executed when the event if detected. \nM * \b Range: The function accepts no arguments and returns no value.f * @return XMC_SCU_STATUS_t Status of configuring the event handler function for the selected event.\n] * \b Range: \a XMC_SCU_STATUS_OK if the event handler is successfully configured.\nF * \a XMC_SCU_STATUS_ERROR if the input event is invalid.\n * \parDescription
    \ * Assigns the event handler function to be executed on occurence of the selected event.\n\n_ * If the input event is valid, the handler function will be assigned to a table to be executedo * when the interrupt is generated and the event status is set in the event status register. By using this API,u * polling for a particular event can be avoided. This way the CPU utilization will be optimized. Multiple SCU eventst * can generate a common interrupt. When the interrupt is generated, a common interrupt service routine is executed.w * It checks for status flags of events which can generate the interrupt. The handler function will be executed if the  * event flag is set. * * \parRelated APIs:
    M * XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERUPT_GetEventStatus() \n\n\n */‹XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler(const XMC_SCU_INTERRUPT_EVENT_t event, const XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler);/**R * @param sr_num Service request number identifying the SCU interrupt generated.\nl * \b Range: 0 to 2. XMC4x devices have one common SCU interrupt, so the value should be 0.\nP * But XMC1x devices support 3 interrupt nodes. * @return None * \parDescription
    K * A common function to execute callback functions for multiple events.\n\ni * It checks for the status of events which can generate the interrupt with the selected service request.t * If the event is set, the corresponding callback function will be executed. It also clears the event status bit.\nZ * \b Note: This is an internal function. It should not be called by the user application. * * \parRelated APIs:
    - * XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n */)void XMC_SCU_IRQHandler(uint32_t sr_num);#ifdef __cplusplus}#endif/** * @} */ /** * @} */ #endif /* SCU_H */ xmc1_scu.cç/*D * Copyright (C) 2015 Infineon Technologies AG. All rights reserved. *N * Infineon Technologies AG (Infineon) is supplying this software for use with * Infineon's microcontrollers.H * This file can be freely distributed within development tools that are$ * supporting such microcontrollers. *v * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITEDi * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * w * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,OR CONSEQUENTIAL DAMAGES, FOR ANY REASON * WHATSOEVER. *//** * @file xmc1_scu.c * @date 16 Feb, 2014 * @version 1.0.0 *` * @brief SCU low level driver API prototype definition for XMC1 family of microcontrollers
     *+ * Detailed description of file
    P * APIs provided in this file cover the following functional blocks of SCU:
    0 * -- GCU (APIs prefixed with XMC_SCU_GEN_)
    @ * ----Temperature Monitoring, Voltage Monitoring, CCU Start etc *1 * -- CCU (APIs prefixed with XMC_SCU_CLOCK_)
    @ * ---- Clock initialization, Clock Gating, Sleep Management etc *2 * -- RCU (APIs prefixed with XMC_SCU_RESET_)
    ; * ---- Reset Init, Cause, Manual Reset Assert/Deassert etc *; * -- INTERRUPT (APIs prefixed with XMC_SCU_INTERRUPT_)
    ? * ---- Initialization, Manual Assert/Deassert, Acknowledge etc * * History * * Version 1.0.0 Initial
     */v/********************************************************************************************************************* * HEADER FILESv ********************************************************************************************************************/#include #if UC_FAMILY == XMC1v/********************************************************************************************************************* * MACROSv ********************************************************************************************************************/T#define SCU_GCU_PASSWD_PROT_ENABLE (195UL) /**< Password for enabling protection */U#define SCU_GCU_PASSWD_PROT_DISABLE (192UL) /**< Password for disabling protection */^#define XMC_SCU_DELAY_20US (200UL) /**< 20us delay count with CPU ticking at 32Mhz */]#define XMC_SCU_CHECK_RTCCLKSRC(source) ( (source == XMC_SCU_CLOCK_RTCCLKSRC_DCO2) || \b (source == XMC_SCU_CLOCK_RTCCLKSRC_ERU_IOUT0) || \b (source == XMC_SCU_CLOCK_RTCCLKSRC_ACMP0_OUT) || \b (source == XMC_SCU_CLOCK_RTCCLKSRC_ACMP1_OUT) || \s (source == XMC_SCU_CLOCK_RTCCLKSRC_ACMP2_OUT) ) /**< Used to verifyu whether provided RTC p clock source is k correct. */L#define XMC_SCU_EVENT_IRQ0_MASK (XMC_SCU_INTERRUPT_EVENT_FLASH_ERROR | \P XMC_SCU_INTERRUPT_EVENT_FLASH_COMPLETED | \G XMC_SCU_INTERRUPT_EVENT_PESRAM | \F XMC_SCU_INTERRUPT_EVENT_PUSIC | \B XMC_SCU_INTERRUPT_EVENT_LOCI)M#define XMC_SCU_EVENT_IRQ1_MASK (XMC_SCU_INTERRUPT_EVENT_STDBYCLKFAIL | \F XMC_SCU_INTERRUPT_EVENT_VDDPI | \F XMC_SCU_INTERRUPT_EVENT_VDROP | \F XMC_SCU_INTERRUPT_EVENT_VCLIP | \I XMC_SCU_INTERRUPT_EVENT_TSE_DONE | \I XMC_SCU_INTERRUPT_EVENT_TSE_HIGH | \H XMC_SCU_INTERRUPT_EVENT_TSE_LOW | \I XMC_SCU_INTERRUPT_EVENT_WDT_WARN | \M XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC | \J XMC_SCU_INTERRUPT_EVENT_RTC_ALARM | \O XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED | \Q XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED | \Q XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED | \P XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED | \M XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED)#if UC_SERIES != XMC11E#define XMC_SCU_EVENT_IRQ2_MASK (XMC_SCU_INTERRUPT_EVENT_ORC0 | \E XMC_SCU_INTERRUPT_EVENT_ORC1 | \E XMC_SCU_INTERRUPT_EVENT_ORC2 | \E XMC_SCU_INTERRUPT_EVENT_ORC3 | \E XMC_SCU_INTERRUPT_EVENT_ORC4 | \E XMC_SCU_INTERRUPT_EVENT_ORC5 | \E XMC_SCU_INTERRUPT_EVENT_ORC6 | \E XMC_SCU_INTERRUPT_EVENT_ORC7 | \F XMC_SCU_INTERRUPT_EVENT_ACMP0 | \F XMC_SCU_INTERRUPT_EVENT_ACMP1 | \C XMC_SCU_INTERRUPT_EVENT_ACMP2)#else(#define XMC_SCU_EVENT_IRQ2_MASK (0U)(#endif  )#define XMC_SCU_INTERRUPT_EVENT_MAX (32U)(#define XMC_SCU_NUM_IRQ (3U) v/********************************************************************************************************************* * GLOBAL DATAv ********************************************************************************************************************/jstatic XMC_SCU_INTERRUPT_EVENT_HANDLER_t event_handler_list[XMC_SCU_NUM_IRQ][XMC_SCU_INTERRUPT_EVENT_MAX];v/********************************************************************************************************************* * LOCAL ROUTINESv ********************************************************************************************************************/Sstatic void XMC_SCU_CLOCK_lDivUpdate(uint32_t idiv, uint32_t fdiv);astatic void XMC_SCU_CLOCK_lFrequencyUpScaling(uint32_t curr_idiv, uint32_t idiv);cstatic void XMC_SCU_CLOCK_lFrequencyDownScaling(uint32_t curr_idiv, uint32_t idiv);v/********************************************************************************************************************* * API IMPLEMENTATIONv ********************************************************************************************************************/9/* API to lock protected bitfields from being modified */$void XMC_SCU_LockProtectedBits(void){3 SCU_GENERAL->PASSWD = SCU_GCU_PASSWD_PROT_ENABLE;}@/* API to make protected bitfields available for modification */&void XMC_SCU_UnlockProtectedBits(void){4 SCU_GENERAL->PASSWD = SCU_GCU_PASSWD_PROT_DISABLE;= while(((SCU_GENERAL->PASSWD)&SCU_GENERAL_PASSWD_PROTS_Msk)) {( /* Loop until the lock is removed */ }}4/* API to initialize power supply monitoring unit */Bvoid XMC_SCU_SupplyMonitorInit(const XMC_SCU_SUPPLYMONITOR_t *obj){ uint32_t anavdel; uint32_t irqmask; anavdel = 0UL; \ anavdel |= (uint32_t)((obj-> ext_supply_threshold) << SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos);` anavdel |= (uint32_t)((obj->ext_supply_monitor_speed) << SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos); # if(true == (obj->enable_at_init)) {8 anavdel |= (uint32_t)SCU_ANALOG_ANAVDEL_VDEL_EN_Msk; }, SCU_ANALOG->ANAVDEL = (uint16_t) anavdel;  irqmask = 0UL; * if(true == (obj->enable_prewarning_int)) {7 irqmask |= (uint32_t)SCU_INTERRUPT_SRMSK_VDDPI_Msk; } % if(true == (obj->enable_vdrop_int)) {8 irqmask |= (uint32_t)SCU_INTERRUPT_SRMSK_VDROPI_Msk; } % if(true == (obj->enable_vclip_int)) {8 irqmask |= (uint32_t)SCU_INTERRUPT_SRMSK_VCLIPI_Msk; }, SCU_INTERRUPT->SRMSK |= (uint32_t)irqmask;} U/* API to program temperature limits as raw digital values into temperature sensor */#if (UC_SERIES != XMC11)Svoid XMC_SCU_SetRawTempLimits(const uint32_t lower_temp, const uint32_t upper_temp){E SCU_ANALOG->ANATSEIH = upper_temp & SCU_ANALOG_ANATSEIH_TSE_IH_Msk;E SCU_ANALOG->ANATSEIL = lower_temp & SCU_ANALOG_ANATSEIL_TSE_IL_Msk;}*/* API to start temperature measurement */3XMC_SCU_STATUS_t XMC_SCU_StartTempMeasurement(void){ volatile uint32_t i; G SCU_ANALOG->ANATSECTRL |= (uint32_t)SCU_ANALOG_ANATSECTRL_TSE_EN_Msk;# /* Spin for about 10000 cycles */! for (i = 0UL; i < 10000UL; i++) { /* NOP */ } return XMC_SCU_STATUS_OK;})/* API to stop temperature measurement */&void XMC_SCU_StopTempMeasurement(void){H SCU_ANALOG->ANATSECTRL &= (uint32_t)~SCU_ANALOG_ANATSECTRL_TSE_EN_Msk;}?/* API to check if the temperature has gone past the ceiling */"bool XMC_SCU_HighTemperature(void){ bool ret_val; uint32_t high_temp; H high_temp = (SCU_INTERRUPT->SRRAW) & SCU_INTERRUPT_SRRAW_TSE_HIGH_Msk; if(high_temp) { ret_val = true; } else { ret_val = false; }  return ret_val;}:/* API to check if the temperature is lower than normal */!bool XMC_SCU_LowTemperature(void){ bool ret_val; uint32_t low_temp; F low_temp = (SCU_INTERRUPT->SRRAW) & SCU_INTERRUPT_SRRAW_TSE_LOW_Msk; if(low_temp) { ret_val = true; } else { ret_val = false; }  return ret_val;}-/* API to retrieve the ddevice temperature */%uint32_t XMC_SCU_GetTemperature(void){ uint32_t temperature; 2 temperature = (uint32_t)(SCU_ANALOG->ANATSEMON);  return temperature;}#endif7/* API which initializes the clock tree ofthe device */Cvoid XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config){ /* Remove protection */ XMC_SCU_UnlockProtectedBits();" /* Update PCLK selection mux. */m SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_PCLKSEL_Msk | SCU_CLK_CLKCR_RTCCLKSEL_Msk)) | $ config->rtc_src |$ config->pclk_src; /* Update the dividers now */7 XMC_SCU_CLOCK_lDivUpdate(config->idiv, config->fdiv); SystemCoreClockUpdate(); # /*Close the lock opened above. */ XMC_SCU_LockProtectedBits(); }\/* API which selects one of the available parent clock nodes for a given child clock node */Lvoid XMC_SCU_CLOCK_SetRtcClockSource(const XMC_SCU_CLOCK_RTCCLKSRC_t source){d XMC_ASSERT("XMC_SCU_CLOCK_SetRtcSourceClock:Wrong Parent Clock", XMC_SCU_CHECK_RTCCLKSRC(source)); XMC_SCU_UnlockProtectedBits(); N SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~SCU_CLK_CLKCR_RTCCLKSEL_Msk) | source; XMC_SCU_LockProtectedBits();}F/* API to program the divider placed between fperiph and its parent */Uvoid XMC_SCU_CLOCK_SetFastPeripheralClockSource(const XMC_SCU_CLOCK_PCLKSRC_t source){ XMC_SCU_UnlockProtectedBits();M SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~SCU_CLK_CLKCR_PCLKSEL_Msk) |  source;  XMC_SCU_LockProtectedBits();}0/* API which gates a clock node at its source */Svoid XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral){# XMC_SCU_UnlockProtectedBits(); , SCU_CLK->CGATSET0 |= (uint32_t)peripheral; XMC_SCU_LockProtectedBits();}2/* API which ungates a clock note at its source */Uvoid XMC_SCU_CLOCK_UngatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral){# XMC_SCU_UnlockProtectedBits(); , SCU_CLK->CGATCLR0 |= (uint32_t)peripheral; XMC_SCU_LockProtectedBits();}Vbool XMC_SCU_CLOCK_IsPeripheralClockGated(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral){ bool retval; # XMC_SCU_UnlockProtectedBits(); 3 retval = (bool)(SCU_CLK->CGATSTAT0 & peripheral); XMC_SCU_LockProtectedBits();  return retval;}F/* A utility routine which updates the fractional dividers in steps */Bstatic void XMC_SCU_CLOCK_lDivUpdate(uint32_t idiv, uint32_t fdiv){1 /* Find out current and target value of idiv */ uint32_t curr_idiv;= /* Take a snapshot of value already programmed into IDIV */R curr_idiv = (SCU_CLK->CLKCR & SCU_CLK_CLKCR_IDIV_Msk) >> SCU_CLK_CLKCR_IDIV_Pos; f SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_FDIV_Msk | SCU_CLK_CLKCR_CNTADJ_Pos)) |? (uint32_t)(fdiv << SCU_CLK_CLKCR_FDIV_Pos) |A (uint32_t)(1023UL <CLKCR)& SCU_CLK_CLKCR_VDDC2LOW_Msk) {/ /* Spin until the core supply stabilizes */ }  if(curr_idiv <= idiv) {^ /* Requested IDIV is greater than currently programmed IDIV. So downscale the frequency */9 XMC_SCU_CLOCK_lFrequencyDownScaling(curr_idiv, idiv); } else {Z /* Requested IDIV is lower than currently programmed IDIV. So upscale the frequency */7 XMC_SCU_CLOCK_lFrequencyUpScaling(curr_idiv, idiv); }f SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_IDIV_Msk | SCU_CLK_CLKCR_CNTADJ_Msk)) |o (uint32_t)(idiv << SCU_CLK_CLKCR_IDIV_Pos) | (uint32_t)(1023UL << SCU_CLK_CLKCR_CNTADJ_Pos);7 while ((SCU_CLK->CLKCR) & SCU_CLK_CLKCR_VDDC2LOW_Msk) {* /* Wait voltage suply stabilization */ } } 4/* Utility routine to perform frequency upscaling */Wstatic void XMC_SCU_CLOCK_lFrequencyUpScaling(uint32_t curr_idiv, uint32_t target_idiv){) while (curr_idiv > (target_idiv * 4UL)) {1 curr_idiv = (curr_idiv & 0xFFFFFFFCUL) + 4UL;B curr_idiv = (uint32_t)(curr_idiv >> 2UL); /* Divide by 4. */ h SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_IDIV_Msk | SCU_CLK_CLKCR_CNTADJ_Msk)) |v (uint32_t)(curr_idiv << SCU_CLK_CLKCR_IDIV_Pos) | (uint32_t)(1023UL << SCU_CLK_CLKCR_CNTADJ_Pos);7 while (SCU_CLK->CLKCR & SCU_CLK_CLKCR_VDDC2LOW_Msk) {* /* Wait voltage suply stabilization */ } }}6/* Utility routine to perform frequency downscaling */Ystatic void XMC_SCU_CLOCK_lFrequencyDownScaling(uint32_t curr_idiv, uint32_t target_idiv){) while ((curr_idiv * 4UL) < target_idiv) {E curr_idiv = (uint32_t)(curr_idiv << 2UL); /* Multiply by 4. */f SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_IDIV_Msk|SCU_CLK_CLKCR_CNTADJ_Pos)) |F (uint32_t)(curr_idiv << SCU_CLK_CLKCR_IDIV_Pos) |D (uint32_t)(1023UL << SCU_CLK_CLKCR_CNTADJ_Pos);7 while (SCU_CLK->CLKCR & SCU_CLK_CLKCR_VDDC2LOW_Msk) {* /* Wait voltage suply stabilization */ } }} /*g * API to retrieve clock frequency of peripherals on the peripheral bus using a shared functional clock */8uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void){ return SystemCoreClock;}<uint32_t XMC_SCU_CLOCK_GetFastPeripheralClockFrequency(void){j return (SystemCoreClock << ((SCU_CLK->CLKCR & SCU_CLK_CLKCR_PCLKSEL_Msk) >> SCU_CLK_CLKCR_PCLKSEL_Pos));}/* * */~XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler(XMC_SCU_INTERRUPT_EVENT_t event, XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler){ uint32_t index; XMC_SCU_STATUS_t status; index = 0U; status = XMC_SCU_STATUS_OK; , while (((uint32_t)event >> index) != 0x1U) { index++; } * if (index < XMC_SCU_INTERRUPT_EVENT_MAX) {, if (event & XMC_SCU_EVENT_IRQ0_MASK)  {. event_handler_list[0U][index] = handler; }- else if (event & XMC_SCU_EVENT_IRQ1_MASK) {. event_handler_list[1U][index] = handler; }- else if (event & XMC_SCU_EVENT_IRQ2_MASK) {. event_handler_list[2U][index] = handler; } else  {& status = XMC_SCU_STATUS_ERROR; }  } else  {" status = XMC_SCU_STATUS_ERROR; }  return status;}/* * */(void XMC_SCU_IRQHandler(uint32_t sr_num){ uint32_t index; uint32_t status; 2 XMC_SCU_INTERRUPT_EVENT_HANDLER_t event_handler; index = 0U;- status = XMC_SCU_INTERUPT_GetEventStatus();- while (index < XMC_SCU_INTERRUPT_EVENT_MAX) { ' if ((status & (1U << index)) != 0U) {8 event_handler = event_handler_list[sr_num][index]; if (event_handler != NULL) { event_handler(); } 6 XMC_SCU_INTERRUPT_ClearEventStatus(1U << index); . /* break; XMC1: Only PULSE interrupts */ } index++; }}#endif /* UC_FAMILY == XMC1 */ xmc_bccu.c1/*D * Copyright (C) 2015 Infineon Technologies AG. All rights reserved. *N * Infineon Technologies AG (Infineon) is supplying this software for use with * Infineon's microcontrollers.H * This file can be freely distributed within development tools that are$ * supporting such microcontrollers. *M * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIEDE * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OFO * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.O * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,7 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * *//** * @file xmc_bccu.c * @date 16 Feb, 2015 * @version 1.0.0 *: * @brief BCCU low level driver for XMC1 Micro-controllers *+ * Detailed description of file:
    @ * APIs for the functional blocks of BCCU have been defined.
    9 * -- Global, Channel, Dimming Engine configuration.
    V * -- Clock configuration, Function/Event configuration, Interrupt configuration.
     * * History *% * Version 1.0.0 Initial version
     */v/********************************************************************************************************************* * HEADER FILESv ********************************************************************************************************************/#include #include #if defined (BCCU0)v/********************************************************************************************************************* * MACROSv ********************************************************************************************************************/v/********************************************************************************************************************* * ENUMSv ********************************************************************************************************************/v/********************************************************************************************************************* * DATA STRUCTURESv ********************************************************************************************************************/v/********************************************************************************************************************* * GLOBAL DATAv ********************************************************************************************************************/v/********************************************************************************************************************* * LOCAL/UTILITY ROUTINESv ********************************************************************************************************************/v/********************************************************************************************************************* * API IMPLEMENTATIONv ********************************************************************************************************************//**2 * API to retrieve the version of the BCCU driver */4XMC_DRIVER_VERSION_t XMC_BCCU_GetDriverVersion(void){ XMC_DRIVER_VERSION_t version;) version.major = XMC_BCCU_MAJOR_VERSION;) version.minor = XMC_BCCU_MINOR_VERSION;) version.patch = XMC_BCCU_PATCH_VERSION; return version;}/*: * API to initialise the global resources of a BCCU module */_void XMC_BCCU_GlobalInit (XMC_BCCU_t *const bccu, const XMC_BCCU_GLOBAL_CONFIG_t *const config){F XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_BCCU0);" bccu->GLOBCON = config->globcon; " bccu->GLOBCLK = config->globclk;, bccu->GLOBDIM = config->global_dimlevel; }/*D * API to configure the global trigger mode & delay of a BCCU module */ovoid XMC_BCCU_ConfigGlobalTrigger(XMC_BCCU_t *const bccu, XMC_BCCU_TRIGMODE_t mode, XMC_BCCU_TRIGDELAY_t delay){M bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_TM_Msk | BCCU_GLOBCON_TRDEL_Msk);R bccu->GLOBCON |= ((uint32_t)mode | ((uint32_t)delay << BCCU_GLOBCON_TRDEL_Pos));}/*= * API to configure the trap input selection of a BCCU module */Svoid XMC_BCCU_SelectTrapInput (XMC_BCCU_t *const bccu, XMC_BCCU_CH_TRAP_IN_t input){8 bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_TRAPIS_Msk);@ bccu->GLOBCON |= ((uint32_t)input << BCCU_GLOBCON_TRAPIS_Pos);}/*< * API to configure the trap edge selection of a BCCU module */Pvoid XMC_BCCU_SetTrapEdge (XMC_BCCU_t *const bccu, XMC_BCCU_CH_TRAP_EDGE_t edge){8 bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_TRAPED_Msk);? bccu->GLOBCON |= ((uint32_t)edge << BCCU_GLOBCON_TRAPED_Pos);}/*5 * API to configure the suspend mode of a BCCU module */Vvoid XMC_BCCU_ConfigSuspendMode (XMC_BCCU_t *const bccu, XMC_BCCU_SUSPEND_MODE_t mode){8 bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_SUSCFG_Msk);? bccu->GLOBCON |= ((uint32_t)mode << BCCU_GLOBCON_SUSCFG_Pos);}/*g * API to configure number of consecutive zeroes allowed at modulator output (flicker watch-dog number) */Svoid XMC_BCCU_SetFlickerWDThreshold (XMC_BCCU_t *const bccu, uint32_t threshold_no){o XMC_ASSERT("XMC_BCCU_SetFlickerWDThreshold: Invalid threshold no", (threshold_no <= BCCU_GLOBCON_WDMBN_Msk)); 7 bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_WDMBN_Msk);F bccu->GLOBCON |= (uint32_t)(threshold_no << BCCU_GLOBCON_WDMBN_Pos);}/*D * API to configure the fast clock prescaler factor of a BCCU module */Jvoid XMC_BCCU_SetFastClockPrescaler (XMC_BCCU_t *const bccu, uint32_t div){i XMC_ASSERT("XMC_BCCU_SetFastClockPrescaler: Invalid divider value", (div <= BCCU_GLOBCLK_FCLK_PS_Msk)); 9 bccu->GLOBCLK &= ~(uint32_t)(BCCU_GLOBCLK_FCLK_PS_Msk); bccu->GLOBCLK |= div; }/*F * API to configure the dimmer clock prescaler factor of a BCCU module */Ivoid XMC_BCCU_SetDimClockPrescaler (XMC_BCCU_t *const bccu, uint32_t div){h XMC_ASSERT("XMC_BCCU_SetDimClockPrescaler: Invalid divider value", (div <= BCCU_GLOBCLK_DCLK_PS_Msk));9 bccu->GLOBCLK &= ~(uint32_t)(BCCU_GLOBCLK_DCLK_PS_Msk);? bccu->GLOBCLK |= (uint32_t)(div << BCCU_GLOBCLK_DCLK_PS_Pos); }/*[ * API to configure the modulator output (bit-time) clock prescaler factor of a BCCU module */Ovoid XMC_BCCU_SelectBitClock (XMC_BCCU_t *const bccu, XMC_BCCU_BCLK_MODE_t div){5 bccu->GLOBCLK &= ~(uint32_t)(BCCU_GLOBCLK_BCS_Msk);; bccu->GLOBCLK |= ((uint32_t)div << BCCU_GLOBCLK_BCS_Pos);}/*. * API to enable the channels at the same time */Nvoid XMC_BCCU_ConcurrentEnableChannels (XMC_BCCU_t *const bccu, uint32_t mask){i XMC_ASSERT("XMC_BCCU_ConcurrentEnableChannels: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK)); bccu->CHEN |= mask;}/*/ * API to disable the channels at the same time */Ovoid XMC_BCCU_ConcurrentDisableChannels (XMC_BCCU_t *const bccu, uint32_t mask){j XMC_ASSERT("XMC_BCCU_ConcurrentDisableChannels: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));" bccu->CHEN &= ~(uint32_t)(mask);}/*B * API to set the channel's output passive levels at the same time */{void XMC_BCCU_ConcurrentSetOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_mask, XMC_BCCU_CH_ACTIVE_LEVEL_t level){u XMC_ASSERT("XMC_BCCU_ConcurrentSetOutputPassiveLevel: Invalid channel mask", (chan_mask <= XMC_BCCU_CHANNEL_MASK)); ) bccu->CHOCON &= ~(uint32_t)(chan_mask);0 bccu->CHOCON |= (chan_mask * (uint32_t)level);}/*< * API to enable the various types of traps at the same time */Jvoid XMC_BCCU_ConcurrentEnableTrap (XMC_BCCU_t *const bccu, uint32_t mask){e XMC_ASSERT("XMC_BCCU_ConcurrentEnableTrap: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));= bccu->CHOCON |= (uint32_t)(mask << BCCU_CHOCON_CH0TPE_Pos);}/*= * API to disable the various types of traps at the same time */Kvoid XMC_BCCU_ConcurrentDisableTrap (XMC_BCCU_t *const bccu, uint32_t mask){f XMC_ASSERT("XMC_BCCU_ConcurrentDisableTrap: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));> bccu->CHOCON &= ~(uint32_t)(mask << BCCU_CHOCON_CH0TPE_Pos);}/*j * API to configure trigger mode and trigger delay at the same time, and also configure the channel enable */\void XMC_BCCU_ConcurrentConfigTrigger (XMC_BCCU_t *const bccu, XMC_BCCU_TRIG_CONFIG_t *trig){ uint32_t reg; t XMC_ASSERT("XMC_BCCU_ConcurrentConfigTrigger: Invalid channel mask", (trig->mask_chans <= XMC_BCCU_CHANNEL_MASK));M bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_TM_Msk | BCCU_GLOBCON_TRDEL_Msk);^ bccu->GLOBCON |= ((uint32_t)trig->mode | ((uint32_t)trig->delay << BCCU_GLOBCON_TRDEL_Pos)); reg = 0U; reg |= trig->mask_chans;C reg |= ((uint32_t)trig->mask_trig_lines << BCCU_CHTRIG_TOS0_Pos); bccu->CHTRIG = reg;}/*c * API to start the linear walk of the channels to change towards target intensity at the same time */Ovoid XMC_BCCU_ConcurrentStartLinearWalk (XMC_BCCU_t *const bccu, uint32_t mask){j XMC_ASSERT("XMC_BCCU_ConcurrentStartLinearWalk: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));% bccu->CHSTRCON |= (uint32_t)(mask);}/*@ * API to abort the linear walk of the channels at the same time */Ovoid XMC_BCCU_ConcurrentAbortLinearWalk (XMC_BCCU_t *const bccu, uint32_t mask){j XMC_ASSERT("XMC_BCCU_ConcurrentAbortLinearWalk: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));? bccu->CHSTRCON |= (uint32_t)(mask << BCCU_CHSTRCON_CH0A_Pos);}/*5 * API to enable the dimming engines at the same time */Svoid XMC_BCCU_ConcurrentEnableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t mask){x XMC_ASSERT("XMC_BCCU_ConcurrentEnableDimmingEngine: Invalid dimming engine mask", (mask <= XMC_BCCU_DIM_ENGINE_MASK)); bccu->DEEN = (uint32_t)(mask);}/*5 * API to enable the dimming engines at the same time */Tvoid XMC_BCCU_ConcurrentDisableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t mask){y XMC_ASSERT("XMC_BCCU_ConcurrentDisableDimmingEngine: Invalid dimming engine mask", (mask <= XMC_BCCU_DIM_ENGINE_MASK));" bccu->DEEN &= ~(uint32_t)(mask);}/*W * API to start the dimming engines at the same time to change towards target dim level */Lvoid XMC_BCCU_ConcurrentStartDimming (XMC_BCCU_t *const bccu, uint32_t mask){q XMC_ASSERT("XMC_BCCU_ConcurrentStartDimming: Invalid dimming engine mask", (mask <= XMC_BCCU_DIM_ENGINE_MASK));% bccu->DESTRCON |= (uint32_t)(mask);}/*4 * API to abort the dimming engines at the same time */Lvoid XMC_BCCU_ConcurrentAbortDimming (XMC_BCCU_t *const bccu, uint32_t mask){q XMC_ASSERT("XMC_BCCU_ConcurrentAbortDimming: Invalid dimming engine mask", (mask <= XMC_BCCU_DIM_ENGINE_MASK));? bccu->DESTRCON |= (uint32_t)(mask << BCCU_DESTRCON_DE0A_Pos);}/*5 * API to configure the dim level of a dimming engine */Mvoid XMC_BCCU_SetGlobalDimmingLevel (XMC_BCCU_t *const bccu, uint32_t level){r XMC_ASSERT("XMC_BCCU_SetGlobalDimmingLevel: Invalid global dimming level", (level <= BCCU_GLOBDIM_GLOBDIM_Msk)); bccu->GLOBDIM |= (level);}/*# * API to enable a specific channel */Fvoid XMC_BCCU_EnableChannel (XMC_BCCU_t *const bccu, uint32_t chan_no){i XMC_ASSERT("XMC_BCCU_EnableChannel: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));: bccu->CHEN |= (uint32_t)(BCCU_CHEN_ECH0_Msk << chan_no);}/*$ * API to disable a specific channel */Gvoid XMC_BCCU_DisableChannel (XMC_BCCU_t *const bccu, uint32_t chan_no){j XMC_ASSERT("XMC_BCCU_DisableChannel: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));; bccu->CHEN &= ~(uint32_t)(BCCU_CHEN_ECH0_Msk << chan_no);}/*2 * API to set the specific channel's passive level */ovoid XMC_BCCU_SetOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_no, XMC_BCCU_CH_ACTIVE_LEVEL_t level){q XMC_ASSERT("XMC_BCCU_SetOutputPassiveLevel: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));/ bccu->CHOCON |= ((uint32_t)level << chan_no);}/** * API to enable the specific channel trap */Cvoid XMC_BCCU_EnableTrap (XMC_BCCU_t *const bccu, uint32_t chan_no){f XMC_ASSERT("XMC_BCCU_EnableTrap: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));@ bccu->CHOCON |= (uint32_t)(BCCU_CHOCON_CH0TPE_Msk << chan_no);}/*+ * API to disable the specific channel trap */Dvoid XMC_BCCU_DisableTrap (XMC_BCCU_t *const bccu, uint32_t chan_no){g XMC_ASSERT("XMC_BCCU_DisableTrap: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));A bccu->CHOCON &= ~(uint32_t)(BCCU_CHOCON_CH0TPE_Msk << chan_no);}/*E * API to configure specific channel trigger enable and trigger line. */nvoid XMC_BCCU_EnableChannelTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no, XMC_BCCU_CH_TRIGOUT_t trig_line){ uint32_t reg;p XMC_ASSERT("XMC_BCCU_EnableChannelTrigger: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));? bccu->CHTRIG &= ~(uint32_t)(BCCU_CHTRIG_TOS0_Msk << chan_no);3 reg = (uint32_t)(BCCU_CHTRIG_ET0_Msk << chan_no);C reg |= ((uint32_t)trig_line << (BCCU_CHTRIG_TOS0_Pos + chan_no)); bccu->CHTRIG |= reg;}/*" * API to disable specific channel */Nvoid XMC_BCCU_DisableChannelTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no){q XMC_ASSERT("XMC_BCCU_DisableChannelTrigger: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));> bccu->CHTRIG &= ~(uint32_t)(BCCU_CHTRIG_ET0_Msk << chan_no);}/*1 * API to initialise the channel of a BCCU module */^void XMC_BCCU_CH_Init (XMC_BCCU_CH_t *const channel, const XMC_BCCU_CH_CONFIG_t *const config){' channel->CHCONFIG = config->chconfig; ! channel->PKCMP = config->pkcmp; # channel->PKCNTR = config->pkcntr;}/*? * API to configure channel trigger edge and force trigger edge */svoid XMC_BCCU_CH_ConfigTrigger (XMC_BCCU_CH_t *const channel, XMC_BCCU_CH_TRIG_EDGE_t edge, uint32_t force_trig_en){ uint32_t reg; Z channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_TRED_Msk | BCCU_CH_CHCONFIG_ENFT_Msk); 6 reg = ((uint32_t)edge << BCCU_CH_CHCONFIG_TRED_Pos);@ reg |= (uint32_t)(force_trig_en << BCCU_CH_CHCONFIG_ENFT_Pos); channel->CHCONFIG |= reg;}/*N * API to configure the linear walker clock prescaler factor of a BCCU channel */Xvoid XMC_BCCU_CH_SetLinearWalkPrescaler (XMC_BCCU_CH_t *const channel, uint32_t clk_div){A channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_LINPRES_Msk);K channel->CHCONFIG |= (uint32_t)(clk_div << BCCU_CH_CHCONFIG_LINPRES_Pos);}/*& * API to set channel target intensity */Svoid XMC_BCCU_CH_SetTargetIntensity (XMC_BCCU_CH_t *const channel, uint32_t ch_int){ channel->INTS = ch_int;}/*/ * API to retrieve the channel actual intensity */Auint32_t XMC_BCCU_CH_ReadIntensity (XMC_BCCU_CH_t *const channel){: return (uint32_t)(channel->INT & BCCU_CH_INT_CHINT_Msk);}/*^ * API to enable packer. Also configures packer threshold, off-time and on-time compare levels */rvoid XMC_BCCU_CH_EnablePacker (XMC_BCCU_CH_t *const channel, uint32_t thresh, uint32_t off_comp, uint32_t on_comp){Y channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_PEN_Msk | BCCU_CH_CHCONFIG_PKTH_Msk); channel->CHCONFIG |= thresh;O channel->PKCMP = (off_comp | (uint32_t)(on_comp << BCCU_CH_PKCMP_ONCMP_Pos));: channel->CHCONFIG |= (uint32_t)BCCU_CH_CHCONFIG_PEN_Msk;}/*$ * API to configure packer threshold */Pvoid XMC_BCCU_CH_SetPackerThreshold (XMC_BCCU_CH_t *const channel, uint32_t val){> channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_PKTH_Msk); channel->CHCONFIG |= val;}/*1 * API to configure packer off-time compare level */Svoid XMC_BCCU_CH_SetPackerOffCompare (XMC_BCCU_CH_t *const channel, uint32_t level){: channel->PKCMP &= ~(uint32_t)(BCCU_CH_PKCMP_OFFCMP_Msk); channel->PKCMP |= level;}/*1 * API to configure packer on-time compare level. */Rvoid XMC_BCCU_CH_SetPackerOnCompare (XMC_BCCU_CH_t *const channel, uint32_t level){9 channel->PKCMP &= ~(uint32_t)(BCCU_CH_PKCMP_ONCMP_Msk);7 channel->PKCMP |= (level << BCCU_CH_PKCMP_ONCMP_Pos);}/* * API to disable a packer. */=void XMC_BCCU_CH_DisablePacker (XMC_BCCU_CH_t *const channel){= channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_PEN_Msk);}/*+ * API to set packer off-time counter value */Uvoid XMC_BCCU_CH_SetPackerOffCounter (XMC_BCCU_CH_t *const channel, uint32_t cnt_val){? channel->PKCNTR &= ~(uint32_t)(BCCU_CH_PKCNTR_OFFCNTVAL_Msk); channel->PKCNTR |= cnt_val;}/** * API to set packer on-time counter value */Tvoid XMC_BCCU_CH_SetPackerOnCounter (XMC_BCCU_CH_t *const channel, uint32_t cnt_val){> channel->PKCNTR &= ~(uint32_t)(BCCU_CH_PKCNTR_ONCNTVAL_Msk);H channel->PKCNTR |= (uint32_t)(cnt_val << BCCU_CH_PKCNTR_ONCNTVAL_Pos);}/*0 * API to select the dimming engine of a channel */avoid XMC_BCCU_CH_SelectDimEngine (XMC_BCCU_CH_t *const channel, XMC_BCCU_CH_DIMMING_SOURCE_t sel){> channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_DSEL_Msk);D channel->CHCONFIG |= ((uint32_t)sel << BCCU_CH_CHCONFIG_DSEL_Pos);}/*W * API to bypass the dimming engine. And the brightness of channel is depending only on * intensity of the channel. */Cvoid XMC_BCCU_CH_EnableDimmingBypass (XMC_BCCU_CH_t *const channel){< channel->CHCONFIG |= (uint32_t)(BCCU_CH_CHCONFIG_DBP_Msk);}/*Z * API to disable the bypass of dimming engine. And the brightness of channel is depending? * on intensity of channel and dimming level of dimming engine. */Dvoid XMC_BCCU_CH_DisableDimmingBypass (XMC_BCCU_CH_t *const channel){= channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_DBP_Msk);}/*? * API to initialise a specific dimming engine of a BCCU module */dvoid XMC_BCCU_DIM_Init (XMC_BCCU_DIM_t *const dim_engine, const XMC_BCCU_DIM_CONFIG_t *const config){ dim_engine->DTT = config->dtt;}/*- * API to set dimming engine target dim level */Zvoid XMC_BCCU_DIM_SetTargetDimmingLevel (XMC_BCCU_DIM_t *const dim_engine, uint32_t level){ dim_engine->DLS = level;}/*J * API to configure the dimming clock prescaler factor of a dimming engine */Pvoid XMC_BCCU_DIM_SetDimDivider (XMC_BCCU_DIM_t *const dim_engine, uint32_t div){9 dim_engine->DTT &= ~(uint32_t)(BCCU_DE_DTT_DIMDIV_Msk); dim_engine->DTT |= div;}/*% * API to configure the dimming curve */qvoid XMC_BCCU_DIM_ConfigDimCurve (XMC_BCCU_DIM_t *const dim_engine, uint32_t dither_en, XMC_BCCU_DIM_CURVE_t sel){ uint32_t reg;N dim_engine->DTT &= ~(uint32_t)(BCCU_DE_DTT_DTEN_Msk | BCCU_DE_DTT_CSEL_Msk);6 reg = (uint32_t)(dither_en << BCCU_DE_DTT_DTEN_Pos);1 reg |= ((uint32_t)sel << BCCU_DE_DTT_CSEL_Pos); dim_engine->DTT |= reg;}#endif /* BCCU0 */ xmc_gpio.cG/*D * Copyright (C) 2015 Infineon Technologies AG. All rights reserved. *N * Infineon Technologies AG (Infineon) is supplying this software for use with * Infineon's microcontrollers.H * This file can be freely distributed within development tools that are$ * supporting such microcontrollers. *M * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIEDE * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OFO * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.O * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,7 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * *//** * @file xmc_gpio.c * @date 16 Feb, 2015 * @version 1.0.0 *E * @brief GPIO driver - API implementation common to all devices
     *  * History
     *& * Version 1.0.0 Initial version
     */P/******************************************************************************* * HEADER FILESQ *******************************************************************************/#include P/******************************************************************************* * MACROSQ *******************************************************************************/*#define PORT_HWSEL_Msk PORT0_HWSEL_HW0_MskP/******************************************************************************* * API IMPLEMENTATIONQ *******************************************************************************/4XMC_DRIVER_VERSION_t XMC_GPIO_GetDriverVersion(void){ XMC_DRIVER_VERSION_t version;2 version.major = (uint8_t)XMC_GPIO_MAJOR_VERSION;2 version.minor = (uint8_t)XMC_GPIO_MINOR_VERSION;2 version.patch = (uint8_t)XMC_GPIO_PATCH_VERSION; return version;}avoid XMC_GPIO_SetMode(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_MODE_t mode){J XMC_ASSERT("XMC_GPIO_SetMode: Invalid port", XMC_GPIO_CHECK_PORT(port));J XMC_ASSERT("XMC_GPIO_SetMode: Invalid mode", XMC_GPIO_CHECK_MODE(mode));‡ port->IOCR[(uint32_t)pin >> 2U] &= ~(uint32_t)((uint32_t)PORT_IOCR_PC_Msk << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U)));n port->IOCR[(uint32_t)pin >> 2U] |= (uint32_t)mode << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U));}pvoid XMC_GPIO_SetHardwareControl(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_HWCTRL_t hwctrl){U XMC_ASSERT("XMC_GPIO_SetHardwareControl: Invalid port", XMC_GPIO_CHECK_PORT(port));[ XMC_ASSERT("XMC_GPIO_SetHardwareControl: Invalid hwctrl", XMC_GPIO_CHECK_HWCTRL(hwctrl));P port->HWSEL &= ~(uint32_t)((uint32_t)PORT_HWSEL_Msk << ((uint32_t)pin << 1U));; port->HWSEL |= (uint32_t)hwctrl << ((uint32_t)pin << 1U);}startup_xmc1200.såO/****************************************************************************** * @file startup_XMC1200.s/ * @brief CMSIS Core Device Startup File for+ * Infineon XMC1200 Device Series * @version V1.13 * @date Dec 2014 *D * Copyright (C) 2014 Infineon Technologies AG. All rights reserved. * * * @parO * Infineon Technologies AG (Infineon) is supplying this software for use with D * Infineon's microcontrollers. This file can be freely distributedF * within development tools that are supporting such microcontrollers. * * @parL * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIEDE * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OFO * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.M * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR4 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. *P ******************************************************************************/O/********************** Version History ***************************************2 * V1.0, Oct, 02, 2012 PKB:Startup file for XMC1 < * V1.1, Oct, 19, 2012 PKB:ERU and MATH interrupt handlers S * V1.2, Nov, 02, 2012 PKB:Renamed AllowPLLInitByStartup to AllowClkInitByStartup I * V1.3, Dec, 11, 2012 PKB:Attributes of .XmcVeneerCode section changed @ * V1.4, Dec, 13, 2012 PKB:Removed unwanted interrupts/veneers > * V1.5, Jan, 26, 2013 PKB:Corrected the SSW related entries ; * V1.6, Feb, 13, 2013 PKB:Relative path to Device_Data.h 3 * V1.7, Feb, 19, 2013 PKB:Included XMC1100_SCU.incM * V1.8, Jan, 24, 2014 PKB:Removed AllowClkInitStartup and DAVE Extended initQ * V1.9, Feb, 05, 2014 PKB:Removed redundant alignment code from copy+clear funcsK * V1.10, Feb, 14, 2014 PKB:Added software_init_hook and hardware_init_hook? * V1.11, May, 06, 2014 JFT:__COPY_FLASH2RAM to initialize ram A * Added ram_code section initialization6 * V1.12, Sep, 29, 2014 JFT:One single default handlerP * Device_Data.h not included, user may use CLKVAL1_SSW, * and CLKVAL2_SSW.M * software_init_hook and hardware_init_hook removed. * Misc optimizationsN * V1.13, Dec, 11,2014 JFT:Default clocking changed, MCLK=32MHz and PCLK=64MHzP ******************************************************************************/N/*****************************************************************************# * Clock system handling by SSW * CLK_VAL1 Configuration4 * FDIV Fractional Divider Selection; * IDIV Divider Selection (limited to 1-16). * <0=> Divider is bypassed( * <1=> MCLK = 32 MHz( * <2=> MCLK = 16 MHz+ * <3=> MCLK = 10.67 MHz' * <4=> MCLK = 8 MHz+ * <254=> MCLK = 126 kHz- * <255=> MCLK = 125.5 kHz, * PCLKSEL PCLK Clock Select& * <0=> PCLK = MCLK* * <1=> PCLK = 2 x MCLK- * RTCCLKSEL RTC Clock Select2 * <0=> 32.768kHz standby clockC * <1=> 32.768kHz external clock from ERU0.IOUT0B * <2=> 32.768kHz external clock from ACMP0.OUTB * <3=> 32.768kHz external clock from ACMP1.OUTB * <4=> 32.768kHz external clock from ACMP2.OUT# * <5=> Reserved# * <6=> Reserved# * <7=> Reserved; *