This circuit is a capacitance bridge; it detects the matching between a reference capacitance C1 and an unknown capacitance, Cx. It uses an instrumentation amplifier in an unusual topology– a sine wave drives the two input op amps’ non- inverting inputs (ordinarily the IA inputs) and the internal 25k feedback resistor of each op amp forces that sine wave to appear at the op amp’s inverting inputs (ordinarily the IA gain resistor connections). The impressed AC voltage across each capacitor causes current to flow in each feedback resistor and this creates a voltage at the output of each of the two input op amps. The third IA stage, a differential amplifier, subtracts the two voltages. Thus, when Cx = C1, the output voltage is zero. A higher or lower capacitance at Cx unbalances the bridge and an output results that is proportional to the capacitance difference; a high/low mismatch is indicated by a 180 degree phase difference. A synchronous detector (aka phase- sensitive demodulator) driven by F and low- pass filtered will result in a capacitance bridge DC output that is at null when Cx = C1. The sensitivity of the bridge is proportional to F, both in amplitude and frequency, and to the reference capacitance C1. Higher frequencies result in higher output voltages but the inevitable IA CMRR roll- off at high frequencies will reduce the depth of the null voltage. An advantage of this circuit is that it is quite simple and it allows both capacitors to be ground- referenced. (Circuit is created by Neil P. Albaugh, TI-Tucson)
Capacitance Bridge circuit:
Online Simulation of the “Capacitance Bridge” Circuit
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