In this tutorial video our circuits are counters. The counter is a widely used sequential logic, where the output depends on the sequence of past inputs, and a present value of the input signals.
Binary up Counter circuit
Our first example is a binary up counter circuit.
The counter is constructed from 4, rising edge sensitive D flip-flops counting from 0 to 15.
Flip-flops store the count until the next event, when the clock signal produces a low to high transition.
The least significant bit is QA. The clock source is 1Hz for good interactivity. Following the practice, we assign a short clear pulse by PS at the very beginning before the counting sequence to reset the flip-flops. The full name of the circuit is “asynchronous binary up counter”. Asynchronous, because each flip-flop has a distinctive clock, usually from the previous stage.
Press the Transient Interactive button. As we can see when the clock is changing low to high the indicator turns red, then the least significant flip-flop, U1, will toggle, and this effect propagates through each flip-flop.
This ripple phenomenon causes a delay in the nanosecond domain, but if we don’t care about an immediate result, short transients are acceptable.
Inserting a Prescaler
Before testing our circuit in a real FPGA environment, we need to extend our schematic with FPGA pin connectors.
Since the board doesn’t provide a 1Hz clock, we have to apply a Prescaler which will produce that from the DE10-Lite 50MHz oscillator.
The PreScaler macro has one input named “Clk” and one output named “PClk”.
The clock frequency at Clk input is 100MHz, and it is 1Hz at the PClk output by default.
The Prescaler itself is also a counter. When the counter reaches 25,000,000, the PClk output is toggled so that the frequency of the clock at this output is 1Hz. This is an additional logic to reach slow, human readable operation speed.
The simulation of this circuit must be handled with care. Because the Prescaler has to count to a very large number before the output toggles, we have to slow down this module therefore in the simulation.
Using a Push button
Replace the Clock Source with a Push button.
Let the Push button (PB) generate a high level, when it is pressed and a low level when it is at rest. When the button is pressed, a rising edge occurs on the clock input of the first flip-flop, and the counter outputs will produce the next binary code.
If we press a button once in the real world that may generate a series of pulses. To debounce the buttons, either FPGA logic or external circuit is necessary.
The Terasic FPGA board will eliminate the unwanted glitches by a Schmitt trigger circuit constructing a single low pulse when the button is pressed.
Modifying the circuit for using these buttons
Remove the Push button and the Resistor. These are not necessary because they are on the board and don’t belong to the synthesizable logic. Remove the Pulse Source as well.
The KEY0 button will be connected to the Clear input of the flip-flops, while KEY1 will provide the Clock.
Since we will not need the Logic Indicators we can delete them.
The circuit is ready for the export of Intel Quartus.
Here every time the KEY1 is pressed and released a rising edge is applied to the counter clock input and as a result it counts up by one.
If we press KEY0 then the counter outputs go to zero.
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