Creating Macros from Verilog

Using Hardware Description Languages in TINA, Part 2: Creating Macros from Verilog, now with English voice-over

Hardware Description Languages (HDL) are powerful tools to describe and simulate complex electronic devices.

In this tutorial video we will show how you can create a macro from a Verilog (.v) code and use       in TINA. You can create macros from VHDL, Verilog-A and Verilog-AMS files in a similar way.

Watch our tutorial video to see how  you can create a macro from a Verilog (.v) code and use           in TINA.

 usinghardwaredescriptionlanguagesintinapart2-voiceover-yt

Download the FREE trial demo of TINA Design Suite and get:

  1. One year free access to TINACloud (the cloud-based, multi-language, installation-free online version of TINA now running in your browser anywhere in the world.)
  2. An immediate 20% discount from the offline version of TINA
  3. Free license for your second computer, laptop etc.
Click here to download the FREE trial demo of TINA.

 

www.tina.com

You can also find below the script of the video: 

Using Hardware Description Languages in TINA, Part 2: Creating Macros from Verilog

In this tutorial video we will show how you can create a macro from a Verilog (.v) code and use in TINA. You can create macros from VHDL, Verilog-A and Verilog-AMS files in a similar way.

For example consider the following Verilog interface:

module half_add (A, B, S, C);   

input A, B;

output S, C;

In this case the A,B ports will appear on the left side and the S,C ports will appear on the right side of the macro shape.

Let’s see how to make a macro from the following Verilog code (a half adder):

module half_add(A, B, S, C);  

input A, B;

output S, C;

assign S = A ^ B;

assign C = A & B;

endmodule

Note that this Verilog code is much simpler than the equivalent VHDL code. This is one of the great advantages of Verilog.

The essential Verilog code of the half adder is 2 lines long only.

Let’s demonstrate the details.

Open TINA

Click the Tools menu

Select New Macro Wizard

Type a name for the new macro In our case: Half adder Verilog

Change the Settings from Current circuit to From file

Click the Open icon

Change the file type to .v

Select TINA examples

Select Examples

Click the Verilog folder

Click Open

Select the Half adder Verilog.v file and press Open

Press the Next button to save the macro,

and save the macro into the default Macrolib folder.

Now you can insert the Macro by pressing the Insert button or you can select the “Insert/Macro…” from the menu.

Click the Insert button

The macro will be attached to your cursor. Place it wherever you wish on the workspace.

To see the content of the macro double-click on it and press the Enter Macro button

The content of the macro appears.

Close the TINA HDL Editor window

Let’s test our newly created macro in TINA’s Digital interactive mode along with the previously created VHDL macro

(See Using Hardware Description languages in TINA, part 1)

Let’s open our previously created Half_ Adder VHDL macro.TSC circuit.

Here is the circuit with two High-Low digital switches, one for each of the A,B inputs, and two logic indicators. We will copy the circuit, then we will change the macro into the Half adder Verilog macro

To select the circuit click at the corner of the area to be selected, hold down the left mouse button then move the mouse and release the left mouse button at the opposite corner.

Click the Copy then the Paste button on the toolbar. Your circuit will be attached to your cursor.  Position it by moving the mouse to the required position and press the left mouse button.

Deselect the circuit by clicking an empty spot.

Click the Half adder VHDL macro to be selected then delete it by pressing the Del key on the keyboard.

Click the Insert menu

Select Macro

Select User Macros

Select the Half adder Verilog.TSM, then click Open

The Verilog macro will be attached to your cursor, you can move and insert it into the place of the deleted VHDL macro.

Let’s test the 2 circuits

Select the Digital interactive mode with the narrow “Select Interactive mode” button on the Toolbar

Press the Dig  button

The logic levels of the nodes appear, Red for High. Blue for Low.

The logic indicators will also show the logic level of the outputs in a Red square for High, and empty square for Low.

Both Half_adder circuits work as required.

Share and Enjoy

  • Facebook
  • Twitter
  • Delicious
  • LinkedIn
  • StumbleUpon
  • Add to favorites
  • Email
  • RSS

Using Hardware Description Languages in TINACloud, Part 2: Creating Macros from Verilog

Hardware Description Languages (HDL) are powerful tools to describe and simulate complex electronic devices.

In this tutorial video we will show how you can create a macro from a Verilog (.v) code and use in TINACloud. You can create macros from VHDL, Verilog-A and Verilog-AMS files in a similar way.

Watch our tutorial video to see how  you can create a macro from a Verilog (.v) code and use in TINACloud.

UsinghardwaredescriptionlanguagesinTINACloudpart2-pinterest

Download the FREE trial demo of TINA Design Suite and get:

  1. One year free access to TINACloud (the cloud-based, multi-language, installation-free online version of TINA now running in your browser anywhere in the world.)
  2. An immediate 20% discount from the offline version of TINA
  3. Free license for your second computer, laptop etc.
Click here to download the FREE trial demo of TINA

 

Dr. Michael Koltai

www.tina.com
www.tinacloud.com

Share and Enjoy

  • Facebook
  • Twitter
  • Delicious
  • LinkedIn
  • StumbleUpon
  • Add to favorites
  • Email
  • RSS

Using Hardware Description Languages in TINA, Part 2: Creating Macros from Verilog

Hardware Description Languages (HDL) are powerful tools to describe and simulate complex electronic devices.

In this tutorial video we will show how you can create a macro from a Verilog (.v) code and use       in TINA. You can create macros from VHDL, Verilog-A and Verilog-AMS files in a similar way.

Watch our tutorial video to see how  you can create a macro from a Verilog (.v) code and use           in TINA.

 UsinghardwaredescriptionlanguagesinTINApart2-blog

 

Download the FREE trial demo of TINA Design Suite and get:

  1. One year free access to TINACloud (the cloud-based, multi-language, installation-free online version of TINA now running in your browser anywhere in the world.)
  2. An immediate 20% discount from the offline version of TINA
  3. Free license for your second computer, laptop etc.
Click here to download the FREE trial demo of TINA

 

Michael Koltai
www.tina.com

Share and Enjoy

  • Facebook
  • Twitter
  • Delicious
  • LinkedIn
  • StumbleUpon
  • Add to favorites
  • Email
  • RSS