Creating Macros from a VHDL code
Hardware Description Languages (HDL) are powerful tools to describe and simulate complex electronic devices.
In this tutorial video
we will show how you can create a macro from a VHDL (.vhd) code and use in TINA. You can create macros from Verilog, Verilog-A and Verilog-AMS files in a similar way.
Watch our tutorial video to see how you can create a macro from a VHDL (.vhd) code and use in TINA.
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You can also find below the script of the video:
Using Hardware Description Languages in TINA, Part 1: Creating Macros from a VHDL code
Hardware Description Languages are powerful tools to describe and simulate complex electronic devices. In this tutorial video we will show how you can create a macro from a VHDL code and use in TINA. You can create macros from Verilog, Verilog-A and Verilog-AMS files in a similar way.
You can create a macro from any .vhd , .v , .va, .vams file that contains an entity (interface to the outside world) with its architecture (description of the hardware).
The meaning of the file extensions is as follows:
Files with .vhd extension are VHDL files,
with .v extension are Verilog files,
With .va extension are Verilog-A files and
with .vams extension are Verilog-AMS files.
The ports declared in the interface part will automatically appear in the macro symbol (shape). By default, the input ports of the interface will appear on the left side of the generated macro shape and the output ports of the interface will appear on the right side, but by editing the generated macro you can change this arrangement.
For example consider the following VHDL interface:
ENTITY e_Half_add_entity IS PORT(
A : IN std_logic;
S : OUT std_logic;
C : OUT std_logic;
B : IN std_logic );
END e_Half_add_entity;
In this case the A,B ports will appear on the left side
and the S,C ports will appear on the right side of the macro shape.
Now let’s see how to make a macro from the following VHDL code (a half adder):
LIBRARY ieee, tina;
use ieee.std_logic_1164.all;
use std.textio.all;
USE tina.primitives.all;
————————————
— entity section
————————————
ENTITY e_Half_add_entity IS PORT(
A : IN std_logic;
S : OUT std_logic;
C : OUT std_logic;
B : IN std_logic );
END e_Half_add_entity;
————————————
— architecture section
————————————
ARCHITECTURE a_Half_add_arch of e_Half_add_entity IS
constant delay : time := 20 ns;
BEGIN
S< = (A xor B) after delay;
C< = (A and B) after delay;
END a_Half_add_arch;
Note that the essential code of the half adder is 2 lines long only
Open TINA
Click the Tools menu
Select New Macro Wizard
Type a name for the new macro
In our case: Half_adder_VHDL
Change the Settings from Current circuit to From file
Click the Open icon
Change the file type to VHDL
From the TINA program folder
Select Examples
Open the VHDL folder
Select the Half_adder_VHDL.vhd file and press Open
Press the Next button to save the macro and save the macro into the default Macrolib folder.
You can insert the Macro by pressing the Insert button or you can select the “Insert/Macro” from the menu.
Click the Insert button
To see the content of the macro double-click on it and press the Enter Macro button
The content of the macro appears
Let’s test our newly created macro in TINA’s Digital interactive mode.
To do this, place two High-Low digital switches from the Switches toolbar, one for each of the A,B inputs, and two logic indicators.
Now select the Digital interactive mode with the narrow “Select Interactive mode” button on the Toolbar
then press the Dig button
The logic levels of the nodes appears, Red for High. Blue for Low.
Click the switches to change the input states.
The logic indicators will also show the logic level of the outputs in a
Red square for High, and empty square for Low.
The Half adder circuit works as required.
In our example so far the terminals or pins of the macro were placed automatically.
You can change the automatic pin arrangement of an automatically generated macro by editing its header.
For example the header in the previous example is
————————————
— TINA HDL Macro Description Begin
—
— entity_name:e_half_add_entity;
— arch_name:ignored;
— ports:a,b;s,c;
— Mode:VHDLTyp;
—
— TINA HDL Macro Description End
———————————-
The pin arrangement is determined by the following line:
ports:A,B;S,C;
the ports before the first semicolon (;) are placed on the left while the rest are
placed on the right side of the macro box.
If you change the port line to Ports as follows:
A,B,S;C
A, B, S will be placed on the left side and C on the right side of the macro box.
You can also change the vertical order of the pins by changing the order of the pins in the list.
Let’s see how to convert the previous Macro:
Half_adder_VHDL into a new Macro called: Half_adder_VHDL_modified
Double-click the macro and press the Enter Macro button
Let’s change the ports line to as follows:
ports:A,B,S;C;
Select File
Select Save as
Save the modified code. We will save it under the name: Half_adder_VHDL_modified.vhd
Close the TINA HDL Editor
In the pop-up window the following message appears:
Macro has been modified. Confirm changes?
Click No
Let’s create a new macro with the modified pin arrangement
Click the Tools menu
Select New Macro Wizard Enter the name of the new macro:In our case: Half_adder_VHDL_modified
Change the Settings from Current circuit to From file
Click the Open icon
Invoke the place where your newly created macro is saved. In our case the Downloads folder
Change the file type to VHDL
Select the Half_adder_VHDL_modified file, then click Open
Press the Next button to save the macro,
and save the .TSM file into the default Macrolib folder.
Click the Insert button
The modified macro with the revised pinout version will be attached to your cursor and you can place it anywhere on the workspace
By double-clicking the modified Macro, then pressing the Enter Macro button you can see the content of the macro with the revised pin arrangement