Category: Uncategorized

In this video, first, we will demonstrate how to simulate and synthesize a circuit, displaying prime numbers.  In our circuit, “PIC16F84_Prime_number_generator_Sim_DE10-Lite” we will use a PIC MCU VHDL code.

This circuit calculates prime numbers between 1 and 9999 and shows them on a 4-digit 7-segment display.

The four digits have 32 pins (4 times 8).

Given that the PIC has limited number of lines to control the display, we use an array of registers, which is implemented in the DisplayRegisters VHDL macro.

The Display Registers

The register array is implemented in the DisplayRegisters VHDL macro.

The registers will be written by the PIC chip.

The macro has two inputs: „sel” and „d ”. Both are VHDL standard logic vector connected to the MCU port by buses.

Each registered output goes to the appropriate digit passing the 7-segment codes to the display.

When one line of the sel input goes low, then the 7-segment code, – asserted on the ‘d’ bus by the MCU, – will be stored in the appropriate output register.

Note, that to turn a segment on, the proper pin should be at a high level, because our display is common cathode type.

The PIC16F84 MCU model

In this circuit, the PIC MCU model is written in VHDL.

Next, we will look at the VHDL code which is implemented in the PIC16F84 MCU model. Among others we will check the the top-level entity, then the rtl_pic entity, in which we instantiate and connect the main components.

We will also take a look at the flash_rom entity, where the prime number generator program was loaded.

Next, in line 76 you we check the case construction which describes the ROM functionality.

Finally, we look at the ROM content of the program code written in C, which we have already converted to this VHDL code.

The C code

In the following we will look at the C code.

It is good to know that the project was created, and the program was developed with the free version of Microchip MPLAB IDE and their Microchip XC8 compiler.

Running the simulation using TINACloud’s Schematic Editor

After that we run the simulation in TINACloud Schematic Editor.

It is also possible to follow the transitions of the digital nodes, if you switch to the “Show Digital Node States” option.

Making the main difference in the C code for the synthesis

Next, we return to the MBLAB editor to make the main difference in the C code for the synthesis.

We comment the SIM definition out. Thus, we have defined new constants, like the processor speed in(50 MHz).

This is the oscillator frequency of the DE10-Lite FPGA board.

Testing our circuit with the Terasic DE10-Lite FPGA board

Finally, we will test our circuit, ” PIC16F84 Prime number generator DE10 Lite ” in a real environment using the Terasic DE10-Lite FPGA board.

We will export the VHDL to the Quartus Prime Lite software, compile it and load the resulting bitstream into the Terasic DE10-Lite FPGA development board.

As soon as we finish programming the hardware and we turn the Terasic DE10-Lite board on, we can see the prime numbers written on the display as expected.

Click here to watch our video.

You can learn more about TINA here: www.tina.com

You can learn more about TINACloud here: www.tinacloud.com

In this video, first, we will demonstrate how to simulate and synthesize a circuit displaying prime numbers using a PIC MCU VHDL code.

In the end, we will download the circuit’s configuration file to the Terasic DE10-Lite FPGA board.

PIC16F84 Prime number generator Sim DE10 Lite circuit

This circuit calculates prime numbers between 1 and 9999 and shows them on a 4-digit 7-segment display.

The four digits have 4 times 8, 32 pins.

Since the PIC has limited number of lines to control the display, we use an array of registers to extend its capability.

The register array is implemented in the DisplayRegisters VHDL macro.

The registers will be written by the PIC chip.

The macro has two inputs: „sel” and „d ”.

Both are VHDL standard logic vector connected to the MCU port by buses.

The ‘sel’ lines go to the MCU port RA, the ‘d’ to the port RB.

The hex vectors are the outputs on the port list.

Each registered output goes to the appropriate digit passing the 7-segment codes to the display.

When one line of the sel input goes low, then the 7-segment code, – asserted on the ‘d’ bus by the MCU, – will be stored in the appropriate output register.

Note: To turn a segment on, the proper pin should be at a low level, because our display is of the common cathode type.

The PIC MCU model is written in VHDL.

The VHDL code is the functional model of a PIC16F84 8-bit microcontroller with initialized flash program memory.

CLK1 provides the external 10-MHz clock.

Looking at the VHDL code

Next, we look at the VHDL code using TINA HDL Editor.

Checking the C code

In the following, we will check the program code written in C and converted to this VHDL code.

The project was created, and the program was developed with the free version of Microchip MPLAB IDE and their Microchip XC8 compiler.

We start MBLAB.

First, we define SIM, indicating that we are running a simulation.

The code writes prime numbers between 1 and 9999 with the help of a for loop starting from line 77.

A digit is displayed by writing the representative 7-segment code to the digit’s external register.

Digital circuit simulation

After that, we return to TINA’s Schematic Editor to test our circuit with digital circuit simulation. 

Testing our circuit in a real environment

Making the main difference in the C code for the Synthesis

Then, we’ll open again the MPLAB editor to make the main difference in the C code for the synthesis, like the processor speed (50 MHz). This is the oscillator frequency of the Terasic DE10-Lite FPGA board.

Compiling the project

Next, we compile the project and convert the result – the executable binary – into VHDL. The code is placed in the flash ROM component of our VHDL PIC model.

PIC16F84 Prime number generator DE10 Lite circuit

Finally, we will test our circuit, ” PIC16F84 Prime number generator DE10 Lite ” in a real environment using the Terasic DE10-Lite FPGA board.

We have FPGA pins connected to the segments of the displays and the clock input pin of the PIC MCU.

The com pin of the displays can be left floating as the common anode of the digits is hardwired on the board.

Using the Quartus Prime Lite software to program the hardware

We will export the VHDL to the Quartus Prime Lite software, compile it and load the resulting bitstream into the Terasic DE10-Lite FPGA development board.

Testing the circuit with the Terasic DE10-Lite board

As soon as we finish programming the hardware and we turn the Terasic DE10-Lite board on, we can see the prime numbers written on the display as expected.

Watch our video to learn more.

You can learn more about TINA here: www.tina.com

You can learn more about TINACloud here: www.tinacloud.com

In this video, first, we will demonstrate how to simulate and synthesize a circuit displaying prime numbers using a PIC MCU VHDL code.

Then, we will download the circuit’s configuration file to the Digilent Basys 3 FPGA board.

In our circuit, PIC16F84_Prime_number_generator, the PIC MCU model is written in VHDL. The VHDL code is the functional model of a PIC16F84 8-bit microcontroller with initialized flash program memory.

Looking at the VHDL code in TINACloud’s HDL editor

First, we look at the VHDL code using TINACloud’s HDL Editor.

The top-level entity is rtl_pic.

In the architecture section bound to the rtl_pic entity (line 1828), we instantiate and connect the main components.

These components are the pic_core (line 1830), the 1k*14 bits flash_rom (line 1890), and the PIC16F_RAM file register (line 1898).

From line 1941, the instantiation statements connect these declared components to signals in the architecture (1941–2002), followed by auxiliary VHDL code to support reset and IO updates.

Looking at the C code in the MPLAB editor

Next, we will check the program code, written in C and converted to this VHDL code.

The project was created, and the program was developed with the free version of Microchip MPLAB IDE and their Microchip XC8 compiler.

Let’s open the MPLAB editor.

First, we define SIM, indicating that we are running a simulation (line 3).

If SIM is defined, then other constants are created in lines 6–10.

The XTAL FREQ is the processor frequency for the simulation.

The other parameters are for handling the display.

The code writes prime numbers between 1 and 9999 with the help of a for loop starting from line 98.

If a number is prime, we will generate the digits and display the number.

We have 8 bits to write a digit (PORTB) and 4 bits (PORTA) to select which one to display.

One digit is displayed for a very short time in the millisecond domain.

When a digit is displayed, the other digits are dark. This process is performed from line 107.

Circuit simulation

After that, we return to TINACloud’s Schematic Editor to run digital simulation. Then we go back to the MPLAB editor to make the main difference in the C code for the synthesis, like the processor speed (100 MHz). This is the oscillator frequency of the BASYS3 FPGA board.

Next, we compile the project and convert the result – the executable binary – into VHDL.

The code is placed in the flash ROM component of our VHDL PIC model.

Testing our circuit in a real environment

Finally, we will test our circuit, ” PIC16F84_Prime_number_generator_BASYS3” in a real environment using the Digilent BASYS3 FPGA board.

As expected, we can see the prime numbers written on the display.

Watch our video to learn more.

You can learn more about TINA here: www.tina.com

You can learn more about TINACloud here: www.tinacloud.com

In this video, first, we will demonstrate how to simulate and synthesize a circuit displaying prime numbers using a PIC MCU VHDL code.

In the end, we will download the circuit’s configuration file to the Digilent Basys 3 FPGA board.

In our circuit, PIC16F84_Prime_number_generator, the PIC MCU model is written in VHDL. The VHDL code is the functional model of a PIC16F84 8-bit microcontroller with initialized flash program memory.

Looking at the VHDL code in TINA HDL editor

First, we look at the VHDL code using TINA HDL Editor.

The top-level entity is rtl_pic.

In the architecture section bound to the rtl_pic entity (line 1828), we instantiate and connect the main components.

These components are the pic_core (line 1830), the 1k*14 bits flash_rom (line 1890), and the PIC16F_RAM file register (line 1898).

From line 1941, the instantiation statements connect these declared components to signals in the architecture (1941–2002), followed by auxiliary VHDL code to support reset and IO updates.

Looking at the C code in the MPLAB editor

Next, we will check the program code, written in C and converted to this VHDL code.

The project was created, and the program was developed with the free version of Microchip MPLAB IDE and their Microchip XC8 compiler.

Let’s open the MPLAB editor.

MPLAB editor

First, we define SIM, indicating that we are running a simulation (line 3).

If SIM is defined, then other constants are created in lines 6–10.

The XTAL FREQ is the processor frequency for the simulation.

The other parameters are for handling the display.

The code writes prime numbers between 1 and 9999 with the help of a for loop starting from line 98.

If a number is prime, we will generate the digits and display the number.

We have 8 bits to write a digit (PORTB) and 4 bits (PORTA) to select which one to display.

One digit is displayed for a very short time in the millisecond domain.

When a digit is displayed, the other digits are dark. This process is performed from line 107.

Circuit simulation

Prime number generator circuit. Circuit simulation

After that, we return to TINA’s Schematic Editor to run digital simulation. Then we go back to the MPLAB editor to make the main difference in the C code for the synthesis, like the processor speed (100 MHz). This is the oscillator frequency of the BASYS3 FPGA board. Next, we compile the project and convert the result – the executable binary – into VHDL.

MBLAB editor. Comment the SIM definition

The code is placed in the flash ROM component of our VHDL PIC model.

Testing our circuit in a real environment

Finally, we will test our circuit, ” PIC16F84_Prime_number_generator_BASYS3” in a real environment using the Digilent BASYS3 FPGA board.

As expected, we can see the prime numbers written on the display.

To watch our video click  here.

You can learn more about TINA here: www.tina.com

You can learn more about TINACloud here: www.tinacloud.com

In this video our counter will be based on the VHDL hardware description language.

In our first example, Binary Counter VHDL circuit, we replace the flip flops by a macro which has been written in VHDL.

The macro has two inputs, one for the Clock (clk) and another for the active-low reset (resetn). Clk is connected to the Clock Source, and resetn is connected to the reset Pulse Source.

The four outputs (QA, QB, QC, QD) provide the counter value.

The Binary Counter entity has the same inputs and outputs as the macro shape.

simulation of the binary counter vhdl circuit

We can start the simulation by pressing the Transient Interactive button.

When the clock is changing low to high the indicator turns red then the QA, the least significant bit, toggles. Then, at each rising edge of the clock, the count value goes up by one.

When the Counter reaches the maximum value (binary 1111), the output goes zero.

testing our circuit with the Terasic de10-Lite FPGA board

Before testing our circuit in a real FPGA environment, we need to extend our schematic with FPGA pin connectors. Since the board doesn’t provide a one hertz Clock, we have to apply a Prescaler which will produce that from the DE10-Lite 50 MHz Oscillator.

The prescaler macro has one input named clk and one output named pclk. The clock frequency at clk input is 100 megahertz and it is one hertz at the pclk output by default. To adjust the VHDL code to the board 50 MHz frequency, we modify the ‘Presc < 50000000’ expression constant to 25 million in the Prescaler macro.

The prescaler itself is also a counter. When the counter reaches 25 million the PClk output is toggled, so that the frequency of the clock at this output is 1Hz.

Next, we will place the FPGA Pin connectors. We will attach the first Pin connector to the Clock input before the Prescaler . Then, we will connect 4 more FPGA pin connectors to the 4 outputs of the circuit and assign them to the LEDs: LEDR[0], LEDR[1], LEDR[2] and LEDR[3] .

The counter will be initialized by the FPGA automatically before generating the source files for Intel Quartus-Lite.

Generating the source files for Intel Quartus-Lite. 

First we will add the sources files, the VHDL and the QSF files. The VHDL file is the top-level entity wrapping the underlying components and connections around. The content of the QSF file will tell the software which FPGA pins are to be used for the logic inputs and outputs.

Next, we will compile the files for the FPGA.

As soon as the “Full Compilation was successful” message appears, we will program the device.

You  will see the “Progress bar at 100%, successful” message  and also you will see the counter lights come up counting up in binary.

If the output code reaches the maximum value of 15 the counter next state will be zero.

replacing the clock source with a push button

A counter can count not only a series of pulses but other events too. For example the number of times a push button has been pressed.

To demonstrate this, we will return to our original circuit and replace the the Clock Source with a Push Button. Let the push button PB generate a high level when it is pressed and a low level when it is at rest.

We will also place a Resistor and a Digital High Source. No, we can start the simulation by pressing the TR button. When the button is pressed a rising edge occurs on the clock input of binary counter entity and the counter outputs will produce the next binary code.

implementing this circuit in a real fpga environment using the Terasic DE10-Lite board

First we will remove the Push button, the Resistor and the Pulse Source. Next, we will place 2 FPGA Pin Connectors named as KEY0 and KEY1.

The KEY0 button will be connected to the resetn input of the counter, while KEY1 will provide the clock. We will place four more Pin Connectors and connect them to the Logic Indicators QA, QB, QC, QD. Then we will set their parameters as we did previously: LEDR[0], LEDR[1], LEDR[2] and LEDR[3].

Since we will not need the Logic Indicators we can delete them now.

Every time the KEY1 is pressed and released a rising edge is applied to the counter clock input and as a result it counts up by one.

If we press KEY0 then the Counter outputs go to zero.

To watch our video click  here.

You can learn more about TINA here: www.tina.com

You can learn more about TINACloud here: www.tinacloud.com