# 10. FET Amplifier design

*FET Amplifier design*

We now explore the extension of the FET amplifier analysis presented earlier in this chapter to the design of FET amplifiers. We will attempt to define the unknowns in the design problem, and then develop equations for solving for these unknowns. As in most electronics design, the number of equations will be less than the number of unknowns. The additional constraints are established to meet certain overall objectives (e.g., minimum cost, less variation in performance due to parameter changes).

**10.1 The CS Amplifier**

**10.1 The CS Amplifier**

The design procedure of a CS amplifier is presented in this section. We shall reduce JFET and the depletion MOSFET amplifier design to an organized procedure. While this may appear to

reduce design to a very routine process, you must convince yourself that you understand the origin of each step since several variations may be subsequently required. If all you do to design a CS amplifier is to thoughtlessly “plug in” to the steps we present, you are missing the whole point of this discussion. As an engineer, you are seeking to do things that are *not* routine. Reducing theory to an organized approach is what you will be doing. You will not simply apply the approaches others have already done for you.

Amplifiers are designed to meet gain requirements assuming the desired specifications are within the range of the transistor. The supply voltage, load resistance, voltage gain and input resistance (or current gain) are usually specified. The designer’s job is to select the resistance values *R _{1}*,

*R*,

_{2}*R*, and

_{D}*R*. Refer to Figure 40 as you follow the steps in the procedure. This procedure assumes that a device has been selected and that its characteristics are known.

_{S}First, select a Q-point in the saturation region of the FET characteristic curves. Refer to the curves of Figure 40(b) for an example. This identifies *V _{DSQ}*,

*V*, and

_{GSQ}*I*.

_{DQ}We now solve for the two resistors in the output loop, *R _{S}* and

*R*. Since there are two unknowns, we require two independent equations. We begin by writing the

_{D}*dc*KVL equation around the drain-source loop,

(58)

Solving for the sum of the two resistors yields

(59)

(60)

The resistance, *R _{D}*,

*is the only unknown in this equation.*Solving for

*R*results in a quadratic equation having two solutions, one negative and one positive. If the positive solution results in

_{D}*R*>

_{D}*K*, thus implying a negative

_{1}*R*, a new Q-point must be selected (i.e., restart the design). If the positive solution yields

_{S}*R*<

_{D}*K*, we can proceed.

_{1}Now that *R _{D}* is known, we solve for

*R*using Equation (59) , the drain-to-source loop equation.

_{S}(61)

With *R _{D}* and

*R*known, we need only find

_{S}*R*and

_{1}*R*.

_{2}We begin by rewriting the KVL equation for the gate-source loop.

(62)

The voltage, *V _{GS}*, is of opposite polarity from

*V*. Thus the term

_{DD}*I*must be greater than

_{DQ}R_{S}*V*in magnitude. Otherwise,

_{GSQ}*V*will have the opposite polarity from

_{GG}*V*, which is not possible according to Equation (62).

_{DD}We now solve for *R _{1}* and

*R*assuming that the

_{2}*V*found has the

_{GG}*same polarity*as

*V*. These resistor values are selected by finding the value of

_{DD}*R*from the current-gain equation or from the input resistance. We solve for

_{G}*R*and

_{1}*R*.

_{2}(63)

Suppose now that Equation (62) results in a *V _{GG}* that has the

*opposite polarity*of

*V*. It is not possible to solve for

_{DD}*R*and

_{1}*R*. The practical way to proceed is to let

_{2}*V*= 0 V. Thus, . Since

_{GG}*V*is specified by Equation (62) , the previously calculated value of

_{GG}*R*now needs to be modified.

_{S}In Figure 41, where a capacitor is used to bypass a part of *R _{S}*, we develop the new value of

*R*as follows:

_{S}(64)

The value of *R _{Sdc}* is

*R*+

_{S1}*R*and the value of

_{S2}*R*is

_{Sac}*R*.

_{S1}Now that we have a new *R _{Sdc}*, we must repeat several earlier steps in the design. We once again determine

*R*using KVL for the drain-to-source loop.

_{D}(65)

The design problem now becomes one of calculating both *R _{S1}* and

*R*instead of finding only one source resistor.

_{S2}With a new value for *R _{D}* of

*K*

_{1}

*– R*, we go to the voltage gain expression of Equation (60) with

_{Sdc}*R*used for this

_{Sac}*ac*equation rather than

*R*. The following additional steps must be added to the design procedure:

_{S}We find *R _{Sac}* (which is simply

*R*) from the voltage gain equation

_{S1}(66)

*R _{Sac}* is the only unknown in this equation. Solving for this, we find

(67)

Suppose now that *R _{Sac}* is found to be positive, but less than

*R*. This is the desirable condition since

_{Sdc}(68)

Then our design is complete and

(69)

Suppose that *R _{Sac}* is found to be positive but

*greater*than

*R*. The amplifier cannot be designed with the voltage gain and Q-point as selected. A new Q-point must be selected. If the voltage gain is too high, it may not be possible to effect the design with any Q-point. A different transistor may be needed or the use of two separate stages may be required.

_{Sdc}**10.2 The CD Amplifier**

**10.2 The CD Amplifier**

We now present the design procedure for the CD JFET amplifier. The following quantities are specified: current gain, load resistance, and *V _{DD}*. Input resistance may be specified instead of current gain. Refer to the circuit of Figure 39 as you study the following procedure. Once again, we remind you that the process of reducing the theory to a set of steps is the important part of this discussion – not the actual steps.

First select a Q-point in the center of the FET characteristic curves with the aid of Figure 20 (“Chapter 3: Junction field-effect transistor (JFET)”). This step determines *V _{DSQ}*,

*V*,

_{GSQ}*I*and

_{DQ}*g*.

_{m}We can solve for the resistor connected to the source by writing the *dc* KVL equation around the drain-to-source loop.

(70)

from which we find the *dc* value of *R _{S}*,

(71)

We next find the *ac* value of resistance, *R _{Sac}*, from the rearranged current gain equation, Equation (55).

(72)

where *R _{G}* =

*R*

_{in}_{. }If the input resistance is not specified, let

*R*=

_{Sac}*R*and calculate the input resistance from Equation (72) . If the input resistance is not high enough, it may be necessary to change the Q-point location.

_{Sdc}If *R _{in}* is specified, it is necessary to calculate

*R*from Equation (72). In such cases,

_{Sac}*R*is different from

_{Sac}*R*, so we bypass part of

_{Sdc}*R*with a capacitor.

_{S}We now turn our attention to the input bias circuitry. We determine *V _{GG}* using the equation,

(73)

No phase inversion is produced in a source follower FET amplifier and *V _{GG}* is normally of the same polarity as the supply voltage.

Now that *V _{GG}* is known, we determine the values of

*R*and

_{1}*R*from the Thevenin equivalent of the bias circuitry

_{2}(74)

There is usually enough drain current in an SF to develop the opposite polarity voltage needed to offset the negative voltages required by the JFET gate. Therefore, normal voltage division biasing can be used.

We now return to the problem of specifying the input resistance. We can assume that part of *R _{S}* is bypassed, as in Figure 44, which leads to different values of

*R*and

_{Sac}*R*. We use Equation (71) to solve for

_{Sdc}*R*. Next, we let

_{Sdc}*R*equal the specified value of

_{G}*R*, and use Equation (72) to solve for

_{in}*R*.

_{Sac}If the *R _{Sac}* calculated above is smaller than

*R*, the design is accomplished by bypassing

_{Sdc}*R*with a capacitor. Remember that

_{S2}*R*=

_{Sac}*R*and

_{S1}*R*=

_{Sdc}*R*+

_{S1}*R*. If on the other hand,

_{S2}*R*is larger than

_{Sac}*R*, the Q-point must be moved to a different location. We select a smaller

_{Sdc}*V*thus causing increased voltage to be dropped across

_{DS}*R*+

_{S1}*R*, which makes

_{S2}*R*larger. If

_{Sdc}*V*cannot be reduced sufficiently to make

_{DS}*R*larger than

_{Sdc}*R*, then the amplifier cannot be designed with the given current gain,

_{Sac}*R*, and FET type. One of these three specifications must be changed, or a second amplifier stage must be used to provide the required gain.

_{in}**10.3 The SF Bootstrap Amplifier**

**10.3 The SF Bootstrap Amplifier**

We now examine a variation of the CD amplifier known as the *SF (or CD) bootstrap FET amplifier*. This circuit is a special case of the SF called the *bootstrap circuit *and is illustrated in Figure 45.

Here the bias is developed across only a part of the source resistor. This reduces the need for a capacitor bypass across part of the source resistor and thus attains a much larger input resistance than normally can be attained. This design allows us to take advantage of the high impedance characteristics of the FET without using a high value of gate resistor, *R _{G}*.

The equivalent circuit of Figure 46 is used to evaluate the circuit operation

We assume that *i _{in}* is sufficiently small to approximate the current in

*R*as

_{S2}*i*. The output voltage is then found to be

_{1}(75)

where

(76)

If the assumption about *i _{in}* is not valid, is replaced by the expression

(77)

A KVL equation at the input yields *v _{in}* as follows:

(78)

The current, *i _{1}*, is found from a current-divider relationship,

(79)

Combining Equations (79) and (78) yields,

(80)

A second equation for *v _{in}* is developed around the loop through

*R*and

_{G}*R*as follows.

_{S2}(81)

We eliminate *v _{in}* by setting Equation (80) equal to Equation (81) and solve for

*i*to obtain

_{in}(82)

The input resistance, *R _{in}* =

*v*/

_{in}*i*, is found by dividing Equation (81) by Equation (82) with the result,

_{in}(83)

*R _{G}* is the only unknown in this equation, so we can solve to obtain,

(84)

The current gain is

(85)

We can now use the equations derived earlier along with the observation that *R _{S }*–

*R*=

_{S2 }*R*in order to solve for the current gain.

_{S1}(86)

The voltage gain is

(87)

Note that the denominator in Equation (84) is larger than the numerator, thus showing that *R _{G }*< (

*R*–

_{in}*R*). This proves that a large input resistance can be attained without having the same order of size as

_{S2}*R*.

_{G}