Digital Verilog Simulation
TINA also includes a powerful digital Verilog simulation engine. The advantage of Verilog compared to VHDL that it is easier to learn and understand, however there are more features in VHDL.
TINA can translate the Verilog models and the other digital components to synthesizable VHDL code and, using the Xilinx’s Webpack software, you can generate the bit stream file describing the implementation of the design and then upload it to Xilinx FPGA chips.
The following circuit compares the same full adder circuit using VHDL and Verilog.
The schematic part is the same, only the codes in the macros are different.
You can double click the VHDL or the Verilog macros and press Enter Macro to see the full details and edit the code if you wish:
The essential parts are very similar:
|assign S = A ^ B||S <= (A xor B)|
|assign C = A & B||C <= (A and B)|
If run the Digital Timing Analysis from the Analysis menu. The following diagram will appear:
You can see that the output signals from both models are exactly the same..