SystemVerilog Simulation

Verilog A and AMS Simulation

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SystemVerilog is an extension of the Verilog hardware description language, also included in TINA.
In TINA SystemVerilog is automatically translated to SystemC which can be compiled with MS Visual Studio providing a very fast and optimized code. You can find several circuit examples in the Examples\HDL\SystemVerilog folder of TINA.

SystemVerilog example:

Wave Generator circuit with SystemVerilog
Wave Generator circuit with SystemVerilog-HDL Editor image1
Wave Generator circuit with SystemVerilog-HDL Editor image2
Wave Generator circuit-Transient diagram1
Transient diagram 2-Smoothed signal after low pass analog filtering
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