HDL Debugger: Debugging VHDL and Verilog codes

HDL Debugger: Debugging VHDL and Verilog codes

Debugging HDL programs is especially hard because of the concurrent processes in these languages. 

A great feature in TINA is that the HDL debugger is now integrated.

You can:
  • Execute VHDL and Verilog codes statement-by-statement (Step)
  • Execute subprograms as a single statement (Step Over)
  • Add breakpoints (Toggle Breakpoint), running continuously (Start) and stopping at the breakpoints.
  • Place variables, signals and other objects under the Watches tab and see their value during debugging.
  • View all breakpoints and objects under the Breakpoints and Locals tabs at the bottom of the HDL debugger window.
HDL Debugger, image 1
en English
en Englishde Germanfr Frenches Spanishpt Portugueseru Russianzh-CN Chinese (Simplified)zh-TW Chinese (Traditional)ja Japaneseko Koreanhu Hungarian